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1da177e4 LT |
1 | /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $ |
2 | * linux/include/linux/cyclades.h | |
3 | * | |
4 | * This file was initially written by | |
5 | * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by | |
6 | * Ivan Passos <ivan@cyclades.com>. | |
7 | * | |
8 | * This file contains the general definitions for the cyclades.c driver | |
9 | *$Log: cyclades.h,v $ | |
10 | *Revision 3.1 2002/01/29 11:36:16 henrique | |
11 | *added throttle field on struct cyclades_port to indicate whether the | |
12 | *port is throttled or not | |
13 | * | |
14 | *Revision 3.1 2000/04/19 18:52:52 ivan | |
15 | *converted address fields to unsigned long and added fields for physical | |
16 | *addresses on cyclades_card structure; | |
17 | * | |
18 | *Revision 3.0 1998/11/02 14:20:59 ivan | |
19 | *added nports field on cyclades_card structure; | |
20 | * | |
21 | *Revision 2.5 1998/08/03 16:57:01 ivan | |
22 | *added cyclades_idle_stats structure; | |
23 | * | |
24 | *Revision 2.4 1998/06/01 12:09:53 ivan | |
25 | *removed closing_wait2 from cyclades_port structure; | |
26 | * | |
27 | *Revision 2.3 1998/03/16 18:01:12 ivan | |
28 | *changes in the cyclades_port structure to get it closer to the | |
29 | *standard serial port structure; | |
30 | *added constants for new ioctls; | |
31 | * | |
32 | *Revision 2.2 1998/02/17 16:50:00 ivan | |
33 | *changes in the cyclades_port structure (addition of shutdown_wait and | |
34 | *chip_rev variables); | |
35 | *added constants for new ioctls and for CD1400 rev. numbers. | |
36 | * | |
37 | *Revision 2.1 1997/10/24 16:03:00 ivan | |
38 | *added rflow (which allows enabling the CD1400 special flow control | |
39 | *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to | |
40 | *cyclades_port structure; | |
41 | *added Alpha support | |
42 | * | |
43 | *Revision 2.0 1997/06/30 10:30:00 ivan | |
44 | *added some new doorbell command constants related to IOCTLW and | |
45 | *UART error signaling | |
46 | * | |
47 | *Revision 1.8 1997/06/03 15:30:00 ivan | |
48 | *added constant ZFIRM_HLT | |
49 | *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) | |
50 | * | |
51 | *Revision 1.7 1997/03/26 10:30:00 daniel | |
52 | *new entries at the end of cyclades_port struct to reallocate | |
53 | *variables illegally allocated within card memory. | |
54 | * | |
55 | *Revision 1.6 1996/09/09 18:35:30 bentson | |
56 | *fold in changes for Cyclom-Z -- including structures for | |
57 | *communicating with board as well modest changes to original | |
58 | *structures to support new features. | |
59 | * | |
60 | *Revision 1.5 1995/11/13 21:13:31 bentson | |
61 | *changes suggested by Michael Chastain <mec@duracef.shout.net> | |
62 | *to support use of this file in non-kernel applications | |
63 | * | |
64 | * | |
65 | */ | |
66 | ||
67 | #ifndef _LINUX_CYCLADES_H | |
68 | #define _LINUX_CYCLADES_H | |
69 | ||
70 | struct cyclades_monitor { | |
71 | unsigned long int_count; | |
72 | unsigned long char_count; | |
73 | unsigned long char_max; | |
74 | unsigned long char_last; | |
75 | }; | |
76 | ||
77 | /* | |
78 | * These stats all reflect activity since the device was last initialized. | |
79 | * (i.e., since the port was opened with no other processes already having it | |
80 | * open) | |
81 | */ | |
82 | struct cyclades_idle_stats { | |
83 | time_t in_use; /* Time device has been in use (secs) */ | |
84 | time_t recv_idle; /* Time since last char received (secs) */ | |
85 | time_t xmit_idle; /* Time since last char transmitted (secs) */ | |
86 | unsigned long recv_bytes; /* Bytes received */ | |
87 | unsigned long xmit_bytes; /* Bytes transmitted */ | |
88 | unsigned long overruns; /* Input overruns */ | |
89 | unsigned long frame_errs; /* Input framing errors */ | |
90 | unsigned long parity_errs; /* Input parity errors */ | |
91 | }; | |
92 | ||
93 | #define CYCLADES_MAGIC 0x4359 | |
94 | ||
95 | #define CYGETMON 0x435901 | |
96 | #define CYGETTHRESH 0x435902 | |
97 | #define CYSETTHRESH 0x435903 | |
98 | #define CYGETDEFTHRESH 0x435904 | |
99 | #define CYSETDEFTHRESH 0x435905 | |
100 | #define CYGETTIMEOUT 0x435906 | |
101 | #define CYSETTIMEOUT 0x435907 | |
102 | #define CYGETDEFTIMEOUT 0x435908 | |
103 | #define CYSETDEFTIMEOUT 0x435909 | |
104 | #define CYSETRFLOW 0x43590a | |
105 | #define CYGETRFLOW 0x43590b | |
106 | #define CYSETRTSDTR_INV 0x43590c | |
107 | #define CYGETRTSDTR_INV 0x43590d | |
108 | #define CYZSETPOLLCYCLE 0x43590e | |
109 | #define CYZGETPOLLCYCLE 0x43590f | |
110 | #define CYGETCD1400VER 0x435910 | |
111 | #define CYGETCARDINFO 0x435911 | |
112 | #define CYSETWAIT 0x435912 | |
113 | #define CYGETWAIT 0x435913 | |
114 | ||
115 | /*************** CYCLOM-Z ADDITIONS ***************/ | |
116 | ||
117 | #define CZIOC ('M' << 8) | |
118 | #define CZ_NBOARDS (CZIOC|0xfa) | |
119 | #define CZ_BOOT_START (CZIOC|0xfb) | |
120 | #define CZ_BOOT_DATA (CZIOC|0xfc) | |
121 | #define CZ_BOOT_END (CZIOC|0xfd) | |
122 | #define CZ_TEST (CZIOC|0xfe) | |
123 | ||
124 | #define CZ_DEF_POLL (HZ/25) | |
125 | ||
126 | #define MAX_BOARD 4 /* Max number of boards */ | |
127 | #define MAX_DEV 256 /* Max number of ports total */ | |
128 | #define CYZ_MAX_SPEED 921600 | |
129 | ||
130 | #define CYZ_FIFO_SIZE 16 | |
131 | ||
132 | #define CYZ_BOOT_NWORDS 0x100 | |
133 | struct CYZ_BOOT_CTRL { | |
134 | unsigned short nboard; | |
135 | int status[MAX_BOARD]; | |
136 | int nchannel[MAX_BOARD]; | |
137 | int fw_rev[MAX_BOARD]; | |
138 | unsigned long offset; | |
139 | unsigned long data[CYZ_BOOT_NWORDS]; | |
140 | }; | |
141 | ||
142 | ||
143 | #ifndef DP_WINDOW_SIZE | |
144 | /* #include "cyclomz.h" */ | |
145 | /****************** ****************** *******************/ | |
146 | /* | |
147 | * The data types defined below are used in all ZFIRM interface | |
148 | * data structures. They accomodate differences between HW | |
149 | * architectures and compilers. | |
150 | */ | |
151 | ||
152 | #if defined(__alpha__) | |
153 | typedef unsigned long ucdouble; /* 64 bits, unsigned */ | |
154 | typedef unsigned int uclong; /* 32 bits, unsigned */ | |
155 | #else | |
156 | typedef unsigned long uclong; /* 32 bits, unsigned */ | |
157 | #endif | |
158 | typedef unsigned short ucshort; /* 16 bits, unsigned */ | |
159 | typedef unsigned char ucchar; /* 8 bits, unsigned */ | |
160 | ||
161 | /* | |
162 | * Memory Window Sizes | |
163 | */ | |
164 | ||
165 | #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ | |
166 | #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and | |
167 | 8Zo V.2 */ | |
168 | #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ | |
169 | ||
170 | /* | |
171 | * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver | |
172 | * normally will access only interested on the fpga_id, fpga_version, | |
173 | * start_cpu and stop_cpu. | |
174 | */ | |
175 | ||
176 | struct CUSTOM_REG { | |
177 | uclong fpga_id; /* FPGA Identification Register */ | |
178 | uclong fpga_version; /* FPGA Version Number Register */ | |
179 | uclong cpu_start; /* CPU start Register (write) */ | |
180 | uclong cpu_stop; /* CPU stop Register (write) */ | |
181 | uclong misc_reg; /* Miscelaneous Register */ | |
182 | uclong idt_mode; /* IDT mode Register */ | |
183 | uclong uart_irq_status; /* UART IRQ status Register */ | |
184 | uclong clear_timer0_irq; /* Clear timer interrupt Register */ | |
185 | uclong clear_timer1_irq; /* Clear timer interrupt Register */ | |
186 | uclong clear_timer2_irq; /* Clear timer interrupt Register */ | |
187 | uclong test_register; /* Test Register */ | |
188 | uclong test_count; /* Test Count Register */ | |
189 | uclong timer_select; /* Timer select register */ | |
190 | uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ | |
191 | uclong ram_wait_state; /* RAM wait-state Register */ | |
192 | uclong uart_wait_state; /* UART wait-state Register */ | |
193 | uclong timer_wait_state; /* timer wait-state Register */ | |
194 | uclong ack_wait_state; /* ACK wait State Register */ | |
195 | }; | |
196 | ||
197 | /* | |
198 | * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime | |
199 | * registers. This structure can be used to access the 9060 registers | |
200 | * (memory mapped). | |
201 | */ | |
202 | ||
203 | struct RUNTIME_9060 { | |
204 | uclong loc_addr_range; /* 00h - Local Address Range */ | |
205 | uclong loc_addr_base; /* 04h - Local Address Base */ | |
206 | uclong loc_arbitr; /* 08h - Local Arbitration */ | |
207 | uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */ | |
208 | uclong loc_rom_range; /* 10h - Local ROM Range */ | |
209 | uclong loc_rom_base; /* 14h - Local ROM Base */ | |
210 | uclong loc_bus_descr; /* 18h - Local Bus descriptor */ | |
211 | uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */ | |
212 | uclong loc_base_mst; /* 20h - Local Base for Master PCI */ | |
213 | uclong loc_range_io; /* 24h - Local Range for Master IO */ | |
214 | uclong pci_base_mst; /* 28h - PCI Base for Master PCI */ | |
215 | uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */ | |
216 | uclong filler1; /* 30h */ | |
217 | uclong filler2; /* 34h */ | |
218 | uclong filler3; /* 38h */ | |
219 | uclong filler4; /* 3Ch */ | |
220 | uclong mail_box_0; /* 40h - Mail Box 0 */ | |
221 | uclong mail_box_1; /* 44h - Mail Box 1 */ | |
222 | uclong mail_box_2; /* 48h - Mail Box 2 */ | |
223 | uclong mail_box_3; /* 4Ch - Mail Box 3 */ | |
224 | uclong filler5; /* 50h */ | |
225 | uclong filler6; /* 54h */ | |
226 | uclong filler7; /* 58h */ | |
227 | uclong filler8; /* 5Ch */ | |
228 | uclong pci_doorbell; /* 60h - PCI to Local Doorbell */ | |
229 | uclong loc_doorbell; /* 64h - Local to PCI Doorbell */ | |
230 | uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */ | |
231 | uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ | |
232 | }; | |
233 | ||
234 | /* Values for the Local Base Address re-map register */ | |
235 | ||
236 | #define WIN_RAM 0x00000001L /* set the sliding window to RAM */ | |
237 | #define WIN_CREG 0x14000001L /* set the window to custom Registers */ | |
238 | ||
239 | /* Values timer select registers */ | |
240 | ||
241 | #define TIMER_BY_1M 0x00 /* clock divided by 1M */ | |
242 | #define TIMER_BY_256K 0x01 /* clock divided by 256k */ | |
243 | #define TIMER_BY_128K 0x02 /* clock divided by 128k */ | |
244 | #define TIMER_BY_32K 0x03 /* clock divided by 32k */ | |
245 | ||
246 | /****************** ****************** *******************/ | |
247 | #endif | |
248 | ||
249 | #ifndef ZFIRM_ID | |
250 | /* #include "zfwint.h" */ | |
251 | /****************** ****************** *******************/ | |
252 | /* | |
253 | * This file contains the definitions for interfacing with the | |
254 | * Cyclom-Z ZFIRM Firmware. | |
255 | */ | |
256 | ||
257 | /* General Constant definitions */ | |
258 | ||
259 | #define MAX_CHAN 64 /* max number of channels per board */ | |
260 | ||
261 | /* firmware id structure (set after boot) */ | |
262 | ||
263 | #define ID_ADDRESS 0x00000180L /* signature/pointer address */ | |
264 | #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ | |
265 | #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ | |
266 | #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ | |
267 | ||
268 | #define ZF_TINACT_DEF 1000 /* default inactivity timeout | |
269 | (1000 ms) */ | |
270 | #define ZF_TINACT ZF_TINACT_DEF | |
271 | ||
272 | struct FIRM_ID { | |
273 | uclong signature; /* ZFIRM/U signature */ | |
274 | uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */ | |
275 | }; | |
276 | ||
277 | /* Op. System id */ | |
278 | ||
279 | #define C_OS_LINUX 0x00000030 /* generic Linux system */ | |
280 | ||
281 | /* channel op_mode */ | |
282 | ||
283 | #define C_CH_DISABLE 0x00000000 /* channel is disabled */ | |
284 | #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ | |
285 | #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ | |
286 | #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ | |
287 | #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ | |
288 | ||
289 | /* comm_parity - parity */ | |
290 | ||
291 | #define C_PR_NONE 0x00000000 /* None */ | |
292 | #define C_PR_ODD 0x00000001 /* Odd */ | |
293 | #define C_PR_EVEN 0x00000002 /* Even */ | |
294 | #define C_PR_MARK 0x00000004 /* Mark */ | |
295 | #define C_PR_SPACE 0x00000008 /* Space */ | |
296 | #define C_PR_PARITY 0x000000ff | |
297 | ||
298 | #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ | |
299 | #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ | |
300 | ||
301 | /* comm_data_l - data length and stop bits */ | |
302 | ||
303 | #define C_DL_CS5 0x00000001 | |
304 | #define C_DL_CS6 0x00000002 | |
305 | #define C_DL_CS7 0x00000004 | |
306 | #define C_DL_CS8 0x00000008 | |
307 | #define C_DL_CS 0x0000000f | |
308 | #define C_DL_1STOP 0x00000010 | |
309 | #define C_DL_15STOP 0x00000020 | |
310 | #define C_DL_2STOP 0x00000040 | |
311 | #define C_DL_STOP 0x000000f0 | |
312 | ||
313 | /* interrupt enabling/status */ | |
314 | ||
315 | #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ | |
316 | #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ | |
317 | #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ | |
318 | #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ | |
319 | #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ | |
320 | #define C_IN_MDCD 0x00000100 /* modem DCD change */ | |
321 | #define C_IN_MDSR 0x00000200 /* modem DSR change */ | |
322 | #define C_IN_MRI 0x00000400 /* modem RI change */ | |
323 | #define C_IN_MCTS 0x00000800 /* modem CTS change */ | |
324 | #define C_IN_RXBRK 0x00001000 /* Break received */ | |
325 | #define C_IN_PR_ERROR 0x00002000 /* parity error */ | |
326 | #define C_IN_FR_ERROR 0x00004000 /* frame error */ | |
327 | #define C_IN_OVR_ERROR 0x00008000 /* overrun error */ | |
328 | #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ | |
329 | #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ | |
330 | #define C_IN_MRTS 0x00040000 /* modem RTS drop */ | |
331 | #define C_IN_ICHAR 0x00080000 | |
332 | ||
333 | /* flow control */ | |
334 | ||
335 | #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ | |
336 | #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ | |
337 | #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ | |
338 | #define C_FL_SWFLOW 0x0000000f | |
339 | ||
340 | /* flow status */ | |
341 | ||
342 | #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ | |
343 | #define C_FS_SENDING 0x00000001 /* UART is sending data */ | |
344 | #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ | |
345 | ||
346 | /* rs_control/rs_status RS-232 signals */ | |
347 | ||
348 | #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in | |
349 | IOCTLM command */ | |
350 | #define C_RS_RTS 0x00000001 /* RTS */ | |
351 | #define C_RS_DTR 0x00000004 /* DTR */ | |
352 | #define C_RS_DCD 0x00000100 /* CD */ | |
353 | #define C_RS_DSR 0x00000200 /* DSR */ | |
354 | #define C_RS_RI 0x00000400 /* RI */ | |
355 | #define C_RS_CTS 0x00000800 /* CTS */ | |
356 | ||
357 | /* commands Host <-> Board */ | |
358 | ||
359 | #define C_CM_RESET 0x01 /* reset/flush buffers */ | |
360 | #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ | |
361 | #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ | |
362 | #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ | |
363 | #define C_CM_SENDXOFF 0x10 /* send Xoff */ | |
364 | #define C_CM_SENDXON 0x11 /* send Xon */ | |
365 | #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ | |
366 | #define C_CM_SENDBRK 0x41 /* send break */ | |
367 | #define C_CM_INTBACK 0x42 /* Interrupt back */ | |
368 | #define C_CM_SET_BREAK 0x43 /* Tx break on */ | |
369 | #define C_CM_CLR_BREAK 0x44 /* Tx break off */ | |
370 | #define C_CM_CMD_DONE 0x45 /* Previous command done */ | |
371 | #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ | |
372 | #define C_CM_TINACT 0x51 /* set inactivity detection */ | |
373 | #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ | |
374 | #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ | |
375 | #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ | |
376 | #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ | |
377 | #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ | |
378 | #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ | |
379 | #define C_CM_Q_ENABLE 0x58 /* enables queue access from the | |
380 | driver */ | |
381 | #define C_CM_Q_DISABLE 0x59 /* disables queue access from the | |
382 | driver */ | |
383 | ||
384 | #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ | |
385 | #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ | |
386 | #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ | |
387 | #define C_CM_RXNNDT 0x63 /* rx no new data timeout */ | |
388 | #define C_CM_TXFEMPTY 0x64 | |
389 | #define C_CM_ICHAR 0x65 | |
390 | #define C_CM_MDCD 0x70 /* modem DCD change */ | |
391 | #define C_CM_MDSR 0x71 /* modem DSR change */ | |
392 | #define C_CM_MRI 0x72 /* modem RI change */ | |
393 | #define C_CM_MCTS 0x73 /* modem CTS change */ | |
394 | #define C_CM_MRTS 0x74 /* modem RTS drop */ | |
395 | #define C_CM_RXBRK 0x84 /* Break received */ | |
396 | #define C_CM_PR_ERROR 0x85 /* Parity error */ | |
397 | #define C_CM_FR_ERROR 0x86 /* Frame error */ | |
398 | #define C_CM_OVR_ERROR 0x87 /* Overrun error */ | |
399 | #define C_CM_RXOFL 0x88 /* RX buffer overflow */ | |
400 | #define C_CM_CMDERROR 0x90 /* command error */ | |
401 | #define C_CM_FATAL 0x91 /* fatal error */ | |
402 | #define C_CM_HW_RESET 0x92 /* reset board */ | |
403 | ||
404 | /* | |
405 | * CH_CTRL - This per port structure contains all parameters | |
406 | * that control an specific port. It can be seen as the | |
407 | * configuration registers of a "super-serial-controller". | |
408 | */ | |
409 | ||
410 | struct CH_CTRL { | |
411 | uclong op_mode; /* operation mode */ | |
412 | uclong intr_enable; /* interrupt masking */ | |
413 | uclong sw_flow; /* SW flow control */ | |
414 | uclong flow_status; /* output flow status */ | |
415 | uclong comm_baud; /* baud rate - numerically specified */ | |
416 | uclong comm_parity; /* parity */ | |
417 | uclong comm_data_l; /* data length/stop */ | |
418 | uclong comm_flags; /* other flags */ | |
419 | uclong hw_flow; /* HW flow control */ | |
420 | uclong rs_control; /* RS-232 outputs */ | |
421 | uclong rs_status; /* RS-232 inputs */ | |
422 | uclong flow_xon; /* xon char */ | |
423 | uclong flow_xoff; /* xoff char */ | |
424 | uclong hw_overflow; /* hw overflow counter */ | |
425 | uclong sw_overflow; /* sw overflow counter */ | |
426 | uclong comm_error; /* frame/parity error counter */ | |
427 | uclong ichar; | |
428 | uclong filler[7]; | |
429 | }; | |
430 | ||
431 | ||
432 | /* | |
433 | * BUF_CTRL - This per channel structure contains | |
434 | * all Tx and Rx buffer control for a given channel. | |
435 | */ | |
436 | ||
437 | struct BUF_CTRL { | |
438 | uclong flag_dma; /* buffers are in Host memory */ | |
439 | uclong tx_bufaddr; /* address of the tx buffer */ | |
440 | uclong tx_bufsize; /* tx buffer size */ | |
441 | uclong tx_threshold; /* tx low water mark */ | |
442 | uclong tx_get; /* tail index tx buf */ | |
443 | uclong tx_put; /* head index tx buf */ | |
444 | uclong rx_bufaddr; /* address of the rx buffer */ | |
445 | uclong rx_bufsize; /* rx buffer size */ | |
446 | uclong rx_threshold; /* rx high water mark */ | |
447 | uclong rx_get; /* tail index rx buf */ | |
448 | uclong rx_put; /* head index rx buf */ | |
449 | uclong filler[5]; /* filler to align structures */ | |
450 | }; | |
451 | ||
452 | /* | |
453 | * BOARD_CTRL - This per board structure contains all global | |
454 | * control fields related to the board. | |
455 | */ | |
456 | ||
457 | struct BOARD_CTRL { | |
458 | ||
459 | /* static info provided by the on-board CPU */ | |
460 | uclong n_channel; /* number of channels */ | |
461 | uclong fw_version; /* firmware version */ | |
462 | ||
463 | /* static info provided by the driver */ | |
464 | uclong op_system; /* op_system id */ | |
465 | uclong dr_version; /* driver version */ | |
466 | ||
467 | /* board control area */ | |
468 | uclong inactivity; /* inactivity control */ | |
469 | ||
470 | /* host to FW commands */ | |
471 | uclong hcmd_channel; /* channel number */ | |
472 | uclong hcmd_param; /* pointer to parameters */ | |
473 | ||
474 | /* FW to Host commands */ | |
475 | uclong fwcmd_channel; /* channel number */ | |
476 | uclong fwcmd_param; /* pointer to parameters */ | |
477 | uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */ | |
478 | ||
479 | /* filler so the structures are aligned */ | |
480 | uclong filler[6]; | |
481 | }; | |
482 | ||
483 | /* Host Interrupt Queue */ | |
484 | ||
485 | #define QUEUE_SIZE (10*MAX_CHAN) | |
486 | ||
487 | struct INT_QUEUE { | |
488 | unsigned char intr_code[QUEUE_SIZE]; | |
489 | unsigned long channel[QUEUE_SIZE]; | |
490 | unsigned long param[QUEUE_SIZE]; | |
491 | unsigned long put; | |
492 | unsigned long get; | |
493 | }; | |
494 | ||
495 | /* | |
496 | * ZFW_CTRL - This is the data structure that includes all other | |
497 | * data structures used by the Firmware. | |
498 | */ | |
499 | ||
500 | struct ZFW_CTRL { | |
501 | struct BOARD_CTRL board_ctrl; | |
502 | struct CH_CTRL ch_ctrl[MAX_CHAN]; | |
503 | struct BUF_CTRL buf_ctrl[MAX_CHAN]; | |
504 | }; | |
505 | ||
506 | /****************** ****************** *******************/ | |
507 | #endif | |
508 | ||
509 | /* Per card data structure */ | |
510 | struct resource; | |
511 | struct cyclades_card { | |
512 | unsigned long base_phys; | |
513 | unsigned long ctl_phys; | |
514 | void __iomem *base_addr; | |
515 | void __iomem *ctl_addr; | |
516 | int irq; | |
517 | int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ | |
518 | int first_line; /* minor number of first channel on card */ | |
519 | int nports; /* Number of ports in the card */ | |
520 | int bus_index; /* address shift - 0 for ISA, 1 for PCI */ | |
521 | int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ | |
522 | struct pci_dev *pdev; | |
523 | #ifdef __KERNEL__ | |
524 | spinlock_t card_lock; | |
525 | #else | |
526 | unsigned long filler; | |
527 | #endif | |
528 | }; | |
529 | ||
530 | struct cyclades_chip { | |
531 | int filler; | |
532 | }; | |
533 | ||
534 | ||
535 | #ifdef __KERNEL__ | |
536 | ||
537 | /*************************************** | |
538 | * Memory access functions/macros * | |
539 | * (required to support Alpha systems) * | |
540 | ***************************************/ | |
541 | ||
542 | #define cy_writeb(port,val) {writeb((val),(port)); mb();} | |
543 | #define cy_writew(port,val) {writew((val),(port)); mb();} | |
544 | #define cy_writel(port,val) {writel((val),(port)); mb();} | |
545 | ||
546 | #define cy_readb(port) readb(port) | |
547 | #define cy_readw(port) readw(port) | |
548 | #define cy_readl(port) readl(port) | |
549 | ||
550 | /* | |
551 | * Statistics counters | |
552 | */ | |
553 | struct cyclades_icount { | |
554 | __u32 cts, dsr, rng, dcd, tx, rx; | |
555 | __u32 frame, parity, overrun, brk; | |
556 | __u32 buf_overrun; | |
557 | }; | |
558 | ||
559 | /* | |
560 | * This is our internal structure for each serial port's state. | |
561 | * | |
562 | * Many fields are paralleled by the structure used by the serial_struct | |
563 | * structure. | |
564 | * | |
565 | * For definitions of the flags field, see tty.h | |
566 | */ | |
567 | ||
568 | struct cyclades_port { | |
569 | int magic; | |
570 | int card; | |
571 | int line; | |
572 | int flags; /* defined in tty.h */ | |
573 | int type; /* UART type */ | |
574 | struct tty_struct *tty; | |
575 | int read_status_mask; | |
576 | int ignore_status_mask; | |
577 | int timeout; | |
578 | int xmit_fifo_size; | |
579 | int cor1,cor2,cor3,cor4,cor5; | |
580 | int tbpr,tco,rbpr,rco; | |
581 | int baud; | |
582 | int rflow; | |
583 | int rtsdtr_inv; | |
584 | int chip_rev; | |
585 | int custom_divisor; | |
586 | int x_char; /* to be pushed out ASAP */ | |
587 | int close_delay; | |
588 | unsigned short closing_wait; | |
589 | unsigned long event; | |
590 | unsigned long last_active; | |
591 | int count; /* # of fd on device */ | |
592 | int breakon; | |
593 | int breakoff; | |
594 | int blocked_open; /* # of blocked opens */ | |
595 | unsigned char *xmit_buf; | |
596 | int xmit_head; | |
597 | int xmit_tail; | |
598 | int xmit_cnt; | |
599 | int default_threshold; | |
600 | int default_timeout; | |
601 | unsigned long jiffies[3]; | |
602 | unsigned long rflush_count; | |
603 | struct cyclades_monitor mon; | |
604 | struct cyclades_idle_stats idle_stats; | |
605 | struct cyclades_icount icount; | |
606 | struct work_struct tqueue; | |
607 | wait_queue_head_t open_wait; | |
608 | wait_queue_head_t close_wait; | |
609 | wait_queue_head_t shutdown_wait; | |
610 | wait_queue_head_t delta_msr_wait; | |
611 | int throttle; | |
612 | }; | |
613 | ||
614 | /* | |
615 | * Events are used to schedule things to happen at timer-interrupt | |
616 | * time, instead of at cy interrupt time. | |
617 | */ | |
618 | #define Cy_EVENT_READ_PROCESS 0 | |
619 | #define Cy_EVENT_WRITE_WAKEUP 1 | |
620 | #define Cy_EVENT_HANGUP 2 | |
621 | #define Cy_EVENT_BREAK 3 | |
622 | #define Cy_EVENT_OPEN_WAKEUP 4 | |
623 | #define Cy_EVENT_SHUTDOWN_WAKEUP 5 | |
624 | #define Cy_EVENT_DELTA_WAKEUP 6 | |
625 | #define Cy_EVENT_Z_RX_FULL 7 | |
626 | ||
627 | #define CLOSING_WAIT_DELAY 30*HZ | |
628 | #define CY_CLOSING_WAIT_NONE 65535 | |
629 | #define CY_CLOSING_WAIT_INF 0 | |
630 | ||
631 | ||
632 | #define CyMAX_CHIPS_PER_CARD 8 | |
633 | #define CyMAX_CHAR_FIFO 12 | |
634 | #define CyPORTS_PER_CHIP 4 | |
635 | #define CD1400_MAX_SPEED 115200 | |
636 | ||
637 | #define CyISA_Ywin 0x2000 | |
638 | ||
639 | #define CyPCI_Ywin 0x4000 | |
640 | #define CyPCI_Yctl 0x80 | |
641 | #define CyPCI_Zctl CTRL_WINDOW_SIZE | |
642 | #define CyPCI_Zwin 0x80000 | |
643 | #define CyPCI_Ze_win (2 * CyPCI_Zwin) | |
644 | ||
645 | #define PCI_DEVICE_ID_MASK 0x06 | |
646 | ||
647 | /**** CD1400 registers ****/ | |
648 | ||
649 | #define CD1400_REV_G 0x46 | |
650 | #define CD1400_REV_J 0x48 | |
651 | ||
652 | #define CyRegSize 0x0400 | |
653 | #define Cy_HwReset 0x1400 | |
654 | #define Cy_ClrIntr 0x1800 | |
655 | #define Cy_EpldRev 0x1e00 | |
656 | ||
657 | /* Global Registers */ | |
658 | ||
659 | #define CyGFRCR (0x40*2) | |
660 | #define CyRevE (44) | |
661 | #define CyCAR (0x68*2) | |
662 | #define CyCHAN_0 (0x00) | |
663 | #define CyCHAN_1 (0x01) | |
664 | #define CyCHAN_2 (0x02) | |
665 | #define CyCHAN_3 (0x03) | |
666 | #define CyGCR (0x4B*2) | |
667 | #define CyCH0_SERIAL (0x00) | |
668 | #define CyCH0_PARALLEL (0x80) | |
669 | #define CySVRR (0x67*2) | |
670 | #define CySRModem (0x04) | |
671 | #define CySRTransmit (0x02) | |
672 | #define CySRReceive (0x01) | |
673 | #define CyRICR (0x44*2) | |
674 | #define CyTICR (0x45*2) | |
675 | #define CyMICR (0x46*2) | |
676 | #define CyICR0 (0x00) | |
677 | #define CyICR1 (0x01) | |
678 | #define CyICR2 (0x02) | |
679 | #define CyICR3 (0x03) | |
680 | #define CyRIR (0x6B*2) | |
681 | #define CyTIR (0x6A*2) | |
682 | #define CyMIR (0x69*2) | |
683 | #define CyIRDirEq (0x80) | |
684 | #define CyIRBusy (0x40) | |
685 | #define CyIRUnfair (0x20) | |
686 | #define CyIRContext (0x1C) | |
687 | #define CyIRChannel (0x03) | |
688 | #define CyPPR (0x7E*2) | |
689 | #define CyCLOCK_20_1MS (0x27) | |
690 | #define CyCLOCK_25_1MS (0x31) | |
691 | #define CyCLOCK_25_5MS (0xf4) | |
692 | #define CyCLOCK_60_1MS (0x75) | |
693 | #define CyCLOCK_60_2MS (0xea) | |
694 | ||
695 | /* Virtual Registers */ | |
696 | ||
697 | #define CyRIVR (0x43*2) | |
698 | #define CyTIVR (0x42*2) | |
699 | #define CyMIVR (0x41*2) | |
700 | #define CyIVRMask (0x07) | |
701 | #define CyIVRRxEx (0x07) | |
702 | #define CyIVRRxOK (0x03) | |
703 | #define CyIVRTxOK (0x02) | |
704 | #define CyIVRMdmOK (0x01) | |
705 | #define CyTDR (0x63*2) | |
706 | #define CyRDSR (0x62*2) | |
707 | #define CyTIMEOUT (0x80) | |
708 | #define CySPECHAR (0x70) | |
709 | #define CyBREAK (0x08) | |
710 | #define CyPARITY (0x04) | |
711 | #define CyFRAME (0x02) | |
712 | #define CyOVERRUN (0x01) | |
713 | #define CyMISR (0x4C*2) | |
714 | /* see CyMCOR_ and CyMSVR_ for bits*/ | |
715 | #define CyEOSRR (0x60*2) | |
716 | ||
717 | /* Channel Registers */ | |
718 | ||
719 | #define CyLIVR (0x18*2) | |
720 | #define CyMscsr (0x01) | |
721 | #define CyTdsr (0x02) | |
722 | #define CyRgdsr (0x03) | |
723 | #define CyRedsr (0x07) | |
724 | #define CyCCR (0x05*2) | |
725 | /* Format 1 */ | |
726 | #define CyCHAN_RESET (0x80) | |
727 | #define CyCHIP_RESET (0x81) | |
728 | #define CyFlushTransFIFO (0x82) | |
729 | /* Format 2 */ | |
730 | #define CyCOR_CHANGE (0x40) | |
731 | #define CyCOR1ch (0x02) | |
732 | #define CyCOR2ch (0x04) | |
733 | #define CyCOR3ch (0x08) | |
734 | /* Format 3 */ | |
735 | #define CySEND_SPEC_1 (0x21) | |
736 | #define CySEND_SPEC_2 (0x22) | |
737 | #define CySEND_SPEC_3 (0x23) | |
738 | #define CySEND_SPEC_4 (0x24) | |
739 | /* Format 4 */ | |
740 | #define CyCHAN_CTL (0x10) | |
741 | #define CyDIS_RCVR (0x01) | |
742 | #define CyENB_RCVR (0x02) | |
743 | #define CyDIS_XMTR (0x04) | |
744 | #define CyENB_XMTR (0x08) | |
745 | #define CySRER (0x06*2) | |
746 | #define CyMdmCh (0x80) | |
747 | #define CyRxData (0x10) | |
748 | #define CyTxRdy (0x04) | |
749 | #define CyTxMpty (0x02) | |
750 | #define CyNNDT (0x01) | |
751 | #define CyCOR1 (0x08*2) | |
752 | #define CyPARITY_NONE (0x00) | |
753 | #define CyPARITY_0 (0x20) | |
754 | #define CyPARITY_1 (0xA0) | |
755 | #define CyPARITY_E (0x40) | |
756 | #define CyPARITY_O (0xC0) | |
757 | #define Cy_1_STOP (0x00) | |
758 | #define Cy_1_5_STOP (0x04) | |
759 | #define Cy_2_STOP (0x08) | |
760 | #define Cy_5_BITS (0x00) | |
761 | #define Cy_6_BITS (0x01) | |
762 | #define Cy_7_BITS (0x02) | |
763 | #define Cy_8_BITS (0x03) | |
764 | #define CyCOR2 (0x09*2) | |
765 | #define CyIXM (0x80) | |
766 | #define CyTxIBE (0x40) | |
767 | #define CyETC (0x20) | |
768 | #define CyAUTO_TXFL (0x60) | |
769 | #define CyLLM (0x10) | |
770 | #define CyRLM (0x08) | |
771 | #define CyRtsAO (0x04) | |
772 | #define CyCtsAE (0x02) | |
773 | #define CyDsrAE (0x01) | |
774 | #define CyCOR3 (0x0A*2) | |
775 | #define CySPL_CH_DRANGE (0x80) /* special character detect range */ | |
776 | #define CySPL_CH_DET1 (0x40) /* enable special character detection | |
777 | on SCHR4-SCHR3 */ | |
778 | #define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */ | |
779 | #define CySPL_CH_DET2 (0x10) /* Enable special character detection | |
780 | on SCHR2-SCHR1 */ | |
781 | #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ | |
782 | #define CyCOR4 (0x1E*2) | |
783 | #define CyCOR5 (0x1F*2) | |
784 | #define CyCCSR (0x0B*2) | |
785 | #define CyRxEN (0x80) | |
786 | #define CyRxFloff (0x40) | |
787 | #define CyRxFlon (0x20) | |
788 | #define CyTxEN (0x08) | |
789 | #define CyTxFloff (0x04) | |
790 | #define CyTxFlon (0x02) | |
791 | #define CyRDCR (0x0E*2) | |
792 | #define CySCHR1 (0x1A*2) | |
793 | #define CySCHR2 (0x1B*2) | |
794 | #define CySCHR3 (0x1C*2) | |
795 | #define CySCHR4 (0x1D*2) | |
796 | #define CySCRL (0x22*2) | |
797 | #define CySCRH (0x23*2) | |
798 | #define CyLNC (0x24*2) | |
799 | #define CyMCOR1 (0x15*2) | |
800 | #define CyMCOR2 (0x16*2) | |
801 | #define CyRTPR (0x21*2) | |
802 | #define CyMSVR1 (0x6C*2) | |
803 | #define CyMSVR2 (0x6D*2) | |
804 | #define CyANY_DELTA (0xF0) | |
805 | #define CyDSR (0x80) | |
806 | #define CyCTS (0x40) | |
807 | #define CyRI (0x20) | |
808 | #define CyDCD (0x10) | |
809 | #define CyDTR (0x02) | |
810 | #define CyRTS (0x01) | |
811 | #define CyPVSR (0x6F*2) | |
812 | #define CyRBPR (0x78*2) | |
813 | #define CyRCOR (0x7C*2) | |
814 | #define CyTBPR (0x72*2) | |
815 | #define CyTCOR (0x76*2) | |
816 | ||
817 | /* Custom Registers */ | |
818 | ||
819 | #define CyPLX_VER (0x3400) | |
820 | #define PLX_9050 0x0b | |
821 | #define PLX_9060 0x0c | |
822 | #define PLX_9080 0x0d | |
823 | ||
824 | /***************************************************************************/ | |
825 | ||
826 | #endif /* __KERNEL__ */ | |
827 | #endif /* _LINUX_CYCLADES_H */ |