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e941759c ML |
1 | /* |
2 | * Fence mechanism for dma-buf to allow for asynchronous dma access | |
3 | * | |
4 | * Copyright (C) 2012 Canonical Ltd | |
5 | * Copyright (C) 2012 Texas Instruments | |
6 | * | |
7 | * Authors: | |
8 | * Rob Clark <robdclark@gmail.com> | |
9 | * Maarten Lankhorst <maarten.lankhorst@canonical.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License version 2 as published by | |
13 | * the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | */ | |
20 | ||
f54d1867 CW |
21 | #ifndef __LINUX_DMA_FENCE_H |
22 | #define __LINUX_DMA_FENCE_H | |
e941759c ML |
23 | |
24 | #include <linux/err.h> | |
25 | #include <linux/wait.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/bitops.h> | |
28 | #include <linux/kref.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/printk.h> | |
3c3b177a | 31 | #include <linux/rcupdate.h> |
e941759c | 32 | |
f54d1867 CW |
33 | struct dma_fence; |
34 | struct dma_fence_ops; | |
35 | struct dma_fence_cb; | |
e941759c ML |
36 | |
37 | /** | |
f54d1867 | 38 | * struct dma_fence - software synchronization primitive |
e941759c | 39 | * @refcount: refcount for this fence |
f54d1867 | 40 | * @ops: dma_fence_ops associated with this fence |
3c3b177a | 41 | * @rcu: used for releasing fence with kfree_rcu |
e941759c ML |
42 | * @cb_list: list of all callbacks to call |
43 | * @lock: spin_lock_irqsave used for locking | |
44 | * @context: execution context this fence belongs to, returned by | |
f54d1867 | 45 | * dma_fence_context_alloc() |
e941759c ML |
46 | * @seqno: the sequence number of this fence inside the execution context, |
47 | * can be compared to decide which fence would be signaled later. | |
f54d1867 | 48 | * @flags: A mask of DMA_FENCE_FLAG_* defined below |
e941759c | 49 | * @timestamp: Timestamp when the fence was signaled. |
a009e975 | 50 | * @error: Optional, only valid if < 0, must be set before calling |
f54d1867 | 51 | * dma_fence_signal, indicates that the fence has completed with an error. |
e941759c ML |
52 | * |
53 | * the flags member must be manipulated and read using the appropriate | |
54 | * atomic ops (bit_*), so taking the spinlock will not be needed most | |
55 | * of the time. | |
56 | * | |
f54d1867 | 57 | * DMA_FENCE_FLAG_SIGNALED_BIT - fence is already signaled |
76250f2b | 58 | * DMA_FENCE_FLAG_TIMESTAMP_BIT - timestamp recorded for fence signaling |
f54d1867 CW |
59 | * DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT - enable_signaling might have been called |
60 | * DMA_FENCE_FLAG_USER_BITS - start of the unused bits, can be used by the | |
e941759c ML |
61 | * implementer of the fence for its own purposes. Can be used in different |
62 | * ways by different fence implementers, so do not rely on this. | |
63 | * | |
3590d50e | 64 | * Since atomic bitops are used, this is not guaranteed to be the case. |
f54d1867 | 65 | * Particularly, if the bit was set, but dma_fence_signal was called right |
e941759c | 66 | * before this bit was set, it would have been able to set the |
f54d1867 CW |
67 | * DMA_FENCE_FLAG_SIGNALED_BIT, before enable_signaling was called. |
68 | * Adding a check for DMA_FENCE_FLAG_SIGNALED_BIT after setting | |
69 | * DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT closes this race, and makes sure that | |
70 | * after dma_fence_signal was called, any enable_signaling call will have either | |
e941759c ML |
71 | * been completed, or never called at all. |
72 | */ | |
f54d1867 | 73 | struct dma_fence { |
e941759c | 74 | struct kref refcount; |
f54d1867 | 75 | const struct dma_fence_ops *ops; |
3c3b177a | 76 | struct rcu_head rcu; |
e941759c ML |
77 | struct list_head cb_list; |
78 | spinlock_t *lock; | |
76bf0db5 CK |
79 | u64 context; |
80 | unsigned seqno; | |
e941759c ML |
81 | unsigned long flags; |
82 | ktime_t timestamp; | |
a009e975 | 83 | int error; |
e941759c ML |
84 | }; |
85 | ||
f54d1867 CW |
86 | enum dma_fence_flag_bits { |
87 | DMA_FENCE_FLAG_SIGNALED_BIT, | |
76250f2b | 88 | DMA_FENCE_FLAG_TIMESTAMP_BIT, |
f54d1867 CW |
89 | DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
90 | DMA_FENCE_FLAG_USER_BITS, /* must always be last member */ | |
e941759c ML |
91 | }; |
92 | ||
f54d1867 CW |
93 | typedef void (*dma_fence_func_t)(struct dma_fence *fence, |
94 | struct dma_fence_cb *cb); | |
e941759c ML |
95 | |
96 | /** | |
2c269b09 DV |
97 | * struct dma_fence_cb - callback for dma_fence_add_callback() |
98 | * @node: used by dma_fence_add_callback() to append this struct to fence::cb_list | |
f54d1867 | 99 | * @func: dma_fence_func_t to call |
e941759c | 100 | * |
2c269b09 | 101 | * This struct will be initialized by dma_fence_add_callback(), additional |
f54d1867 | 102 | * data can be passed along by embedding dma_fence_cb in another struct. |
e941759c | 103 | */ |
f54d1867 | 104 | struct dma_fence_cb { |
e941759c | 105 | struct list_head node; |
f54d1867 | 106 | dma_fence_func_t func; |
e941759c ML |
107 | }; |
108 | ||
109 | /** | |
f54d1867 | 110 | * struct dma_fence_ops - operations implemented for fence |
e941759c | 111 | * |
e941759c | 112 | */ |
f54d1867 | 113 | struct dma_fence_ops { |
2c269b09 DV |
114 | /** |
115 | * @get_driver_name: | |
116 | * | |
117 | * Returns the driver name. This is a callback to allow drivers to | |
118 | * compute the name at runtime, without having it to store permanently | |
119 | * for each fence, or build a cache of some sort. | |
120 | * | |
121 | * This callback is mandatory. | |
122 | */ | |
f54d1867 | 123 | const char * (*get_driver_name)(struct dma_fence *fence); |
2c269b09 DV |
124 | |
125 | /** | |
126 | * @get_timeline_name: | |
127 | * | |
128 | * Return the name of the context this fence belongs to. This is a | |
129 | * callback to allow drivers to compute the name at runtime, without | |
130 | * having it to store permanently for each fence, or build a cache of | |
131 | * some sort. | |
132 | * | |
133 | * This callback is mandatory. | |
134 | */ | |
f54d1867 | 135 | const char * (*get_timeline_name)(struct dma_fence *fence); |
2c269b09 DV |
136 | |
137 | /** | |
138 | * @enable_signaling: | |
139 | * | |
140 | * Enable software signaling of fence. | |
141 | * | |
142 | * For fence implementations that have the capability for hw->hw | |
143 | * signaling, they can implement this op to enable the necessary | |
144 | * interrupts, or insert commands into cmdstream, etc, to avoid these | |
145 | * costly operations for the common case where only hw->hw | |
146 | * synchronization is required. This is called in the first | |
147 | * dma_fence_wait() or dma_fence_add_callback() path to let the fence | |
148 | * implementation know that there is another driver waiting on the | |
149 | * signal (ie. hw->sw case). | |
150 | * | |
151 | * This function can be called from atomic context, but not | |
152 | * from irq context, so normal spinlocks can be used. | |
153 | * | |
154 | * A return value of false indicates the fence already passed, | |
155 | * or some failure occurred that made it impossible to enable | |
156 | * signaling. True indicates successful enabling. | |
157 | * | |
158 | * &dma_fence.error may be set in enable_signaling, but only when false | |
159 | * is returned. | |
160 | * | |
161 | * Since many implementations can call dma_fence_signal() even when before | |
162 | * @enable_signaling has been called there's a race window, where the | |
163 | * dma_fence_signal() might result in the final fence reference being | |
164 | * released and its memory freed. To avoid this, implementations of this | |
165 | * callback should grab their own reference using dma_fence_get(), to be | |
166 | * released when the fence is signalled (through e.g. the interrupt | |
167 | * handler). | |
168 | * | |
51f170a5 | 169 | * This callback is mandatory. |
2c269b09 | 170 | */ |
f54d1867 | 171 | bool (*enable_signaling)(struct dma_fence *fence); |
2c269b09 DV |
172 | |
173 | /** | |
174 | * @signaled: | |
175 | * | |
176 | * Peek whether the fence is signaled, as a fastpath optimization for | |
177 | * e.g. dma_fence_wait() or dma_fence_add_callback(). Note that this | |
178 | * callback does not need to make any guarantees beyond that a fence | |
179 | * once indicates as signalled must always return true from this | |
180 | * callback. This callback may return false even if the fence has | |
181 | * completed already, in this case information hasn't propogated throug | |
182 | * the system yet. See also dma_fence_is_signaled(). | |
183 | * | |
184 | * May set &dma_fence.error if returning true. | |
185 | * | |
186 | * This callback is optional. | |
187 | */ | |
f54d1867 | 188 | bool (*signaled)(struct dma_fence *fence); |
2c269b09 DV |
189 | |
190 | /** | |
191 | * @wait: | |
192 | * | |
51f170a5 | 193 | * Custom wait implementation, or dma_fence_default_wait. |
2c269b09 | 194 | * |
51f170a5 DV |
195 | * Must not be NULL, set to dma_fence_default_wait for default implementation. |
196 | * the dma_fence_default_wait implementation should work for any fence, as long | |
197 | * as enable_signaling works correctly. | |
2c269b09 DV |
198 | * |
199 | * Must return -ERESTARTSYS if the wait is intr = true and the wait was | |
200 | * interrupted, and remaining jiffies if fence has signaled, or 0 if wait | |
201 | * timed out. Can also return other error values on custom implementations, | |
202 | * which should be treated as if the fence is signaled. For example a hardware | |
203 | * lockup could be reported like that. | |
204 | * | |
51f170a5 | 205 | * This callback is mandatory. |
2c269b09 | 206 | */ |
f54d1867 CW |
207 | signed long (*wait)(struct dma_fence *fence, |
208 | bool intr, signed long timeout); | |
2c269b09 DV |
209 | |
210 | /** | |
211 | * @release: | |
212 | * | |
213 | * Called on destruction of fence to release additional resources. | |
214 | * Can be called from irq context. This callback is optional. If it is | |
215 | * NULL, then dma_fence_free() is instead called as the default | |
216 | * implementation. | |
217 | */ | |
f54d1867 CW |
218 | void (*release)(struct dma_fence *fence); |
219 | ||
51f170a5 DV |
220 | /** |
221 | * @fill_driver_data: | |
222 | * | |
223 | * Callback to fill in free-form debug info. | |
224 | * | |
225 | * Returns amount of bytes filled, or negative error on failure. | |
226 | * | |
227 | * This callback is optional. | |
228 | */ | |
229 | int (*fill_driver_data)(struct dma_fence *fence, void *data, int size); | |
230 | ||
2c269b09 DV |
231 | /** |
232 | * @fence_value_str: | |
233 | * | |
234 | * Callback to fill in free-form debug info specific to this fence, like | |
235 | * the sequence number. | |
236 | * | |
237 | * This callback is optional. | |
238 | */ | |
f54d1867 | 239 | void (*fence_value_str)(struct dma_fence *fence, char *str, int size); |
2c269b09 DV |
240 | |
241 | /** | |
242 | * @timeline_value_str: | |
243 | * | |
244 | * Fills in the current value of the timeline as a string, like the | |
51f170a5 DV |
245 | * sequence number. This should match what @fill_driver_data prints for |
246 | * the most recently signalled fence (assuming no delayed signalling). | |
2c269b09 | 247 | */ |
f54d1867 CW |
248 | void (*timeline_value_str)(struct dma_fence *fence, |
249 | char *str, int size); | |
e941759c ML |
250 | }; |
251 | ||
f54d1867 CW |
252 | void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, |
253 | spinlock_t *lock, u64 context, unsigned seqno); | |
e941759c | 254 | |
f54d1867 CW |
255 | void dma_fence_release(struct kref *kref); |
256 | void dma_fence_free(struct dma_fence *fence); | |
e941759c | 257 | |
4be05420 | 258 | /** |
f54d1867 | 259 | * dma_fence_put - decreases refcount of the fence |
2c269b09 | 260 | * @fence: fence to reduce refcount of |
4be05420 | 261 | */ |
f54d1867 | 262 | static inline void dma_fence_put(struct dma_fence *fence) |
4be05420 CW |
263 | { |
264 | if (fence) | |
f54d1867 | 265 | kref_put(&fence->refcount, dma_fence_release); |
4be05420 CW |
266 | } |
267 | ||
e941759c | 268 | /** |
f54d1867 | 269 | * dma_fence_get - increases refcount of the fence |
2c269b09 | 270 | * @fence: fence to increase refcount of |
e941759c ML |
271 | * |
272 | * Returns the same fence, with refcount increased by 1. | |
273 | */ | |
f54d1867 | 274 | static inline struct dma_fence *dma_fence_get(struct dma_fence *fence) |
e941759c ML |
275 | { |
276 | if (fence) | |
277 | kref_get(&fence->refcount); | |
278 | return fence; | |
279 | } | |
280 | ||
3c3b177a | 281 | /** |
f54d1867 CW |
282 | * dma_fence_get_rcu - get a fence from a reservation_object_list with |
283 | * rcu read lock | |
2c269b09 | 284 | * @fence: fence to increase refcount of |
3c3b177a ML |
285 | * |
286 | * Function returns NULL if no refcount could be obtained, or the fence. | |
287 | */ | |
f54d1867 | 288 | static inline struct dma_fence *dma_fence_get_rcu(struct dma_fence *fence) |
3c3b177a ML |
289 | { |
290 | if (kref_get_unless_zero(&fence->refcount)) | |
291 | return fence; | |
292 | else | |
293 | return NULL; | |
294 | } | |
295 | ||
e941759c | 296 | /** |
f54d1867 | 297 | * dma_fence_get_rcu_safe - acquire a reference to an RCU tracked fence |
2c269b09 | 298 | * @fencep: pointer to fence to increase refcount of |
4be05420 CW |
299 | * |
300 | * Function returns NULL if no refcount could be obtained, or the fence. | |
301 | * This function handles acquiring a reference to a fence that may be | |
5f0d5a3a | 302 | * reallocated within the RCU grace period (such as with SLAB_TYPESAFE_BY_RCU), |
4be05420 CW |
303 | * so long as the caller is using RCU on the pointer to the fence. |
304 | * | |
305 | * An alternative mechanism is to employ a seqlock to protect a bunch of | |
306 | * fences, such as used by struct reservation_object. When using a seqlock, | |
307 | * the seqlock must be taken before and checked after a reference to the | |
308 | * fence is acquired (as shown here). | |
309 | * | |
310 | * The caller is required to hold the RCU read lock. | |
e941759c | 311 | */ |
f54d1867 | 312 | static inline struct dma_fence * |
5f72db59 | 313 | dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) |
e941759c | 314 | { |
4be05420 | 315 | do { |
f54d1867 | 316 | struct dma_fence *fence; |
4be05420 CW |
317 | |
318 | fence = rcu_dereference(*fencep); | |
f8e0731d | 319 | if (!fence) |
4be05420 CW |
320 | return NULL; |
321 | ||
f8e0731d CK |
322 | if (!dma_fence_get_rcu(fence)) |
323 | continue; | |
324 | ||
f54d1867 | 325 | /* The atomic_inc_not_zero() inside dma_fence_get_rcu() |
4be05420 CW |
326 | * provides a full memory barrier upon success (such as now). |
327 | * This is paired with the write barrier from assigning | |
328 | * to the __rcu protected fence pointer so that if that | |
329 | * pointer still matches the current fence, we know we | |
330 | * have successfully acquire a reference to it. If it no | |
331 | * longer matches, we are holding a reference to some other | |
332 | * reallocated pointer. This is possible if the allocator | |
5f0d5a3a | 333 | * is using a freelist like SLAB_TYPESAFE_BY_RCU where the |
4be05420 CW |
334 | * fence remains valid for the RCU grace period, but it |
335 | * may be reallocated. When using such allocators, we are | |
336 | * responsible for ensuring the reference we get is to | |
337 | * the right fence, as below. | |
338 | */ | |
339 | if (fence == rcu_access_pointer(*fencep)) | |
340 | return rcu_pointer_handoff(fence); | |
341 | ||
f54d1867 | 342 | dma_fence_put(fence); |
4be05420 | 343 | } while (1); |
e941759c ML |
344 | } |
345 | ||
f54d1867 CW |
346 | int dma_fence_signal(struct dma_fence *fence); |
347 | int dma_fence_signal_locked(struct dma_fence *fence); | |
348 | signed long dma_fence_default_wait(struct dma_fence *fence, | |
349 | bool intr, signed long timeout); | |
350 | int dma_fence_add_callback(struct dma_fence *fence, | |
351 | struct dma_fence_cb *cb, | |
352 | dma_fence_func_t func); | |
353 | bool dma_fence_remove_callback(struct dma_fence *fence, | |
354 | struct dma_fence_cb *cb); | |
355 | void dma_fence_enable_sw_signaling(struct dma_fence *fence); | |
e941759c ML |
356 | |
357 | /** | |
f54d1867 CW |
358 | * dma_fence_is_signaled_locked - Return an indication if the fence |
359 | * is signaled yet. | |
2c269b09 | 360 | * @fence: the fence to check |
e941759c ML |
361 | * |
362 | * Returns true if the fence was already signaled, false if not. Since this | |
363 | * function doesn't enable signaling, it is not guaranteed to ever return | |
2c269b09 DV |
364 | * true if dma_fence_add_callback(), dma_fence_wait() or |
365 | * dma_fence_enable_sw_signaling() haven't been called before. | |
e941759c | 366 | * |
2c269b09 DV |
367 | * This function requires &dma_fence.lock to be held. |
368 | * | |
369 | * See also dma_fence_is_signaled(). | |
e941759c ML |
370 | */ |
371 | static inline bool | |
f54d1867 | 372 | dma_fence_is_signaled_locked(struct dma_fence *fence) |
e941759c | 373 | { |
f54d1867 | 374 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
375 | return true; |
376 | ||
377 | if (fence->ops->signaled && fence->ops->signaled(fence)) { | |
f54d1867 | 378 | dma_fence_signal_locked(fence); |
e941759c ML |
379 | return true; |
380 | } | |
381 | ||
382 | return false; | |
383 | } | |
384 | ||
385 | /** | |
f54d1867 | 386 | * dma_fence_is_signaled - Return an indication if the fence is signaled yet. |
2c269b09 | 387 | * @fence: the fence to check |
e941759c ML |
388 | * |
389 | * Returns true if the fence was already signaled, false if not. Since this | |
390 | * function doesn't enable signaling, it is not guaranteed to ever return | |
2c269b09 DV |
391 | * true if dma_fence_add_callback(), dma_fence_wait() or |
392 | * dma_fence_enable_sw_signaling() haven't been called before. | |
e941759c | 393 | * |
f54d1867 | 394 | * It's recommended for seqno fences to call dma_fence_signal when the |
e941759c ML |
395 | * operation is complete, it makes it possible to prevent issues from |
396 | * wraparound between time of issue and time of use by checking the return | |
397 | * value of this function before calling hardware-specific wait instructions. | |
2c269b09 DV |
398 | * |
399 | * See also dma_fence_is_signaled_locked(). | |
e941759c ML |
400 | */ |
401 | static inline bool | |
f54d1867 | 402 | dma_fence_is_signaled(struct dma_fence *fence) |
e941759c | 403 | { |
f54d1867 | 404 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
405 | return true; |
406 | ||
407 | if (fence->ops->signaled && fence->ops->signaled(fence)) { | |
f54d1867 | 408 | dma_fence_signal(fence); |
e941759c ML |
409 | return true; |
410 | } | |
411 | ||
412 | return false; | |
413 | } | |
414 | ||
81114776 CW |
415 | /** |
416 | * __dma_fence_is_later - return if f1 is chronologically later than f2 | |
2c269b09 DV |
417 | * @f1: the first fence's seqno |
418 | * @f2: the second fence's seqno from the same context | |
81114776 CW |
419 | * |
420 | * Returns true if f1 is chronologically later than f2. Both fences must be | |
421 | * from the same context, since a seqno is not common across contexts. | |
422 | */ | |
423 | static inline bool __dma_fence_is_later(u32 f1, u32 f2) | |
424 | { | |
425 | return (int)(f1 - f2) > 0; | |
426 | } | |
427 | ||
6c455ac1 | 428 | /** |
f54d1867 | 429 | * dma_fence_is_later - return if f1 is chronologically later than f2 |
2c269b09 DV |
430 | * @f1: the first fence from the same context |
431 | * @f2: the second fence from the same context | |
6c455ac1 CK |
432 | * |
433 | * Returns true if f1 is chronologically later than f2. Both fences must be | |
434 | * from the same context, since a seqno is not re-used across contexts. | |
435 | */ | |
f54d1867 CW |
436 | static inline bool dma_fence_is_later(struct dma_fence *f1, |
437 | struct dma_fence *f2) | |
6c455ac1 CK |
438 | { |
439 | if (WARN_ON(f1->context != f2->context)) | |
440 | return false; | |
441 | ||
81114776 | 442 | return __dma_fence_is_later(f1->seqno, f2->seqno); |
6c455ac1 CK |
443 | } |
444 | ||
e941759c | 445 | /** |
f54d1867 | 446 | * dma_fence_later - return the chronologically later fence |
2c269b09 DV |
447 | * @f1: the first fence from the same context |
448 | * @f2: the second fence from the same context | |
e941759c ML |
449 | * |
450 | * Returns NULL if both fences are signaled, otherwise the fence that would be | |
451 | * signaled last. Both fences must be from the same context, since a seqno is | |
452 | * not re-used across contexts. | |
453 | */ | |
f54d1867 CW |
454 | static inline struct dma_fence *dma_fence_later(struct dma_fence *f1, |
455 | struct dma_fence *f2) | |
e941759c ML |
456 | { |
457 | if (WARN_ON(f1->context != f2->context)) | |
458 | return NULL; | |
459 | ||
460 | /* | |
f54d1867 CW |
461 | * Can't check just DMA_FENCE_FLAG_SIGNALED_BIT here, it may never |
462 | * have been set if enable_signaling wasn't called, and enabling that | |
463 | * here is overkill. | |
e941759c | 464 | */ |
f54d1867 CW |
465 | if (dma_fence_is_later(f1, f2)) |
466 | return dma_fence_is_signaled(f1) ? NULL : f1; | |
6c455ac1 | 467 | else |
f54d1867 | 468 | return dma_fence_is_signaled(f2) ? NULL : f2; |
e941759c ML |
469 | } |
470 | ||
d6c99f4b CW |
471 | /** |
472 | * dma_fence_get_status_locked - returns the status upon completion | |
2c269b09 | 473 | * @fence: the dma_fence to query |
d6c99f4b CW |
474 | * |
475 | * Drivers can supply an optional error status condition before they signal | |
476 | * the fence (to indicate whether the fence was completed due to an error | |
477 | * rather than success). The value of the status condition is only valid | |
478 | * if the fence has been signaled, dma_fence_get_status_locked() first checks | |
479 | * the signal state before reporting the error status. | |
480 | * | |
481 | * Returns 0 if the fence has not yet been signaled, 1 if the fence has | |
482 | * been signaled without an error condition, or a negative error code | |
483 | * if the fence has been completed in err. | |
484 | */ | |
485 | static inline int dma_fence_get_status_locked(struct dma_fence *fence) | |
486 | { | |
487 | if (dma_fence_is_signaled_locked(fence)) | |
a009e975 | 488 | return fence->error ?: 1; |
d6c99f4b CW |
489 | else |
490 | return 0; | |
491 | } | |
492 | ||
493 | int dma_fence_get_status(struct dma_fence *fence); | |
494 | ||
a009e975 CW |
495 | /** |
496 | * dma_fence_set_error - flag an error condition on the fence | |
2c269b09 DV |
497 | * @fence: the dma_fence |
498 | * @error: the error to store | |
a009e975 CW |
499 | * |
500 | * Drivers can supply an optional error status condition before they signal | |
501 | * the fence, to indicate that the fence was completed due to an error | |
502 | * rather than success. This must be set before signaling (so that the value | |
503 | * is visible before any waiters on the signal callback are woken). This | |
504 | * helper exists to help catching erroneous setting of #dma_fence.error. | |
505 | */ | |
506 | static inline void dma_fence_set_error(struct dma_fence *fence, | |
507 | int error) | |
508 | { | |
6ce31263 DV |
509 | WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)); |
510 | WARN_ON(error >= 0 || error < -MAX_ERRNO); | |
a009e975 CW |
511 | |
512 | fence->error = error; | |
513 | } | |
514 | ||
f54d1867 | 515 | signed long dma_fence_wait_timeout(struct dma_fence *, |
a519435a | 516 | bool intr, signed long timeout); |
f54d1867 CW |
517 | signed long dma_fence_wait_any_timeout(struct dma_fence **fences, |
518 | uint32_t count, | |
7392b4bb | 519 | bool intr, signed long timeout, |
520 | uint32_t *idx); | |
e941759c ML |
521 | |
522 | /** | |
f54d1867 | 523 | * dma_fence_wait - sleep until the fence gets signaled |
2c269b09 DV |
524 | * @fence: the fence to wait on |
525 | * @intr: if true, do an interruptible wait | |
e941759c ML |
526 | * |
527 | * This function will return -ERESTARTSYS if interrupted by a signal, | |
528 | * or 0 if the fence was signaled. Other error values may be | |
529 | * returned on custom implementations. | |
530 | * | |
531 | * Performs a synchronous wait on this fence. It is assumed the caller | |
532 | * directly or indirectly holds a reference to the fence, otherwise the | |
533 | * fence might be freed before return, resulting in undefined behavior. | |
2c269b09 DV |
534 | * |
535 | * See also dma_fence_wait_timeout() and dma_fence_wait_any_timeout(). | |
e941759c | 536 | */ |
f54d1867 | 537 | static inline signed long dma_fence_wait(struct dma_fence *fence, bool intr) |
e941759c ML |
538 | { |
539 | signed long ret; | |
540 | ||
f54d1867 | 541 | /* Since dma_fence_wait_timeout cannot timeout with |
e941759c ML |
542 | * MAX_SCHEDULE_TIMEOUT, only valid return values are |
543 | * -ERESTARTSYS and MAX_SCHEDULE_TIMEOUT. | |
544 | */ | |
f54d1867 | 545 | ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); |
e941759c ML |
546 | |
547 | return ret < 0 ? ret : 0; | |
548 | } | |
549 | ||
f54d1867 | 550 | u64 dma_fence_context_alloc(unsigned num); |
e941759c | 551 | |
f54d1867 | 552 | #define DMA_FENCE_TRACE(f, fmt, args...) \ |
e941759c | 553 | do { \ |
f54d1867 CW |
554 | struct dma_fence *__ff = (f); \ |
555 | if (IS_ENABLED(CONFIG_DMA_FENCE_TRACE)) \ | |
76bf0db5 | 556 | pr_info("f %llu#%u: " fmt, \ |
e941759c ML |
557 | __ff->context, __ff->seqno, ##args); \ |
558 | } while (0) | |
559 | ||
f54d1867 | 560 | #define DMA_FENCE_WARN(f, fmt, args...) \ |
e941759c | 561 | do { \ |
f54d1867 | 562 | struct dma_fence *__ff = (f); \ |
76bf0db5 | 563 | pr_warn("f %llu#%u: " fmt, __ff->context, __ff->seqno, \ |
e941759c ML |
564 | ##args); \ |
565 | } while (0) | |
566 | ||
f54d1867 | 567 | #define DMA_FENCE_ERR(f, fmt, args...) \ |
e941759c | 568 | do { \ |
f54d1867 | 569 | struct dma_fence *__ff = (f); \ |
76bf0db5 | 570 | pr_err("f %llu#%u: " fmt, __ff->context, __ff->seqno, \ |
e941759c ML |
571 | ##args); \ |
572 | } while (0) | |
573 | ||
f54d1867 | 574 | #endif /* __LINUX_DMA_FENCE_H */ |