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96532bab RD |
1 | #ifndef _LINUX_DMA_MAPPING_H |
2 | #define _LINUX_DMA_MAPPING_H | |
1da177e4 | 3 | |
002edb6f | 4 | #include <linux/sizes.h> |
842fa69f | 5 | #include <linux/string.h> |
1da177e4 LT |
6 | #include <linux/device.h> |
7 | #include <linux/err.h> | |
e1c7e324 | 8 | #include <linux/dma-debug.h> |
b7f080cf | 9 | #include <linux/dma-direction.h> |
f0402a26 | 10 | #include <linux/scatterlist.h> |
e1c7e324 CH |
11 | #include <linux/kmemcheck.h> |
12 | #include <linux/bug.h> | |
1da177e4 | 13 | |
00085f1e KK |
14 | /** |
15 | * List of possible attributes associated with a DMA mapping. The semantics | |
16 | * of each attribute should be defined in Documentation/DMA-attributes.txt. | |
17 | * | |
18 | * DMA_ATTR_WRITE_BARRIER: DMA to a memory region with this attribute | |
19 | * forces all pending DMA writes to complete. | |
20 | */ | |
21 | #define DMA_ATTR_WRITE_BARRIER (1UL << 0) | |
22 | /* | |
23 | * DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping | |
24 | * may be weakly ordered, that is that reads and writes may pass each other. | |
25 | */ | |
26 | #define DMA_ATTR_WEAK_ORDERING (1UL << 1) | |
27 | /* | |
28 | * DMA_ATTR_WRITE_COMBINE: Specifies that writes to the mapping may be | |
29 | * buffered to improve performance. | |
30 | */ | |
31 | #define DMA_ATTR_WRITE_COMBINE (1UL << 2) | |
32 | /* | |
33 | * DMA_ATTR_NON_CONSISTENT: Lets the platform to choose to return either | |
34 | * consistent or non-consistent memory as it sees fit. | |
35 | */ | |
36 | #define DMA_ATTR_NON_CONSISTENT (1UL << 3) | |
37 | /* | |
38 | * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platform to avoid creating a kernel | |
39 | * virtual mapping for the allocated buffer. | |
40 | */ | |
41 | #define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4) | |
42 | /* | |
43 | * DMA_ATTR_SKIP_CPU_SYNC: Allows platform code to skip synchronization of | |
44 | * the CPU cache for the given buffer assuming that it has been already | |
45 | * transferred to 'device' domain. | |
46 | */ | |
47 | #define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5) | |
48 | /* | |
49 | * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguous allocation of the buffer | |
50 | * in physical memory. | |
51 | */ | |
52 | #define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6) | |
53 | /* | |
54 | * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint to the DMA-mapping subsystem | |
55 | * that it's probably not worth the time to try to allocate memory to in a way | |
56 | * that gives better TLB efficiency. | |
57 | */ | |
58 | #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7) | |
59 | ||
77f2ea2f BH |
60 | /* |
61 | * A dma_addr_t can hold any valid DMA or bus address for the platform. | |
62 | * It can be given to a device to use as a DMA source or target. A CPU cannot | |
63 | * reference a dma_addr_t directly because there may be translation between | |
64 | * its physical address space and the bus address space. | |
65 | */ | |
f0402a26 | 66 | struct dma_map_ops { |
613c4578 MS |
67 | void* (*alloc)(struct device *dev, size_t size, |
68 | dma_addr_t *dma_handle, gfp_t gfp, | |
00085f1e | 69 | unsigned long attrs); |
613c4578 MS |
70 | void (*free)(struct device *dev, size_t size, |
71 | void *vaddr, dma_addr_t dma_handle, | |
00085f1e | 72 | unsigned long attrs); |
9adc5374 | 73 | int (*mmap)(struct device *, struct vm_area_struct *, |
00085f1e KK |
74 | void *, dma_addr_t, size_t, |
75 | unsigned long attrs); | |
9adc5374 | 76 | |
d2b7428e | 77 | int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *, |
00085f1e | 78 | dma_addr_t, size_t, unsigned long attrs); |
d2b7428e | 79 | |
f0402a26 FT |
80 | dma_addr_t (*map_page)(struct device *dev, struct page *page, |
81 | unsigned long offset, size_t size, | |
82 | enum dma_data_direction dir, | |
00085f1e | 83 | unsigned long attrs); |
f0402a26 FT |
84 | void (*unmap_page)(struct device *dev, dma_addr_t dma_handle, |
85 | size_t size, enum dma_data_direction dir, | |
00085f1e | 86 | unsigned long attrs); |
04abab69 RRD |
87 | /* |
88 | * map_sg returns 0 on error and a value > 0 on success. | |
89 | * It should never return a value < 0. | |
90 | */ | |
f0402a26 FT |
91 | int (*map_sg)(struct device *dev, struct scatterlist *sg, |
92 | int nents, enum dma_data_direction dir, | |
00085f1e | 93 | unsigned long attrs); |
f0402a26 FT |
94 | void (*unmap_sg)(struct device *dev, |
95 | struct scatterlist *sg, int nents, | |
96 | enum dma_data_direction dir, | |
00085f1e | 97 | unsigned long attrs); |
ba409b31 NS |
98 | dma_addr_t (*map_resource)(struct device *dev, phys_addr_t phys_addr, |
99 | size_t size, enum dma_data_direction dir, | |
100 | unsigned long attrs); | |
101 | void (*unmap_resource)(struct device *dev, dma_addr_t dma_handle, | |
102 | size_t size, enum dma_data_direction dir, | |
103 | unsigned long attrs); | |
f0402a26 FT |
104 | void (*sync_single_for_cpu)(struct device *dev, |
105 | dma_addr_t dma_handle, size_t size, | |
106 | enum dma_data_direction dir); | |
107 | void (*sync_single_for_device)(struct device *dev, | |
108 | dma_addr_t dma_handle, size_t size, | |
109 | enum dma_data_direction dir); | |
f0402a26 FT |
110 | void (*sync_sg_for_cpu)(struct device *dev, |
111 | struct scatterlist *sg, int nents, | |
112 | enum dma_data_direction dir); | |
113 | void (*sync_sg_for_device)(struct device *dev, | |
114 | struct scatterlist *sg, int nents, | |
115 | enum dma_data_direction dir); | |
116 | int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); | |
117 | int (*dma_supported)(struct device *dev, u64 mask); | |
f726f30e | 118 | int (*set_dma_mask)(struct device *dev, u64 mask); |
3a8f7558 MM |
119 | #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK |
120 | u64 (*get_required_mask)(struct device *dev); | |
121 | #endif | |
f0402a26 FT |
122 | int is_phys; |
123 | }; | |
124 | ||
a8463d4b CB |
125 | extern struct dma_map_ops dma_noop_ops; |
126 | ||
8f286c33 | 127 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
34c65384 | 128 | |
32e8f702 JB |
129 | #define DMA_MASK_NONE 0x0ULL |
130 | ||
d6bd3a39 REB |
131 | static inline int valid_dma_direction(int dma_direction) |
132 | { | |
133 | return ((dma_direction == DMA_BIDIRECTIONAL) || | |
134 | (dma_direction == DMA_TO_DEVICE) || | |
135 | (dma_direction == DMA_FROM_DEVICE)); | |
136 | } | |
137 | ||
32e8f702 JB |
138 | static inline int is_device_dma_capable(struct device *dev) |
139 | { | |
140 | return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE; | |
141 | } | |
142 | ||
20d666e4 CH |
143 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
144 | /* | |
145 | * These three functions are only for dma allocator. | |
146 | * Don't use them in device drivers. | |
147 | */ | |
148 | int dma_alloc_from_coherent(struct device *dev, ssize_t size, | |
149 | dma_addr_t *dma_handle, void **ret); | |
150 | int dma_release_from_coherent(struct device *dev, int order, void *vaddr); | |
151 | ||
152 | int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma, | |
153 | void *cpu_addr, size_t size, int *ret); | |
154 | #else | |
155 | #define dma_alloc_from_coherent(dev, size, handle, ret) (0) | |
156 | #define dma_release_from_coherent(dev, order, vaddr) (0) | |
157 | #define dma_mmap_from_coherent(dev, vma, vaddr, order, ret) (0) | |
158 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ | |
159 | ||
1b0fac45 | 160 | #ifdef CONFIG_HAS_DMA |
1da177e4 | 161 | #include <asm/dma-mapping.h> |
1b0fac45 | 162 | #else |
e1c7e324 CH |
163 | /* |
164 | * Define the dma api to allow compilation but not linking of | |
165 | * dma dependent code. Code that depends on the dma-mapping | |
166 | * API needs to set 'depends on HAS_DMA' in its Kconfig | |
167 | */ | |
168 | extern struct dma_map_ops bad_dma_ops; | |
169 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) | |
170 | { | |
171 | return &bad_dma_ops; | |
172 | } | |
173 | #endif | |
174 | ||
175 | static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, | |
176 | size_t size, | |
177 | enum dma_data_direction dir, | |
00085f1e | 178 | unsigned long attrs) |
e1c7e324 CH |
179 | { |
180 | struct dma_map_ops *ops = get_dma_ops(dev); | |
181 | dma_addr_t addr; | |
182 | ||
183 | kmemcheck_mark_initialized(ptr, size); | |
184 | BUG_ON(!valid_dma_direction(dir)); | |
185 | addr = ops->map_page(dev, virt_to_page(ptr), | |
8e99469a | 186 | offset_in_page(ptr), size, |
e1c7e324 CH |
187 | dir, attrs); |
188 | debug_dma_map_page(dev, virt_to_page(ptr), | |
8e99469a | 189 | offset_in_page(ptr), size, |
e1c7e324 CH |
190 | dir, addr, true); |
191 | return addr; | |
192 | } | |
193 | ||
194 | static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, | |
195 | size_t size, | |
196 | enum dma_data_direction dir, | |
00085f1e | 197 | unsigned long attrs) |
e1c7e324 CH |
198 | { |
199 | struct dma_map_ops *ops = get_dma_ops(dev); | |
200 | ||
201 | BUG_ON(!valid_dma_direction(dir)); | |
202 | if (ops->unmap_page) | |
203 | ops->unmap_page(dev, addr, size, dir, attrs); | |
204 | debug_dma_unmap_page(dev, addr, size, dir, true); | |
205 | } | |
206 | ||
207 | /* | |
208 | * dma_maps_sg_attrs returns 0 on error and > 0 on success. | |
209 | * It should never return a value < 0. | |
210 | */ | |
211 | static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, | |
212 | int nents, enum dma_data_direction dir, | |
00085f1e | 213 | unsigned long attrs) |
e1c7e324 CH |
214 | { |
215 | struct dma_map_ops *ops = get_dma_ops(dev); | |
216 | int i, ents; | |
217 | struct scatterlist *s; | |
218 | ||
219 | for_each_sg(sg, s, nents, i) | |
220 | kmemcheck_mark_initialized(sg_virt(s), s->length); | |
221 | BUG_ON(!valid_dma_direction(dir)); | |
222 | ents = ops->map_sg(dev, sg, nents, dir, attrs); | |
223 | BUG_ON(ents < 0); | |
224 | debug_dma_map_sg(dev, sg, nents, ents, dir); | |
225 | ||
226 | return ents; | |
227 | } | |
228 | ||
229 | static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, | |
230 | int nents, enum dma_data_direction dir, | |
00085f1e | 231 | unsigned long attrs) |
e1c7e324 CH |
232 | { |
233 | struct dma_map_ops *ops = get_dma_ops(dev); | |
234 | ||
235 | BUG_ON(!valid_dma_direction(dir)); | |
236 | debug_dma_unmap_sg(dev, sg, nents, dir); | |
237 | if (ops->unmap_sg) | |
238 | ops->unmap_sg(dev, sg, nents, dir, attrs); | |
239 | } | |
240 | ||
241 | static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |
242 | size_t offset, size_t size, | |
243 | enum dma_data_direction dir) | |
244 | { | |
245 | struct dma_map_ops *ops = get_dma_ops(dev); | |
246 | dma_addr_t addr; | |
247 | ||
248 | kmemcheck_mark_initialized(page_address(page) + offset, size); | |
249 | BUG_ON(!valid_dma_direction(dir)); | |
00085f1e | 250 | addr = ops->map_page(dev, page, offset, size, dir, 0); |
e1c7e324 CH |
251 | debug_dma_map_page(dev, page, offset, size, dir, addr, false); |
252 | ||
253 | return addr; | |
254 | } | |
255 | ||
256 | static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, | |
257 | size_t size, enum dma_data_direction dir) | |
258 | { | |
259 | struct dma_map_ops *ops = get_dma_ops(dev); | |
260 | ||
261 | BUG_ON(!valid_dma_direction(dir)); | |
262 | if (ops->unmap_page) | |
00085f1e | 263 | ops->unmap_page(dev, addr, size, dir, 0); |
e1c7e324 CH |
264 | debug_dma_unmap_page(dev, addr, size, dir, false); |
265 | } | |
266 | ||
6f3d8796 NS |
267 | static inline dma_addr_t dma_map_resource(struct device *dev, |
268 | phys_addr_t phys_addr, | |
269 | size_t size, | |
270 | enum dma_data_direction dir, | |
271 | unsigned long attrs) | |
272 | { | |
273 | struct dma_map_ops *ops = get_dma_ops(dev); | |
6f3d8796 NS |
274 | dma_addr_t addr; |
275 | ||
276 | BUG_ON(!valid_dma_direction(dir)); | |
277 | ||
278 | /* Don't allow RAM to be mapped */ | |
3757dc48 | 279 | BUG_ON(pfn_valid(PHYS_PFN(phys_addr))); |
6f3d8796 NS |
280 | |
281 | addr = phys_addr; | |
282 | if (ops->map_resource) | |
283 | addr = ops->map_resource(dev, phys_addr, size, dir, attrs); | |
284 | ||
285 | debug_dma_map_resource(dev, phys_addr, size, dir, addr); | |
286 | ||
287 | return addr; | |
288 | } | |
289 | ||
290 | static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr, | |
291 | size_t size, enum dma_data_direction dir, | |
292 | unsigned long attrs) | |
293 | { | |
294 | struct dma_map_ops *ops = get_dma_ops(dev); | |
295 | ||
296 | BUG_ON(!valid_dma_direction(dir)); | |
297 | if (ops->unmap_resource) | |
298 | ops->unmap_resource(dev, addr, size, dir, attrs); | |
299 | debug_dma_unmap_resource(dev, addr, size, dir); | |
300 | } | |
301 | ||
e1c7e324 CH |
302 | static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, |
303 | size_t size, | |
304 | enum dma_data_direction dir) | |
305 | { | |
306 | struct dma_map_ops *ops = get_dma_ops(dev); | |
307 | ||
308 | BUG_ON(!valid_dma_direction(dir)); | |
309 | if (ops->sync_single_for_cpu) | |
310 | ops->sync_single_for_cpu(dev, addr, size, dir); | |
311 | debug_dma_sync_single_for_cpu(dev, addr, size, dir); | |
312 | } | |
313 | ||
314 | static inline void dma_sync_single_for_device(struct device *dev, | |
315 | dma_addr_t addr, size_t size, | |
316 | enum dma_data_direction dir) | |
317 | { | |
318 | struct dma_map_ops *ops = get_dma_ops(dev); | |
319 | ||
320 | BUG_ON(!valid_dma_direction(dir)); | |
321 | if (ops->sync_single_for_device) | |
322 | ops->sync_single_for_device(dev, addr, size, dir); | |
323 | debug_dma_sync_single_for_device(dev, addr, size, dir); | |
324 | } | |
325 | ||
326 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | |
327 | dma_addr_t addr, | |
328 | unsigned long offset, | |
329 | size_t size, | |
330 | enum dma_data_direction dir) | |
331 | { | |
332 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
333 | ||
334 | BUG_ON(!valid_dma_direction(dir)); | |
335 | if (ops->sync_single_for_cpu) | |
336 | ops->sync_single_for_cpu(dev, addr + offset, size, dir); | |
337 | debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); | |
338 | } | |
339 | ||
340 | static inline void dma_sync_single_range_for_device(struct device *dev, | |
341 | dma_addr_t addr, | |
342 | unsigned long offset, | |
343 | size_t size, | |
344 | enum dma_data_direction dir) | |
345 | { | |
346 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
347 | ||
348 | BUG_ON(!valid_dma_direction(dir)); | |
349 | if (ops->sync_single_for_device) | |
350 | ops->sync_single_for_device(dev, addr + offset, size, dir); | |
351 | debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); | |
352 | } | |
353 | ||
354 | static inline void | |
355 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
356 | int nelems, enum dma_data_direction dir) | |
357 | { | |
358 | struct dma_map_ops *ops = get_dma_ops(dev); | |
359 | ||
360 | BUG_ON(!valid_dma_direction(dir)); | |
361 | if (ops->sync_sg_for_cpu) | |
362 | ops->sync_sg_for_cpu(dev, sg, nelems, dir); | |
363 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); | |
364 | } | |
365 | ||
366 | static inline void | |
367 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
368 | int nelems, enum dma_data_direction dir) | |
369 | { | |
370 | struct dma_map_ops *ops = get_dma_ops(dev); | |
371 | ||
372 | BUG_ON(!valid_dma_direction(dir)); | |
373 | if (ops->sync_sg_for_device) | |
374 | ops->sync_sg_for_device(dev, sg, nelems, dir); | |
375 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); | |
376 | ||
377 | } | |
378 | ||
00085f1e KK |
379 | #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0) |
380 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | |
381 | #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, 0) | |
382 | #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, 0) | |
e1c7e324 CH |
383 | |
384 | extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, | |
385 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
386 | ||
387 | void *dma_common_contiguous_remap(struct page *page, size_t size, | |
388 | unsigned long vm_flags, | |
389 | pgprot_t prot, const void *caller); | |
390 | ||
391 | void *dma_common_pages_remap(struct page **pages, size_t size, | |
392 | unsigned long vm_flags, pgprot_t prot, | |
393 | const void *caller); | |
394 | void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags); | |
395 | ||
396 | /** | |
397 | * dma_mmap_attrs - map a coherent DMA allocation into user space | |
398 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
399 | * @vma: vm_area_struct describing requested user mapping | |
400 | * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs | |
401 | * @handle: device-view address returned from dma_alloc_attrs | |
402 | * @size: size of memory originally requested in dma_alloc_attrs | |
403 | * @attrs: attributes of mapping properties requested in dma_alloc_attrs | |
404 | * | |
405 | * Map a coherent DMA buffer previously allocated by dma_alloc_attrs | |
406 | * into user space. The coherent DMA buffer must not be freed by the | |
407 | * driver until the user space mapping has been released. | |
408 | */ | |
409 | static inline int | |
410 | dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 411 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
e1c7e324 CH |
412 | { |
413 | struct dma_map_ops *ops = get_dma_ops(dev); | |
414 | BUG_ON(!ops); | |
415 | if (ops->mmap) | |
416 | return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
417 | return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); | |
418 | } | |
419 | ||
00085f1e | 420 | #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0) |
e1c7e324 CH |
421 | |
422 | int | |
423 | dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, | |
424 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
425 | ||
426 | static inline int | |
427 | dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, | |
00085f1e KK |
428 | dma_addr_t dma_addr, size_t size, |
429 | unsigned long attrs) | |
e1c7e324 CH |
430 | { |
431 | struct dma_map_ops *ops = get_dma_ops(dev); | |
432 | BUG_ON(!ops); | |
433 | if (ops->get_sgtable) | |
434 | return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, | |
435 | attrs); | |
436 | return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); | |
437 | } | |
438 | ||
00085f1e | 439 | #define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0) |
e1c7e324 CH |
440 | |
441 | #ifndef arch_dma_alloc_attrs | |
442 | #define arch_dma_alloc_attrs(dev, flag) (true) | |
443 | #endif | |
444 | ||
445 | static inline void *dma_alloc_attrs(struct device *dev, size_t size, | |
446 | dma_addr_t *dma_handle, gfp_t flag, | |
00085f1e | 447 | unsigned long attrs) |
e1c7e324 CH |
448 | { |
449 | struct dma_map_ops *ops = get_dma_ops(dev); | |
450 | void *cpu_addr; | |
451 | ||
452 | BUG_ON(!ops); | |
453 | ||
454 | if (dma_alloc_from_coherent(dev, size, dma_handle, &cpu_addr)) | |
455 | return cpu_addr; | |
456 | ||
457 | if (!arch_dma_alloc_attrs(&dev, &flag)) | |
458 | return NULL; | |
459 | if (!ops->alloc) | |
460 | return NULL; | |
461 | ||
462 | cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); | |
463 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
464 | return cpu_addr; | |
465 | } | |
466 | ||
467 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
468 | void *cpu_addr, dma_addr_t dma_handle, | |
00085f1e | 469 | unsigned long attrs) |
e1c7e324 CH |
470 | { |
471 | struct dma_map_ops *ops = get_dma_ops(dev); | |
472 | ||
473 | BUG_ON(!ops); | |
474 | WARN_ON(irqs_disabled()); | |
475 | ||
476 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) | |
477 | return; | |
478 | ||
d6b7eaeb | 479 | if (!ops->free || !cpu_addr) |
e1c7e324 CH |
480 | return; |
481 | ||
482 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
483 | ops->free(dev, size, cpu_addr, dma_handle, attrs); | |
484 | } | |
485 | ||
486 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
487 | dma_addr_t *dma_handle, gfp_t flag) | |
488 | { | |
00085f1e | 489 | return dma_alloc_attrs(dev, size, dma_handle, flag, 0); |
e1c7e324 CH |
490 | } |
491 | ||
492 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
493 | void *cpu_addr, dma_addr_t dma_handle) | |
494 | { | |
00085f1e | 495 | return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0); |
e1c7e324 CH |
496 | } |
497 | ||
498 | static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, | |
499 | dma_addr_t *dma_handle, gfp_t gfp) | |
500 | { | |
00085f1e KK |
501 | return dma_alloc_attrs(dev, size, dma_handle, gfp, |
502 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
503 | } |
504 | ||
505 | static inline void dma_free_noncoherent(struct device *dev, size_t size, | |
506 | void *cpu_addr, dma_addr_t dma_handle) | |
507 | { | |
00085f1e KK |
508 | dma_free_attrs(dev, size, cpu_addr, dma_handle, |
509 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
510 | } |
511 | ||
512 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
513 | { | |
514 | debug_dma_mapping_error(dev, dma_addr); | |
515 | ||
516 | if (get_dma_ops(dev)->mapping_error) | |
517 | return get_dma_ops(dev)->mapping_error(dev, dma_addr); | |
518 | ||
519 | #ifdef DMA_ERROR_CODE | |
520 | return dma_addr == DMA_ERROR_CODE; | |
521 | #else | |
522 | return 0; | |
523 | #endif | |
524 | } | |
525 | ||
526 | #ifndef HAVE_ARCH_DMA_SUPPORTED | |
527 | static inline int dma_supported(struct device *dev, u64 mask) | |
528 | { | |
529 | struct dma_map_ops *ops = get_dma_ops(dev); | |
530 | ||
531 | if (!ops) | |
532 | return 0; | |
533 | if (!ops->dma_supported) | |
534 | return 1; | |
535 | return ops->dma_supported(dev, mask); | |
536 | } | |
537 | #endif | |
538 | ||
539 | #ifndef HAVE_ARCH_DMA_SET_MASK | |
540 | static inline int dma_set_mask(struct device *dev, u64 mask) | |
541 | { | |
542 | struct dma_map_ops *ops = get_dma_ops(dev); | |
543 | ||
544 | if (ops->set_dma_mask) | |
545 | return ops->set_dma_mask(dev, mask); | |
546 | ||
547 | if (!dev->dma_mask || !dma_supported(dev, mask)) | |
548 | return -EIO; | |
549 | *dev->dma_mask = mask; | |
550 | return 0; | |
551 | } | |
1b0fac45 | 552 | #endif |
1da177e4 | 553 | |
589fc9a6 FT |
554 | static inline u64 dma_get_mask(struct device *dev) |
555 | { | |
07a2c01a | 556 | if (dev && dev->dma_mask && *dev->dma_mask) |
589fc9a6 | 557 | return *dev->dma_mask; |
284901a9 | 558 | return DMA_BIT_MASK(32); |
589fc9a6 FT |
559 | } |
560 | ||
58af4a24 | 561 | #ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK |
710224fa FT |
562 | int dma_set_coherent_mask(struct device *dev, u64 mask); |
563 | #else | |
6a1961f4 FT |
564 | static inline int dma_set_coherent_mask(struct device *dev, u64 mask) |
565 | { | |
566 | if (!dma_supported(dev, mask)) | |
567 | return -EIO; | |
568 | dev->coherent_dma_mask = mask; | |
569 | return 0; | |
570 | } | |
710224fa | 571 | #endif |
6a1961f4 | 572 | |
4aa806b7 RK |
573 | /* |
574 | * Set both the DMA mask and the coherent DMA mask to the same thing. | |
575 | * Note that we don't check the return value from dma_set_coherent_mask() | |
576 | * as the DMA API guarantees that the coherent DMA mask can be set to | |
577 | * the same or smaller than the streaming DMA mask. | |
578 | */ | |
579 | static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask) | |
580 | { | |
581 | int rc = dma_set_mask(dev, mask); | |
582 | if (rc == 0) | |
583 | dma_set_coherent_mask(dev, mask); | |
584 | return rc; | |
585 | } | |
586 | ||
fa6a8d6d RK |
587 | /* |
588 | * Similar to the above, except it deals with the case where the device | |
589 | * does not have dev->dma_mask appropriately setup. | |
590 | */ | |
591 | static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask) | |
592 | { | |
593 | dev->dma_mask = &dev->coherent_dma_mask; | |
594 | return dma_set_mask_and_coherent(dev, mask); | |
595 | } | |
596 | ||
1da177e4 LT |
597 | extern u64 dma_get_required_mask(struct device *dev); |
598 | ||
a3a60f81 | 599 | #ifndef arch_setup_dma_ops |
97890ba9 | 600 | static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, |
53c92d79 | 601 | u64 size, const struct iommu_ops *iommu, |
97890ba9 WD |
602 | bool coherent) { } |
603 | #endif | |
604 | ||
605 | #ifndef arch_teardown_dma_ops | |
606 | static inline void arch_teardown_dma_ops(struct device *dev) { } | |
591c1ee4 SS |
607 | #endif |
608 | ||
6b7b6510 FT |
609 | static inline unsigned int dma_get_max_seg_size(struct device *dev) |
610 | { | |
002edb6f RM |
611 | if (dev->dma_parms && dev->dma_parms->max_segment_size) |
612 | return dev->dma_parms->max_segment_size; | |
613 | return SZ_64K; | |
6b7b6510 FT |
614 | } |
615 | ||
616 | static inline unsigned int dma_set_max_seg_size(struct device *dev, | |
617 | unsigned int size) | |
618 | { | |
619 | if (dev->dma_parms) { | |
620 | dev->dma_parms->max_segment_size = size; | |
621 | return 0; | |
002edb6f RM |
622 | } |
623 | return -EIO; | |
6b7b6510 FT |
624 | } |
625 | ||
d22a6966 FT |
626 | static inline unsigned long dma_get_seg_boundary(struct device *dev) |
627 | { | |
002edb6f RM |
628 | if (dev->dma_parms && dev->dma_parms->segment_boundary_mask) |
629 | return dev->dma_parms->segment_boundary_mask; | |
630 | return DMA_BIT_MASK(32); | |
d22a6966 FT |
631 | } |
632 | ||
633 | static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) | |
634 | { | |
635 | if (dev->dma_parms) { | |
636 | dev->dma_parms->segment_boundary_mask = mask; | |
637 | return 0; | |
002edb6f RM |
638 | } |
639 | return -EIO; | |
d22a6966 FT |
640 | } |
641 | ||
00c8f162 SS |
642 | #ifndef dma_max_pfn |
643 | static inline unsigned long dma_max_pfn(struct device *dev) | |
644 | { | |
645 | return *dev->dma_mask >> PAGE_SHIFT; | |
646 | } | |
647 | #endif | |
648 | ||
842fa69f AM |
649 | static inline void *dma_zalloc_coherent(struct device *dev, size_t size, |
650 | dma_addr_t *dma_handle, gfp_t flag) | |
651 | { | |
ede23fa8 JP |
652 | void *ret = dma_alloc_coherent(dev, size, dma_handle, |
653 | flag | __GFP_ZERO); | |
842fa69f AM |
654 | return ret; |
655 | } | |
656 | ||
e259f191 | 657 | #ifdef CONFIG_HAS_DMA |
4565f017 FT |
658 | static inline int dma_get_cache_alignment(void) |
659 | { | |
660 | #ifdef ARCH_DMA_MINALIGN | |
661 | return ARCH_DMA_MINALIGN; | |
662 | #endif | |
663 | return 1; | |
664 | } | |
e259f191 | 665 | #endif |
4565f017 | 666 | |
1da177e4 LT |
667 | /* flags for the coherent memory api */ |
668 | #define DMA_MEMORY_MAP 0x01 | |
669 | #define DMA_MEMORY_IO 0x02 | |
670 | #define DMA_MEMORY_INCLUDES_CHILDREN 0x04 | |
671 | #define DMA_MEMORY_EXCLUSIVE 0x08 | |
672 | ||
20d666e4 CH |
673 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
674 | int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, | |
675 | dma_addr_t device_addr, size_t size, int flags); | |
676 | void dma_release_declared_memory(struct device *dev); | |
677 | void *dma_mark_declared_memory_occupied(struct device *dev, | |
678 | dma_addr_t device_addr, size_t size); | |
679 | #else | |
1da177e4 | 680 | static inline int |
88a984ba | 681 | dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, |
1da177e4 LT |
682 | dma_addr_t device_addr, size_t size, int flags) |
683 | { | |
684 | return 0; | |
685 | } | |
686 | ||
687 | static inline void | |
688 | dma_release_declared_memory(struct device *dev) | |
689 | { | |
690 | } | |
691 | ||
692 | static inline void * | |
693 | dma_mark_declared_memory_occupied(struct device *dev, | |
694 | dma_addr_t device_addr, size_t size) | |
695 | { | |
696 | return ERR_PTR(-EBUSY); | |
697 | } | |
20d666e4 | 698 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 699 | |
9ac7849e TH |
700 | /* |
701 | * Managed DMA API | |
702 | */ | |
703 | extern void *dmam_alloc_coherent(struct device *dev, size_t size, | |
704 | dma_addr_t *dma_handle, gfp_t gfp); | |
705 | extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, | |
706 | dma_addr_t dma_handle); | |
707 | extern void *dmam_alloc_noncoherent(struct device *dev, size_t size, | |
708 | dma_addr_t *dma_handle, gfp_t gfp); | |
709 | extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr, | |
710 | dma_addr_t dma_handle); | |
20d666e4 | 711 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
88a984ba BH |
712 | extern int dmam_declare_coherent_memory(struct device *dev, |
713 | phys_addr_t phys_addr, | |
9ac7849e TH |
714 | dma_addr_t device_addr, size_t size, |
715 | int flags); | |
716 | extern void dmam_release_declared_memory(struct device *dev); | |
20d666e4 | 717 | #else /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
9ac7849e | 718 | static inline int dmam_declare_coherent_memory(struct device *dev, |
88a984ba | 719 | phys_addr_t phys_addr, dma_addr_t device_addr, |
9ac7849e TH |
720 | size_t size, gfp_t gfp) |
721 | { | |
722 | return 0; | |
723 | } | |
1da177e4 | 724 | |
9ac7849e TH |
725 | static inline void dmam_release_declared_memory(struct device *dev) |
726 | { | |
727 | } | |
20d666e4 | 728 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 729 | |
f6e45661 LR |
730 | static inline void *dma_alloc_wc(struct device *dev, size_t size, |
731 | dma_addr_t *dma_addr, gfp_t gfp) | |
b4bbb107 | 732 | { |
00085f1e KK |
733 | return dma_alloc_attrs(dev, size, dma_addr, gfp, |
734 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 735 | } |
f6e45661 LR |
736 | #ifndef dma_alloc_writecombine |
737 | #define dma_alloc_writecombine dma_alloc_wc | |
738 | #endif | |
b4bbb107 | 739 | |
f6e45661 LR |
740 | static inline void dma_free_wc(struct device *dev, size_t size, |
741 | void *cpu_addr, dma_addr_t dma_addr) | |
b4bbb107 | 742 | { |
00085f1e KK |
743 | return dma_free_attrs(dev, size, cpu_addr, dma_addr, |
744 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 745 | } |
f6e45661 LR |
746 | #ifndef dma_free_writecombine |
747 | #define dma_free_writecombine dma_free_wc | |
748 | #endif | |
b4bbb107 | 749 | |
f6e45661 LR |
750 | static inline int dma_mmap_wc(struct device *dev, |
751 | struct vm_area_struct *vma, | |
752 | void *cpu_addr, dma_addr_t dma_addr, | |
753 | size_t size) | |
b4bbb107 | 754 | { |
00085f1e KK |
755 | return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, |
756 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 757 | } |
f6e45661 LR |
758 | #ifndef dma_mmap_writecombine |
759 | #define dma_mmap_writecombine dma_mmap_wc | |
760 | #endif | |
74bc7cee | 761 | |
2481366a | 762 | #if defined(CONFIG_NEED_DMA_MAP_STATE) || defined(CONFIG_DMA_API_DEBUG) |
0acedc12 FT |
763 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME |
764 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME | |
765 | #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | |
766 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | |
767 | #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | |
768 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | |
769 | #else | |
770 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) | |
771 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) | |
772 | #define dma_unmap_addr(PTR, ADDR_NAME) (0) | |
773 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
774 | #define dma_unmap_len(PTR, LEN_NAME) (0) | |
775 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
776 | #endif | |
777 | ||
9ac7849e | 778 | #endif |