[mirror_ubuntu-zesty-kernel.git] / include / linux / dma-mapping.h

#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H

#include <linux/string.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/dma-attrs.h>
#include <linux/dma-direction.h>
#include <linux/scatterlist.h>

/*
 * A dma_addr_t can hold any valid DMA or bus address for the platform.
 * It can be given to a device to use as a DMA source or target.  A CPU cannot
 * reference a dma_addr_t directly because there may be translation between
 * its physical address space and the bus address space.
 */
struct dma_map_ops {
	void* (*alloc)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t gfp,
				struct dma_attrs *attrs);
	void (*free)(struct device *dev, size_t size,
			      void *vaddr, dma_addr_t dma_handle,
			      struct dma_attrs *attrs);
	int (*mmap)(struct device *, struct vm_area_struct *,
			  void *, dma_addr_t, size_t, struct dma_attrs *attrs);

	int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *,
			   dma_addr_t, size_t, struct dma_attrs *attrs);

	dma_addr_t (*map_page)(struct device *dev, struct page *page,
			       unsigned long offset, size_t size,
			       enum dma_data_direction dir,
			       struct dma_attrs *attrs);
	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
			   size_t size, enum dma_data_direction dir,
			   struct dma_attrs *attrs);
	/*
	 * map_sg returns 0 on error and a value > 0 on success.
	 * It should never return a value < 0.
	 */
	int (*map_sg)(struct device *dev, struct scatterlist *sg,
		      int nents, enum dma_data_direction dir,
		      struct dma_attrs *attrs);
	void (*unmap_sg)(struct device *dev,
			 struct scatterlist *sg, int nents,
			 enum dma_data_direction dir,
			 struct dma_attrs *attrs);
	void (*sync_single_for_cpu)(struct device *dev,
				    dma_addr_t dma_handle, size_t size,
				    enum dma_data_direction dir);
	void (*sync_single_for_device)(struct device *dev,
				       dma_addr_t dma_handle, size_t size,
				       enum dma_data_direction dir);
	void (*sync_sg_for_cpu)(struct device *dev,
				struct scatterlist *sg, int nents,
				enum dma_data_direction dir);
	void (*sync_sg_for_device)(struct device *dev,
				   struct scatterlist *sg, int nents,
				   enum dma_data_direction dir);
	int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
	int (*dma_supported)(struct device *dev, u64 mask);
	int (*set_dma_mask)(struct device *dev, u64 mask);
#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	u64 (*get_required_mask)(struct device *dev);
#endif
	int is_phys;
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

static inline u64 dma_get_mask(struct device *dev)
{
	if (dev && dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	return DMA_BIT_MASK(32);
}

#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
int dma_set_coherent_mask(struct device *dev, u64 mask);
#else
static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
{
	if (!dma_supported(dev, mask))
		return -EIO;
	dev->coherent_dma_mask = mask;
	return 0;
}
#endif

/*
 * Set both the DMA mask and the coherent DMA mask to the same thing.
 * Note that we don't check the return value from dma_set_coherent_mask()
 * as the DMA API guarantees that the coherent DMA mask can be set to
 * the same or smaller than the streaming DMA mask.
 */
static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
{
	int rc = dma_set_mask(dev, mask);
	if (rc == 0)
		dma_set_coherent_mask(dev, mask);
	return rc;
}

/*
 * Similar to the above, except it deals with the case where the device
 * does not have dev->dma_mask appropriately setup.
 */
static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
{
	dev->dma_mask = &dev->coherent_dma_mask;
	return dma_set_mask_and_coherent(dev, mask);
}

extern u64 dma_get_required_mask(struct device *dev);

#ifndef arch_setup_dma_ops
static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
				      u64 size, struct iommu_ops *iommu,
				      bool coherent) { }
#endif

#ifndef arch_teardown_dma_ops
static inline void arch_teardown_dma_ops(struct device *dev) { }
#endif

static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
}

static inline unsigned int dma_set_max_seg_size(struct device *dev,
						unsigned int size)
{
	if (dev->dma_parms) {
		dev->dma_parms->max_segment_size = size;
		return 0;
	} else
		return -EIO;
}

static inline unsigned long dma_get_seg_boundary(struct device *dev)
{
	return dev->dma_parms ?
		dev->dma_parms->segment_boundary_mask : 0xffffffff;
}

static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
{
	if (dev->dma_parms) {
		dev->dma_parms->segment_boundary_mask = mask;
		return 0;
	} else
		return -EIO;
}

#ifndef dma_max_pfn
static inline unsigned long dma_max_pfn(struct device *dev)
{
	return *dev->dma_mask >> PAGE_SHIFT;
}
#endif

static inline void *dma_zalloc_coherent(struct device *dev, size_t size,
					dma_addr_t *dma_handle, gfp_t flag)
{
	void *ret = dma_alloc_coherent(dev, size, dma_handle,
				       flag | __GFP_ZERO);
	return ret;
}

#ifdef CONFIG_HAS_DMA
static inline int dma_get_cache_alignment(void)
{
#ifdef ARCH_DMA_MINALIGN
	return ARCH_DMA_MINALIGN;
#endif
	return 1;
}
#endif

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev,
					phys_addr_t phys_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				phys_addr_t phys_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#ifndef CONFIG_HAVE_DMA_ATTRS
struct dma_attrs;

#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	dma_map_single(dev, cpu_addr, size, dir)

#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	dma_unmap_single(dev, dma_addr, size, dir)

#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_map_sg(dev, sgl, nents, dir)

#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_unmap_sg(dev, sgl, nents, dir)

#else
static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
					   dma_addr_t *dma_addr, gfp_t gfp)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
}

static inline void dma_free_writecombine(struct device *dev, size_t size,
					 void *cpu_addr, dma_addr_t dma_addr)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs);
}

static inline int dma_mmap_writecombine(struct device *dev,
					struct vm_area_struct *vma,
					void *cpu_addr, dma_addr_t dma_addr,
					size_t size)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
}
#endif /* CONFIG_HAVE_DMA_ATTRS */

#ifdef CONFIG_NEED_DMA_MAP_STATE
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)        dma_addr_t ADDR_NAME
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)          __u32 LEN_NAME
#define dma_unmap_addr(PTR, ADDR_NAME)           ((PTR)->ADDR_NAME)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  (((PTR)->ADDR_NAME) = (VAL))
#define dma_unmap_len(PTR, LEN_NAME)             ((PTR)->LEN_NAME)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    (((PTR)->LEN_NAME) = (VAL))
#else
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
#define dma_unmap_addr(PTR, ADDR_NAME)           (0)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  do { } while (0)
#define dma_unmap_len(PTR, LEN_NAME)             (0)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    do { } while (0)
#endif

#endif
Commit	Line	Data
96532bab RD	1	#ifndef _LINUX_DMA_MAPPING_H
96532bab RD	2	#define _LINUX_DMA_MAPPING_H
1da177e4	3
842fa69f	4	#include <linux/string.h>
1da177e4 LT	5	#include <linux/device.h>
1da177e4 LT	6	#include <linux/err.h>
f0402a26	7	#include <linux/dma-attrs.h>
b7f080cf	8	#include <linux/dma-direction.h>
f0402a26	9	#include <linux/scatterlist.h>
1da177e4	10
77f2ea2f BH	11	/*
	12	* A dma_addr_t can hold any valid DMA or bus address for the platform.
	13	* It can be given to a device to use as a DMA source or target. A CPU cannot
	14	* reference a dma_addr_t directly because there may be translation between
	15	* its physical address space and the bus address space.
	16	*/
f0402a26	17	struct dma_map_ops {
613c4578 MS	18	void* (alloc)(struct device dev, size_t size,
	19	dma_addr_t *dma_handle, gfp_t gfp,
	20	struct dma_attrs *attrs);
	21	void (free)(struct device dev, size_t size,
	22	void *vaddr, dma_addr_t dma_handle,
	23	struct dma_attrs *attrs);
9adc5374 MS	24	int (mmap)(struct device , struct vm_area_struct *,
	25	void , dma_addr_t, size_t, struct dma_attrs attrs);
	26
d2b7428e MS	27	int (get_sgtable)(struct device dev, struct sg_table sgt, void ,
	28	dma_addr_t, size_t, struct dma_attrs *attrs);
	29
f0402a26 FT	30	dma_addr_t (map_page)(struct device dev, struct page *page,
	31	unsigned long offset, size_t size,
	32	enum dma_data_direction dir,
	33	struct dma_attrs *attrs);
	34	void (unmap_page)(struct device dev, dma_addr_t dma_handle,
	35	size_t size, enum dma_data_direction dir,
	36	struct dma_attrs *attrs);
04abab69 RRD	37	/*
	38	* map_sg returns 0 on error and a value > 0 on success.
	39	* It should never return a value < 0.
	40	*/
f0402a26 FT	41	int (map_sg)(struct device dev, struct scatterlist *sg,
	42	int nents, enum dma_data_direction dir,
	43	struct dma_attrs *attrs);
	44	void (unmap_sg)(struct device dev,
	45	struct scatterlist *sg, int nents,
	46	enum dma_data_direction dir,
	47	struct dma_attrs *attrs);
	48	void (sync_single_for_cpu)(struct device dev,
	49	dma_addr_t dma_handle, size_t size,
	50	enum dma_data_direction dir);
	51	void (sync_single_for_device)(struct device dev,
	52	dma_addr_t dma_handle, size_t size,
	53	enum dma_data_direction dir);
f0402a26 FT	54	void (sync_sg_for_cpu)(struct device dev,
	55	struct scatterlist *sg, int nents,
	56	enum dma_data_direction dir);
	57	void (sync_sg_for_device)(struct device dev,
	58	struct scatterlist *sg, int nents,
	59	enum dma_data_direction dir);
	60	int (mapping_error)(struct device dev, dma_addr_t dma_addr);
	61	int (dma_supported)(struct device dev, u64 mask);
f726f30e	62	int (set_dma_mask)(struct device dev, u64 mask);
3a8f7558 MM	63	#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	64	u64 (get_required_mask)(struct device dev);
	65	#endif
f0402a26 FT	66	int is_phys;
	67	};
	68
8f286c33	69	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	70
32e8f702 JB	71	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	72
d6bd3a39 REB	73	static inline int valid_dma_direction(int dma_direction)
	74	{
	75	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	76	(dma_direction == DMA_TO_DEVICE) \|\|
	77	(dma_direction == DMA_FROM_DEVICE));
	78	}
	79
32e8f702 JB	80	static inline int is_device_dma_capable(struct device *dev)
	81	{
	82	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	83	}
	84
1b0fac45	85	#ifdef CONFIG_HAS_DMA
1da177e4	86	#include <asm/dma-mapping.h>
1b0fac45 DW	87	#else
	88	#include <asm-generic/dma-mapping-broken.h>
	89	#endif
1da177e4	90
589fc9a6 FT	91	static inline u64 dma_get_mask(struct device *dev)
589fc9a6 FT	92	{
07a2c01a	93	if (dev && dev->dma_mask && *dev->dma_mask)
589fc9a6	94	return *dev->dma_mask;
284901a9	95	return DMA_BIT_MASK(32);
589fc9a6 FT	96	}
589fc9a6 FT	97
58af4a24	98	#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
710224fa FT	99	int dma_set_coherent_mask(struct device *dev, u64 mask);
710224fa FT	100	#else
6a1961f4 FT	101	static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
	102	{
	103	if (!dma_supported(dev, mask))
	104	return -EIO;
	105	dev->coherent_dma_mask = mask;
	106	return 0;
	107	}
710224fa	108	#endif
6a1961f4	109
4aa806b7 RK	110	/*
	111	* Set both the DMA mask and the coherent DMA mask to the same thing.
	112	* Note that we don't check the return value from dma_set_coherent_mask()
	113	* as the DMA API guarantees that the coherent DMA mask can be set to
	114	* the same or smaller than the streaming DMA mask.
	115	*/
	116	static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
	117	{
	118	int rc = dma_set_mask(dev, mask);
	119	if (rc == 0)
	120	dma_set_coherent_mask(dev, mask);
	121	return rc;
	122	}
	123
fa6a8d6d RK	124	/*
	125	* Similar to the above, except it deals with the case where the device
	126	* does not have dev->dma_mask appropriately setup.
	127	*/
	128	static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
	129	{
	130	dev->dma_mask = &dev->coherent_dma_mask;
	131	return dma_set_mask_and_coherent(dev, mask);
	132	}
	133
1da177e4 LT	134	extern u64 dma_get_required_mask(struct device *dev);
1da177e4 LT	135
a3a60f81	136	#ifndef arch_setup_dma_ops
97890ba9 WD	137	static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
	138	u64 size, struct iommu_ops *iommu,
	139	bool coherent) { }
	140	#endif
	141
	142	#ifndef arch_teardown_dma_ops
	143	static inline void arch_teardown_dma_ops(struct device *dev) { }
591c1ee4 SS	144	#endif
591c1ee4 SS	145
6b7b6510 FT	146	static inline unsigned int dma_get_max_seg_size(struct device *dev)
	147	{
	148	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
	149	}
	150
	151	static inline unsigned int dma_set_max_seg_size(struct device *dev,
	152	unsigned int size)
	153	{
	154	if (dev->dma_parms) {
	155	dev->dma_parms->max_segment_size = size;
	156	return 0;
	157	} else
	158	return -EIO;
	159	}
	160
d22a6966 FT	161	static inline unsigned long dma_get_seg_boundary(struct device *dev)
	162	{
	163	return dev->dma_parms ?
	164	dev->dma_parms->segment_boundary_mask : 0xffffffff;
	165	}
	166
	167	static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
	168	{
	169	if (dev->dma_parms) {
	170	dev->dma_parms->segment_boundary_mask = mask;
	171	return 0;
	172	} else
	173	return -EIO;
	174	}
	175
00c8f162 SS	176	#ifndef dma_max_pfn
	177	static inline unsigned long dma_max_pfn(struct device *dev)
	178	{
	179	return *dev->dma_mask >> PAGE_SHIFT;
	180	}
	181	#endif
	182
842fa69f AM	183	static inline void dma_zalloc_coherent(struct device dev, size_t size,
	184	dma_addr_t *dma_handle, gfp_t flag)
	185	{
ede23fa8 JP	186	void *ret = dma_alloc_coherent(dev, size, dma_handle,
ede23fa8 JP	187	flag \| __GFP_ZERO);
842fa69f AM	188	return ret;
	189	}
	190
e259f191	191	#ifdef CONFIG_HAS_DMA
4565f017 FT	192	static inline int dma_get_cache_alignment(void)
	193	{
	194	#ifdef ARCH_DMA_MINALIGN
	195	return ARCH_DMA_MINALIGN;
	196	#endif
	197	return 1;
	198	}
e259f191	199	#endif
4565f017	200
1da177e4 LT	201	/* flags for the coherent memory api */
	202	#define DMA_MEMORY_MAP 0x01
	203	#define DMA_MEMORY_IO 0x02
	204	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	205	#define DMA_MEMORY_EXCLUSIVE 0x08
	206
	207	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	208	static inline int
88a984ba	209	dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
1da177e4 LT	210	dma_addr_t device_addr, size_t size, int flags)
	211	{
	212	return 0;
	213	}
	214
	215	static inline void
	216	dma_release_declared_memory(struct device *dev)
	217	{
	218	}
	219
	220	static inline void *
	221	dma_mark_declared_memory_occupied(struct device *dev,
	222	dma_addr_t device_addr, size_t size)
	223	{
	224	return ERR_PTR(-EBUSY);
	225	}
	226	#endif
	227
9ac7849e TH	228	/*
	229	* Managed DMA API
	230	*/
	231	extern void dmam_alloc_coherent(struct device dev, size_t size,
	232	dma_addr_t *dma_handle, gfp_t gfp);
	233	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	234	dma_addr_t dma_handle);
	235	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	236	dma_addr_t *dma_handle, gfp_t gfp);
	237	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	238	dma_addr_t dma_handle);
	239	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
88a984ba BH	240	extern int dmam_declare_coherent_memory(struct device *dev,
88a984ba BH	241	phys_addr_t phys_addr,
9ac7849e TH	242	dma_addr_t device_addr, size_t size,
	243	int flags);
	244	extern void dmam_release_declared_memory(struct device *dev);
	245	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	246	static inline int dmam_declare_coherent_memory(struct device *dev,
88a984ba	247	phys_addr_t phys_addr, dma_addr_t device_addr,
9ac7849e TH	248	size_t size, gfp_t gfp)
	249	{
	250	return 0;
	251	}
1da177e4	252
9ac7849e TH	253	static inline void dmam_release_declared_memory(struct device *dev)
	254	{
	255	}
	256	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	257
74bc7cee AK	258	#ifndef CONFIG_HAVE_DMA_ATTRS
	259	struct dma_attrs;
	260
	261	#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	262	dma_map_single(dev, cpu_addr, size, dir)
	263
	264	#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	265	dma_unmap_single(dev, dma_addr, size, dir)
	266
	267	#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	268	dma_map_sg(dev, sgl, nents, dir)
	269
	270	#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	271	dma_unmap_sg(dev, sgl, nents, dir)
	272
b4bbb107 TR	273	#else
	274	static inline void dma_alloc_writecombine(struct device dev, size_t size,
	275	dma_addr_t *dma_addr, gfp_t gfp)
	276	{
	277	DEFINE_DMA_ATTRS(attrs);
	278	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	279	return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
	280	}
	281
	282	static inline void dma_free_writecombine(struct device *dev, size_t size,
	283	void *cpu_addr, dma_addr_t dma_addr)
	284	{
	285	DEFINE_DMA_ATTRS(attrs);
	286	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	287	return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs);
	288	}
	289
	290	static inline int dma_mmap_writecombine(struct device *dev,
	291	struct vm_area_struct *vma,
	292	void *cpu_addr, dma_addr_t dma_addr,
	293	size_t size)
	294	{
	295	DEFINE_DMA_ATTRS(attrs);
	296	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	297	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
	298	}
74bc7cee AK	299	#endif /* CONFIG_HAVE_DMA_ATTRS */
74bc7cee AK	300
0acedc12 FT	301	#ifdef CONFIG_NEED_DMA_MAP_STATE
	302	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
	303	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
	304	#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
	305	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
	306	#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
	307	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
	308	#else
	309	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
	310	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
	311	#define dma_unmap_addr(PTR, ADDR_NAME) (0)
	312	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	313	#define dma_unmap_len(PTR, LEN_NAME) (0)
	314	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	315	#endif
	316
9ac7849e	317	#endif