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96532bab RD |
1 | #ifndef _LINUX_DMA_MAPPING_H |
2 | #define _LINUX_DMA_MAPPING_H | |
1da177e4 | 3 | |
002edb6f | 4 | #include <linux/sizes.h> |
842fa69f | 5 | #include <linux/string.h> |
1da177e4 LT |
6 | #include <linux/device.h> |
7 | #include <linux/err.h> | |
e1c7e324 | 8 | #include <linux/dma-debug.h> |
b7f080cf | 9 | #include <linux/dma-direction.h> |
f0402a26 | 10 | #include <linux/scatterlist.h> |
e1c7e324 CH |
11 | #include <linux/kmemcheck.h> |
12 | #include <linux/bug.h> | |
1da177e4 | 13 | |
00085f1e KK |
14 | /** |
15 | * List of possible attributes associated with a DMA mapping. The semantics | |
16 | * of each attribute should be defined in Documentation/DMA-attributes.txt. | |
17 | * | |
18 | * DMA_ATTR_WRITE_BARRIER: DMA to a memory region with this attribute | |
19 | * forces all pending DMA writes to complete. | |
20 | */ | |
21 | #define DMA_ATTR_WRITE_BARRIER (1UL << 0) | |
22 | /* | |
23 | * DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping | |
24 | * may be weakly ordered, that is that reads and writes may pass each other. | |
25 | */ | |
26 | #define DMA_ATTR_WEAK_ORDERING (1UL << 1) | |
27 | /* | |
28 | * DMA_ATTR_WRITE_COMBINE: Specifies that writes to the mapping may be | |
29 | * buffered to improve performance. | |
30 | */ | |
31 | #define DMA_ATTR_WRITE_COMBINE (1UL << 2) | |
32 | /* | |
33 | * DMA_ATTR_NON_CONSISTENT: Lets the platform to choose to return either | |
34 | * consistent or non-consistent memory as it sees fit. | |
35 | */ | |
36 | #define DMA_ATTR_NON_CONSISTENT (1UL << 3) | |
37 | /* | |
38 | * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platform to avoid creating a kernel | |
39 | * virtual mapping for the allocated buffer. | |
40 | */ | |
41 | #define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4) | |
42 | /* | |
43 | * DMA_ATTR_SKIP_CPU_SYNC: Allows platform code to skip synchronization of | |
44 | * the CPU cache for the given buffer assuming that it has been already | |
45 | * transferred to 'device' domain. | |
46 | */ | |
47 | #define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5) | |
48 | /* | |
49 | * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguous allocation of the buffer | |
50 | * in physical memory. | |
51 | */ | |
52 | #define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6) | |
53 | /* | |
54 | * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint to the DMA-mapping subsystem | |
55 | * that it's probably not worth the time to try to allocate memory to in a way | |
56 | * that gives better TLB efficiency. | |
57 | */ | |
58 | #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7) | |
a9a62c93 MFO |
59 | /* |
60 | * DMA_ATTR_NO_WARN: This tells the DMA-mapping subsystem to suppress | |
61 | * allocation failure reports (similarly to __GFP_NOWARN). | |
62 | */ | |
63 | #define DMA_ATTR_NO_WARN (1UL << 8) | |
00085f1e | 64 | |
b2fb3664 MH |
65 | /* |
66 | * DMA_ATTR_PRIVILEGED: used to indicate that the buffer is fully | |
67 | * accessible at an elevated privilege level (and ideally inaccessible or | |
68 | * at least read-only at lesser-privileged levels). | |
69 | */ | |
70 | #define DMA_ATTR_PRIVILEGED (1UL << 9) | |
71 | ||
77f2ea2f BH |
72 | /* |
73 | * A dma_addr_t can hold any valid DMA or bus address for the platform. | |
74 | * It can be given to a device to use as a DMA source or target. A CPU cannot | |
75 | * reference a dma_addr_t directly because there may be translation between | |
76 | * its physical address space and the bus address space. | |
77 | */ | |
f0402a26 | 78 | struct dma_map_ops { |
613c4578 MS |
79 | void* (*alloc)(struct device *dev, size_t size, |
80 | dma_addr_t *dma_handle, gfp_t gfp, | |
00085f1e | 81 | unsigned long attrs); |
613c4578 MS |
82 | void (*free)(struct device *dev, size_t size, |
83 | void *vaddr, dma_addr_t dma_handle, | |
00085f1e | 84 | unsigned long attrs); |
9adc5374 | 85 | int (*mmap)(struct device *, struct vm_area_struct *, |
00085f1e KK |
86 | void *, dma_addr_t, size_t, |
87 | unsigned long attrs); | |
9adc5374 | 88 | |
d2b7428e | 89 | int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *, |
00085f1e | 90 | dma_addr_t, size_t, unsigned long attrs); |
d2b7428e | 91 | |
f0402a26 FT |
92 | dma_addr_t (*map_page)(struct device *dev, struct page *page, |
93 | unsigned long offset, size_t size, | |
94 | enum dma_data_direction dir, | |
00085f1e | 95 | unsigned long attrs); |
f0402a26 FT |
96 | void (*unmap_page)(struct device *dev, dma_addr_t dma_handle, |
97 | size_t size, enum dma_data_direction dir, | |
00085f1e | 98 | unsigned long attrs); |
04abab69 RR |
99 | /* |
100 | * map_sg returns 0 on error and a value > 0 on success. | |
101 | * It should never return a value < 0. | |
102 | */ | |
f0402a26 FT |
103 | int (*map_sg)(struct device *dev, struct scatterlist *sg, |
104 | int nents, enum dma_data_direction dir, | |
00085f1e | 105 | unsigned long attrs); |
f0402a26 FT |
106 | void (*unmap_sg)(struct device *dev, |
107 | struct scatterlist *sg, int nents, | |
108 | enum dma_data_direction dir, | |
00085f1e | 109 | unsigned long attrs); |
ba409b31 NS |
110 | dma_addr_t (*map_resource)(struct device *dev, phys_addr_t phys_addr, |
111 | size_t size, enum dma_data_direction dir, | |
112 | unsigned long attrs); | |
113 | void (*unmap_resource)(struct device *dev, dma_addr_t dma_handle, | |
114 | size_t size, enum dma_data_direction dir, | |
115 | unsigned long attrs); | |
f0402a26 FT |
116 | void (*sync_single_for_cpu)(struct device *dev, |
117 | dma_addr_t dma_handle, size_t size, | |
118 | enum dma_data_direction dir); | |
119 | void (*sync_single_for_device)(struct device *dev, | |
120 | dma_addr_t dma_handle, size_t size, | |
121 | enum dma_data_direction dir); | |
f0402a26 FT |
122 | void (*sync_sg_for_cpu)(struct device *dev, |
123 | struct scatterlist *sg, int nents, | |
124 | enum dma_data_direction dir); | |
125 | void (*sync_sg_for_device)(struct device *dev, | |
126 | struct scatterlist *sg, int nents, | |
127 | enum dma_data_direction dir); | |
128 | int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); | |
129 | int (*dma_supported)(struct device *dev, u64 mask); | |
3a8f7558 MM |
130 | #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK |
131 | u64 (*get_required_mask)(struct device *dev); | |
132 | #endif | |
f0402a26 FT |
133 | int is_phys; |
134 | }; | |
135 | ||
5299709d | 136 | extern const struct dma_map_ops dma_noop_ops; |
551199ac | 137 | extern const struct dma_map_ops dma_virt_ops; |
a8463d4b | 138 | |
8f286c33 | 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
34c65384 | 140 | |
32e8f702 JB |
141 | #define DMA_MASK_NONE 0x0ULL |
142 | ||
d6bd3a39 REB |
143 | static inline int valid_dma_direction(int dma_direction) |
144 | { | |
145 | return ((dma_direction == DMA_BIDIRECTIONAL) || | |
146 | (dma_direction == DMA_TO_DEVICE) || | |
147 | (dma_direction == DMA_FROM_DEVICE)); | |
148 | } | |
149 | ||
32e8f702 JB |
150 | static inline int is_device_dma_capable(struct device *dev) |
151 | { | |
152 | return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE; | |
153 | } | |
154 | ||
20d666e4 CH |
155 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
156 | /* | |
157 | * These three functions are only for dma allocator. | |
158 | * Don't use them in device drivers. | |
159 | */ | |
160 | int dma_alloc_from_coherent(struct device *dev, ssize_t size, | |
161 | dma_addr_t *dma_handle, void **ret); | |
162 | int dma_release_from_coherent(struct device *dev, int order, void *vaddr); | |
163 | ||
164 | int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma, | |
165 | void *cpu_addr, size_t size, int *ret); | |
166 | #else | |
167 | #define dma_alloc_from_coherent(dev, size, handle, ret) (0) | |
168 | #define dma_release_from_coherent(dev, order, vaddr) (0) | |
169 | #define dma_mmap_from_coherent(dev, vma, vaddr, order, ret) (0) | |
170 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ | |
171 | ||
1b0fac45 | 172 | #ifdef CONFIG_HAS_DMA |
1da177e4 | 173 | #include <asm/dma-mapping.h> |
815dd187 BVA |
174 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) |
175 | { | |
176 | if (dev && dev->dma_ops) | |
177 | return dev->dma_ops; | |
178 | return get_arch_dma_ops(dev ? dev->bus : NULL); | |
179 | } | |
180 | ||
ca6e8e10 BVA |
181 | static inline void set_dma_ops(struct device *dev, |
182 | const struct dma_map_ops *dma_ops) | |
183 | { | |
184 | dev->dma_ops = dma_ops; | |
185 | } | |
1b0fac45 | 186 | #else |
e1c7e324 CH |
187 | /* |
188 | * Define the dma api to allow compilation but not linking of | |
189 | * dma dependent code. Code that depends on the dma-mapping | |
190 | * API needs to set 'depends on HAS_DMA' in its Kconfig | |
191 | */ | |
5299709d BVA |
192 | extern const struct dma_map_ops bad_dma_ops; |
193 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) | |
e1c7e324 CH |
194 | { |
195 | return &bad_dma_ops; | |
196 | } | |
197 | #endif | |
198 | ||
199 | static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, | |
200 | size_t size, | |
201 | enum dma_data_direction dir, | |
00085f1e | 202 | unsigned long attrs) |
e1c7e324 | 203 | { |
5299709d | 204 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
205 | dma_addr_t addr; |
206 | ||
207 | kmemcheck_mark_initialized(ptr, size); | |
208 | BUG_ON(!valid_dma_direction(dir)); | |
209 | addr = ops->map_page(dev, virt_to_page(ptr), | |
8e99469a | 210 | offset_in_page(ptr), size, |
e1c7e324 CH |
211 | dir, attrs); |
212 | debug_dma_map_page(dev, virt_to_page(ptr), | |
8e99469a | 213 | offset_in_page(ptr), size, |
e1c7e324 CH |
214 | dir, addr, true); |
215 | return addr; | |
216 | } | |
217 | ||
218 | static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, | |
219 | size_t size, | |
220 | enum dma_data_direction dir, | |
00085f1e | 221 | unsigned long attrs) |
e1c7e324 | 222 | { |
5299709d | 223 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
224 | |
225 | BUG_ON(!valid_dma_direction(dir)); | |
226 | if (ops->unmap_page) | |
227 | ops->unmap_page(dev, addr, size, dir, attrs); | |
228 | debug_dma_unmap_page(dev, addr, size, dir, true); | |
229 | } | |
230 | ||
231 | /* | |
232 | * dma_maps_sg_attrs returns 0 on error and > 0 on success. | |
233 | * It should never return a value < 0. | |
234 | */ | |
235 | static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, | |
236 | int nents, enum dma_data_direction dir, | |
00085f1e | 237 | unsigned long attrs) |
e1c7e324 | 238 | { |
5299709d | 239 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
240 | int i, ents; |
241 | struct scatterlist *s; | |
242 | ||
243 | for_each_sg(sg, s, nents, i) | |
244 | kmemcheck_mark_initialized(sg_virt(s), s->length); | |
245 | BUG_ON(!valid_dma_direction(dir)); | |
246 | ents = ops->map_sg(dev, sg, nents, dir, attrs); | |
247 | BUG_ON(ents < 0); | |
248 | debug_dma_map_sg(dev, sg, nents, ents, dir); | |
249 | ||
250 | return ents; | |
251 | } | |
252 | ||
253 | static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, | |
254 | int nents, enum dma_data_direction dir, | |
00085f1e | 255 | unsigned long attrs) |
e1c7e324 | 256 | { |
5299709d | 257 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
258 | |
259 | BUG_ON(!valid_dma_direction(dir)); | |
260 | debug_dma_unmap_sg(dev, sg, nents, dir); | |
261 | if (ops->unmap_sg) | |
262 | ops->unmap_sg(dev, sg, nents, dir, attrs); | |
263 | } | |
264 | ||
0495c3d3 AD |
265 | static inline dma_addr_t dma_map_page_attrs(struct device *dev, |
266 | struct page *page, | |
267 | size_t offset, size_t size, | |
268 | enum dma_data_direction dir, | |
269 | unsigned long attrs) | |
e1c7e324 | 270 | { |
5299709d | 271 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
272 | dma_addr_t addr; |
273 | ||
274 | kmemcheck_mark_initialized(page_address(page) + offset, size); | |
275 | BUG_ON(!valid_dma_direction(dir)); | |
0495c3d3 | 276 | addr = ops->map_page(dev, page, offset, size, dir, attrs); |
e1c7e324 CH |
277 | debug_dma_map_page(dev, page, offset, size, dir, addr, false); |
278 | ||
279 | return addr; | |
280 | } | |
281 | ||
0495c3d3 AD |
282 | static inline void dma_unmap_page_attrs(struct device *dev, |
283 | dma_addr_t addr, size_t size, | |
284 | enum dma_data_direction dir, | |
285 | unsigned long attrs) | |
e1c7e324 | 286 | { |
5299709d | 287 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
288 | |
289 | BUG_ON(!valid_dma_direction(dir)); | |
290 | if (ops->unmap_page) | |
0495c3d3 | 291 | ops->unmap_page(dev, addr, size, dir, attrs); |
e1c7e324 CH |
292 | debug_dma_unmap_page(dev, addr, size, dir, false); |
293 | } | |
294 | ||
6f3d8796 NS |
295 | static inline dma_addr_t dma_map_resource(struct device *dev, |
296 | phys_addr_t phys_addr, | |
297 | size_t size, | |
298 | enum dma_data_direction dir, | |
299 | unsigned long attrs) | |
300 | { | |
5299709d | 301 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
302 | dma_addr_t addr; |
303 | ||
304 | BUG_ON(!valid_dma_direction(dir)); | |
305 | ||
306 | /* Don't allow RAM to be mapped */ | |
3757dc48 | 307 | BUG_ON(pfn_valid(PHYS_PFN(phys_addr))); |
6f3d8796 NS |
308 | |
309 | addr = phys_addr; | |
310 | if (ops->map_resource) | |
311 | addr = ops->map_resource(dev, phys_addr, size, dir, attrs); | |
312 | ||
313 | debug_dma_map_resource(dev, phys_addr, size, dir, addr); | |
314 | ||
315 | return addr; | |
316 | } | |
317 | ||
318 | static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr, | |
319 | size_t size, enum dma_data_direction dir, | |
320 | unsigned long attrs) | |
321 | { | |
5299709d | 322 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
323 | |
324 | BUG_ON(!valid_dma_direction(dir)); | |
325 | if (ops->unmap_resource) | |
326 | ops->unmap_resource(dev, addr, size, dir, attrs); | |
327 | debug_dma_unmap_resource(dev, addr, size, dir); | |
328 | } | |
329 | ||
e1c7e324 CH |
330 | static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, |
331 | size_t size, | |
332 | enum dma_data_direction dir) | |
333 | { | |
5299709d | 334 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
335 | |
336 | BUG_ON(!valid_dma_direction(dir)); | |
337 | if (ops->sync_single_for_cpu) | |
338 | ops->sync_single_for_cpu(dev, addr, size, dir); | |
339 | debug_dma_sync_single_for_cpu(dev, addr, size, dir); | |
340 | } | |
341 | ||
342 | static inline void dma_sync_single_for_device(struct device *dev, | |
343 | dma_addr_t addr, size_t size, | |
344 | enum dma_data_direction dir) | |
345 | { | |
5299709d | 346 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
347 | |
348 | BUG_ON(!valid_dma_direction(dir)); | |
349 | if (ops->sync_single_for_device) | |
350 | ops->sync_single_for_device(dev, addr, size, dir); | |
351 | debug_dma_sync_single_for_device(dev, addr, size, dir); | |
352 | } | |
353 | ||
354 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | |
355 | dma_addr_t addr, | |
356 | unsigned long offset, | |
357 | size_t size, | |
358 | enum dma_data_direction dir) | |
359 | { | |
360 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
361 | ||
362 | BUG_ON(!valid_dma_direction(dir)); | |
363 | if (ops->sync_single_for_cpu) | |
364 | ops->sync_single_for_cpu(dev, addr + offset, size, dir); | |
365 | debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); | |
366 | } | |
367 | ||
368 | static inline void dma_sync_single_range_for_device(struct device *dev, | |
369 | dma_addr_t addr, | |
370 | unsigned long offset, | |
371 | size_t size, | |
372 | enum dma_data_direction dir) | |
373 | { | |
374 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
375 | ||
376 | BUG_ON(!valid_dma_direction(dir)); | |
377 | if (ops->sync_single_for_device) | |
378 | ops->sync_single_for_device(dev, addr + offset, size, dir); | |
379 | debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); | |
380 | } | |
381 | ||
382 | static inline void | |
383 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
384 | int nelems, enum dma_data_direction dir) | |
385 | { | |
5299709d | 386 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
387 | |
388 | BUG_ON(!valid_dma_direction(dir)); | |
389 | if (ops->sync_sg_for_cpu) | |
390 | ops->sync_sg_for_cpu(dev, sg, nelems, dir); | |
391 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); | |
392 | } | |
393 | ||
394 | static inline void | |
395 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
396 | int nelems, enum dma_data_direction dir) | |
397 | { | |
5299709d | 398 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
399 | |
400 | BUG_ON(!valid_dma_direction(dir)); | |
401 | if (ops->sync_sg_for_device) | |
402 | ops->sync_sg_for_device(dev, sg, nelems, dir); | |
403 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); | |
404 | ||
405 | } | |
406 | ||
00085f1e KK |
407 | #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0) |
408 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | |
409 | #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, 0) | |
410 | #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, 0) | |
0495c3d3 AD |
411 | #define dma_map_page(d, p, o, s, r) dma_map_page_attrs(d, p, o, s, r, 0) |
412 | #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0) | |
e1c7e324 CH |
413 | |
414 | extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, | |
415 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
416 | ||
417 | void *dma_common_contiguous_remap(struct page *page, size_t size, | |
418 | unsigned long vm_flags, | |
419 | pgprot_t prot, const void *caller); | |
420 | ||
421 | void *dma_common_pages_remap(struct page **pages, size_t size, | |
422 | unsigned long vm_flags, pgprot_t prot, | |
423 | const void *caller); | |
424 | void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags); | |
425 | ||
426 | /** | |
427 | * dma_mmap_attrs - map a coherent DMA allocation into user space | |
428 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
429 | * @vma: vm_area_struct describing requested user mapping | |
430 | * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs | |
431 | * @handle: device-view address returned from dma_alloc_attrs | |
432 | * @size: size of memory originally requested in dma_alloc_attrs | |
433 | * @attrs: attributes of mapping properties requested in dma_alloc_attrs | |
434 | * | |
435 | * Map a coherent DMA buffer previously allocated by dma_alloc_attrs | |
436 | * into user space. The coherent DMA buffer must not be freed by the | |
437 | * driver until the user space mapping has been released. | |
438 | */ | |
439 | static inline int | |
440 | dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 441 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
e1c7e324 | 442 | { |
5299709d | 443 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
444 | BUG_ON(!ops); |
445 | if (ops->mmap) | |
446 | return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
447 | return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); | |
448 | } | |
449 | ||
00085f1e | 450 | #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0) |
e1c7e324 CH |
451 | |
452 | int | |
453 | dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, | |
454 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
455 | ||
456 | static inline int | |
457 | dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, | |
00085f1e KK |
458 | dma_addr_t dma_addr, size_t size, |
459 | unsigned long attrs) | |
e1c7e324 | 460 | { |
5299709d | 461 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
462 | BUG_ON(!ops); |
463 | if (ops->get_sgtable) | |
464 | return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, | |
465 | attrs); | |
466 | return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); | |
467 | } | |
468 | ||
00085f1e | 469 | #define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0) |
e1c7e324 CH |
470 | |
471 | #ifndef arch_dma_alloc_attrs | |
472 | #define arch_dma_alloc_attrs(dev, flag) (true) | |
473 | #endif | |
474 | ||
475 | static inline void *dma_alloc_attrs(struct device *dev, size_t size, | |
476 | dma_addr_t *dma_handle, gfp_t flag, | |
00085f1e | 477 | unsigned long attrs) |
e1c7e324 | 478 | { |
5299709d | 479 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
480 | void *cpu_addr; |
481 | ||
482 | BUG_ON(!ops); | |
483 | ||
484 | if (dma_alloc_from_coherent(dev, size, dma_handle, &cpu_addr)) | |
485 | return cpu_addr; | |
486 | ||
487 | if (!arch_dma_alloc_attrs(&dev, &flag)) | |
488 | return NULL; | |
489 | if (!ops->alloc) | |
490 | return NULL; | |
491 | ||
492 | cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); | |
493 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
494 | return cpu_addr; | |
495 | } | |
496 | ||
497 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
498 | void *cpu_addr, dma_addr_t dma_handle, | |
00085f1e | 499 | unsigned long attrs) |
e1c7e324 | 500 | { |
5299709d | 501 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
502 | |
503 | BUG_ON(!ops); | |
504 | WARN_ON(irqs_disabled()); | |
505 | ||
506 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) | |
507 | return; | |
508 | ||
d6b7eaeb | 509 | if (!ops->free || !cpu_addr) |
e1c7e324 CH |
510 | return; |
511 | ||
512 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
513 | ops->free(dev, size, cpu_addr, dma_handle, attrs); | |
514 | } | |
515 | ||
516 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
517 | dma_addr_t *dma_handle, gfp_t flag) | |
518 | { | |
00085f1e | 519 | return dma_alloc_attrs(dev, size, dma_handle, flag, 0); |
e1c7e324 CH |
520 | } |
521 | ||
522 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
523 | void *cpu_addr, dma_addr_t dma_handle) | |
524 | { | |
00085f1e | 525 | return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0); |
e1c7e324 CH |
526 | } |
527 | ||
528 | static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, | |
529 | dma_addr_t *dma_handle, gfp_t gfp) | |
530 | { | |
00085f1e KK |
531 | return dma_alloc_attrs(dev, size, dma_handle, gfp, |
532 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
533 | } |
534 | ||
535 | static inline void dma_free_noncoherent(struct device *dev, size_t size, | |
536 | void *cpu_addr, dma_addr_t dma_handle) | |
537 | { | |
00085f1e KK |
538 | dma_free_attrs(dev, size, cpu_addr, dma_handle, |
539 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
540 | } |
541 | ||
542 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
543 | { | |
544 | debug_dma_mapping_error(dev, dma_addr); | |
545 | ||
546 | if (get_dma_ops(dev)->mapping_error) | |
547 | return get_dma_ops(dev)->mapping_error(dev, dma_addr); | |
e1c7e324 | 548 | return 0; |
e1c7e324 CH |
549 | } |
550 | ||
e1c7e324 CH |
551 | static inline int dma_supported(struct device *dev, u64 mask) |
552 | { | |
5299709d | 553 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
554 | |
555 | if (!ops) | |
556 | return 0; | |
557 | if (!ops->dma_supported) | |
558 | return 1; | |
559 | return ops->dma_supported(dev, mask); | |
560 | } | |
e1c7e324 CH |
561 | |
562 | #ifndef HAVE_ARCH_DMA_SET_MASK | |
563 | static inline int dma_set_mask(struct device *dev, u64 mask) | |
564 | { | |
e1c7e324 CH |
565 | if (!dev->dma_mask || !dma_supported(dev, mask)) |
566 | return -EIO; | |
567 | *dev->dma_mask = mask; | |
568 | return 0; | |
569 | } | |
1b0fac45 | 570 | #endif |
1da177e4 | 571 | |
589fc9a6 FT |
572 | static inline u64 dma_get_mask(struct device *dev) |
573 | { | |
07a2c01a | 574 | if (dev && dev->dma_mask && *dev->dma_mask) |
589fc9a6 | 575 | return *dev->dma_mask; |
284901a9 | 576 | return DMA_BIT_MASK(32); |
589fc9a6 FT |
577 | } |
578 | ||
58af4a24 | 579 | #ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK |
710224fa FT |
580 | int dma_set_coherent_mask(struct device *dev, u64 mask); |
581 | #else | |
6a1961f4 FT |
582 | static inline int dma_set_coherent_mask(struct device *dev, u64 mask) |
583 | { | |
584 | if (!dma_supported(dev, mask)) | |
585 | return -EIO; | |
586 | dev->coherent_dma_mask = mask; | |
587 | return 0; | |
588 | } | |
710224fa | 589 | #endif |
6a1961f4 | 590 | |
4aa806b7 RK |
591 | /* |
592 | * Set both the DMA mask and the coherent DMA mask to the same thing. | |
593 | * Note that we don't check the return value from dma_set_coherent_mask() | |
594 | * as the DMA API guarantees that the coherent DMA mask can be set to | |
595 | * the same or smaller than the streaming DMA mask. | |
596 | */ | |
597 | static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask) | |
598 | { | |
599 | int rc = dma_set_mask(dev, mask); | |
600 | if (rc == 0) | |
601 | dma_set_coherent_mask(dev, mask); | |
602 | return rc; | |
603 | } | |
604 | ||
fa6a8d6d RK |
605 | /* |
606 | * Similar to the above, except it deals with the case where the device | |
607 | * does not have dev->dma_mask appropriately setup. | |
608 | */ | |
609 | static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask) | |
610 | { | |
611 | dev->dma_mask = &dev->coherent_dma_mask; | |
612 | return dma_set_mask_and_coherent(dev, mask); | |
613 | } | |
614 | ||
1da177e4 LT |
615 | extern u64 dma_get_required_mask(struct device *dev); |
616 | ||
a3a60f81 | 617 | #ifndef arch_setup_dma_ops |
97890ba9 | 618 | static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, |
53c92d79 | 619 | u64 size, const struct iommu_ops *iommu, |
97890ba9 WD |
620 | bool coherent) { } |
621 | #endif | |
622 | ||
623 | #ifndef arch_teardown_dma_ops | |
624 | static inline void arch_teardown_dma_ops(struct device *dev) { } | |
591c1ee4 SS |
625 | #endif |
626 | ||
6b7b6510 FT |
627 | static inline unsigned int dma_get_max_seg_size(struct device *dev) |
628 | { | |
002edb6f RM |
629 | if (dev->dma_parms && dev->dma_parms->max_segment_size) |
630 | return dev->dma_parms->max_segment_size; | |
631 | return SZ_64K; | |
6b7b6510 FT |
632 | } |
633 | ||
634 | static inline unsigned int dma_set_max_seg_size(struct device *dev, | |
635 | unsigned int size) | |
636 | { | |
637 | if (dev->dma_parms) { | |
638 | dev->dma_parms->max_segment_size = size; | |
639 | return 0; | |
002edb6f RM |
640 | } |
641 | return -EIO; | |
6b7b6510 FT |
642 | } |
643 | ||
d22a6966 FT |
644 | static inline unsigned long dma_get_seg_boundary(struct device *dev) |
645 | { | |
002edb6f RM |
646 | if (dev->dma_parms && dev->dma_parms->segment_boundary_mask) |
647 | return dev->dma_parms->segment_boundary_mask; | |
648 | return DMA_BIT_MASK(32); | |
d22a6966 FT |
649 | } |
650 | ||
651 | static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) | |
652 | { | |
653 | if (dev->dma_parms) { | |
654 | dev->dma_parms->segment_boundary_mask = mask; | |
655 | return 0; | |
002edb6f RM |
656 | } |
657 | return -EIO; | |
d22a6966 FT |
658 | } |
659 | ||
00c8f162 SS |
660 | #ifndef dma_max_pfn |
661 | static inline unsigned long dma_max_pfn(struct device *dev) | |
662 | { | |
663 | return *dev->dma_mask >> PAGE_SHIFT; | |
664 | } | |
665 | #endif | |
666 | ||
842fa69f AM |
667 | static inline void *dma_zalloc_coherent(struct device *dev, size_t size, |
668 | dma_addr_t *dma_handle, gfp_t flag) | |
669 | { | |
ede23fa8 JP |
670 | void *ret = dma_alloc_coherent(dev, size, dma_handle, |
671 | flag | __GFP_ZERO); | |
842fa69f AM |
672 | return ret; |
673 | } | |
674 | ||
e259f191 | 675 | #ifdef CONFIG_HAS_DMA |
4565f017 FT |
676 | static inline int dma_get_cache_alignment(void) |
677 | { | |
678 | #ifdef ARCH_DMA_MINALIGN | |
679 | return ARCH_DMA_MINALIGN; | |
680 | #endif | |
681 | return 1; | |
682 | } | |
e259f191 | 683 | #endif |
4565f017 | 684 | |
1da177e4 LT |
685 | /* flags for the coherent memory api */ |
686 | #define DMA_MEMORY_MAP 0x01 | |
687 | #define DMA_MEMORY_IO 0x02 | |
688 | #define DMA_MEMORY_INCLUDES_CHILDREN 0x04 | |
689 | #define DMA_MEMORY_EXCLUSIVE 0x08 | |
690 | ||
20d666e4 CH |
691 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
692 | int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, | |
693 | dma_addr_t device_addr, size_t size, int flags); | |
694 | void dma_release_declared_memory(struct device *dev); | |
695 | void *dma_mark_declared_memory_occupied(struct device *dev, | |
696 | dma_addr_t device_addr, size_t size); | |
697 | #else | |
1da177e4 | 698 | static inline int |
88a984ba | 699 | dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, |
1da177e4 LT |
700 | dma_addr_t device_addr, size_t size, int flags) |
701 | { | |
702 | return 0; | |
703 | } | |
704 | ||
705 | static inline void | |
706 | dma_release_declared_memory(struct device *dev) | |
707 | { | |
708 | } | |
709 | ||
710 | static inline void * | |
711 | dma_mark_declared_memory_occupied(struct device *dev, | |
712 | dma_addr_t device_addr, size_t size) | |
713 | { | |
714 | return ERR_PTR(-EBUSY); | |
715 | } | |
20d666e4 | 716 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 717 | |
09515ef5 S |
718 | #ifdef CONFIG_HAS_DMA |
719 | int dma_configure(struct device *dev); | |
720 | void dma_deconfigure(struct device *dev); | |
721 | #else | |
722 | static inline int dma_configure(struct device *dev) | |
723 | { | |
724 | return 0; | |
725 | } | |
726 | ||
727 | static inline void dma_deconfigure(struct device *dev) {} | |
728 | #endif | |
729 | ||
9ac7849e TH |
730 | /* |
731 | * Managed DMA API | |
732 | */ | |
733 | extern void *dmam_alloc_coherent(struct device *dev, size_t size, | |
734 | dma_addr_t *dma_handle, gfp_t gfp); | |
735 | extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, | |
736 | dma_addr_t dma_handle); | |
63d36c95 CH |
737 | extern void *dmam_alloc_attrs(struct device *dev, size_t size, |
738 | dma_addr_t *dma_handle, gfp_t gfp, | |
739 | unsigned long attrs); | |
20d666e4 | 740 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
88a984ba BH |
741 | extern int dmam_declare_coherent_memory(struct device *dev, |
742 | phys_addr_t phys_addr, | |
9ac7849e TH |
743 | dma_addr_t device_addr, size_t size, |
744 | int flags); | |
745 | extern void dmam_release_declared_memory(struct device *dev); | |
20d666e4 | 746 | #else /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
9ac7849e | 747 | static inline int dmam_declare_coherent_memory(struct device *dev, |
88a984ba | 748 | phys_addr_t phys_addr, dma_addr_t device_addr, |
9ac7849e TH |
749 | size_t size, gfp_t gfp) |
750 | { | |
751 | return 0; | |
752 | } | |
1da177e4 | 753 | |
9ac7849e TH |
754 | static inline void dmam_release_declared_memory(struct device *dev) |
755 | { | |
756 | } | |
20d666e4 | 757 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 758 | |
f6e45661 LR |
759 | static inline void *dma_alloc_wc(struct device *dev, size_t size, |
760 | dma_addr_t *dma_addr, gfp_t gfp) | |
b4bbb107 | 761 | { |
00085f1e KK |
762 | return dma_alloc_attrs(dev, size, dma_addr, gfp, |
763 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 764 | } |
f6e45661 LR |
765 | #ifndef dma_alloc_writecombine |
766 | #define dma_alloc_writecombine dma_alloc_wc | |
767 | #endif | |
b4bbb107 | 768 | |
f6e45661 LR |
769 | static inline void dma_free_wc(struct device *dev, size_t size, |
770 | void *cpu_addr, dma_addr_t dma_addr) | |
b4bbb107 | 771 | { |
00085f1e KK |
772 | return dma_free_attrs(dev, size, cpu_addr, dma_addr, |
773 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 774 | } |
f6e45661 LR |
775 | #ifndef dma_free_writecombine |
776 | #define dma_free_writecombine dma_free_wc | |
777 | #endif | |
b4bbb107 | 778 | |
f6e45661 LR |
779 | static inline int dma_mmap_wc(struct device *dev, |
780 | struct vm_area_struct *vma, | |
781 | void *cpu_addr, dma_addr_t dma_addr, | |
782 | size_t size) | |
b4bbb107 | 783 | { |
00085f1e KK |
784 | return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, |
785 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 786 | } |
f6e45661 LR |
787 | #ifndef dma_mmap_writecombine |
788 | #define dma_mmap_writecombine dma_mmap_wc | |
789 | #endif | |
74bc7cee | 790 | |
2481366a | 791 | #if defined(CONFIG_NEED_DMA_MAP_STATE) || defined(CONFIG_DMA_API_DEBUG) |
0acedc12 FT |
792 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME |
793 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME | |
794 | #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | |
795 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | |
796 | #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | |
797 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | |
798 | #else | |
799 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) | |
800 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) | |
801 | #define dma_unmap_addr(PTR, ADDR_NAME) (0) | |
802 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
803 | #define dma_unmap_len(PTR, LEN_NAME) (0) | |
804 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
805 | #endif | |
806 | ||
9ac7849e | 807 | #endif |