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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
96532bab RD |
2 | #ifndef _LINUX_DMA_MAPPING_H |
3 | #define _LINUX_DMA_MAPPING_H | |
1da177e4 | 4 | |
002edb6f | 5 | #include <linux/sizes.h> |
842fa69f | 6 | #include <linux/string.h> |
1da177e4 LT |
7 | #include <linux/device.h> |
8 | #include <linux/err.h> | |
e1c7e324 | 9 | #include <linux/dma-debug.h> |
b7f080cf | 10 | #include <linux/dma-direction.h> |
f0402a26 | 11 | #include <linux/scatterlist.h> |
e1c7e324 CH |
12 | #include <linux/kmemcheck.h> |
13 | #include <linux/bug.h> | |
648babb7 | 14 | #include <linux/mem_encrypt.h> |
1da177e4 | 15 | |
00085f1e KK |
16 | /** |
17 | * List of possible attributes associated with a DMA mapping. The semantics | |
18 | * of each attribute should be defined in Documentation/DMA-attributes.txt. | |
19 | * | |
20 | * DMA_ATTR_WRITE_BARRIER: DMA to a memory region with this attribute | |
21 | * forces all pending DMA writes to complete. | |
22 | */ | |
23 | #define DMA_ATTR_WRITE_BARRIER (1UL << 0) | |
24 | /* | |
25 | * DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping | |
26 | * may be weakly ordered, that is that reads and writes may pass each other. | |
27 | */ | |
28 | #define DMA_ATTR_WEAK_ORDERING (1UL << 1) | |
29 | /* | |
30 | * DMA_ATTR_WRITE_COMBINE: Specifies that writes to the mapping may be | |
31 | * buffered to improve performance. | |
32 | */ | |
33 | #define DMA_ATTR_WRITE_COMBINE (1UL << 2) | |
34 | /* | |
35 | * DMA_ATTR_NON_CONSISTENT: Lets the platform to choose to return either | |
36 | * consistent or non-consistent memory as it sees fit. | |
37 | */ | |
38 | #define DMA_ATTR_NON_CONSISTENT (1UL << 3) | |
39 | /* | |
40 | * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platform to avoid creating a kernel | |
41 | * virtual mapping for the allocated buffer. | |
42 | */ | |
43 | #define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4) | |
44 | /* | |
45 | * DMA_ATTR_SKIP_CPU_SYNC: Allows platform code to skip synchronization of | |
46 | * the CPU cache for the given buffer assuming that it has been already | |
47 | * transferred to 'device' domain. | |
48 | */ | |
49 | #define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5) | |
50 | /* | |
51 | * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguous allocation of the buffer | |
52 | * in physical memory. | |
53 | */ | |
54 | #define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6) | |
55 | /* | |
56 | * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint to the DMA-mapping subsystem | |
57 | * that it's probably not worth the time to try to allocate memory to in a way | |
58 | * that gives better TLB efficiency. | |
59 | */ | |
60 | #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7) | |
a9a62c93 MFO |
61 | /* |
62 | * DMA_ATTR_NO_WARN: This tells the DMA-mapping subsystem to suppress | |
63 | * allocation failure reports (similarly to __GFP_NOWARN). | |
64 | */ | |
65 | #define DMA_ATTR_NO_WARN (1UL << 8) | |
00085f1e | 66 | |
b2fb3664 MH |
67 | /* |
68 | * DMA_ATTR_PRIVILEGED: used to indicate that the buffer is fully | |
69 | * accessible at an elevated privilege level (and ideally inaccessible or | |
70 | * at least read-only at lesser-privileged levels). | |
71 | */ | |
72 | #define DMA_ATTR_PRIVILEGED (1UL << 9) | |
73 | ||
77f2ea2f BH |
74 | /* |
75 | * A dma_addr_t can hold any valid DMA or bus address for the platform. | |
76 | * It can be given to a device to use as a DMA source or target. A CPU cannot | |
77 | * reference a dma_addr_t directly because there may be translation between | |
78 | * its physical address space and the bus address space. | |
79 | */ | |
f0402a26 | 80 | struct dma_map_ops { |
613c4578 MS |
81 | void* (*alloc)(struct device *dev, size_t size, |
82 | dma_addr_t *dma_handle, gfp_t gfp, | |
00085f1e | 83 | unsigned long attrs); |
613c4578 MS |
84 | void (*free)(struct device *dev, size_t size, |
85 | void *vaddr, dma_addr_t dma_handle, | |
00085f1e | 86 | unsigned long attrs); |
9adc5374 | 87 | int (*mmap)(struct device *, struct vm_area_struct *, |
00085f1e KK |
88 | void *, dma_addr_t, size_t, |
89 | unsigned long attrs); | |
9adc5374 | 90 | |
d2b7428e | 91 | int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *, |
00085f1e | 92 | dma_addr_t, size_t, unsigned long attrs); |
d2b7428e | 93 | |
f0402a26 FT |
94 | dma_addr_t (*map_page)(struct device *dev, struct page *page, |
95 | unsigned long offset, size_t size, | |
96 | enum dma_data_direction dir, | |
00085f1e | 97 | unsigned long attrs); |
f0402a26 FT |
98 | void (*unmap_page)(struct device *dev, dma_addr_t dma_handle, |
99 | size_t size, enum dma_data_direction dir, | |
00085f1e | 100 | unsigned long attrs); |
04abab69 RRD |
101 | /* |
102 | * map_sg returns 0 on error and a value > 0 on success. | |
103 | * It should never return a value < 0. | |
104 | */ | |
f0402a26 FT |
105 | int (*map_sg)(struct device *dev, struct scatterlist *sg, |
106 | int nents, enum dma_data_direction dir, | |
00085f1e | 107 | unsigned long attrs); |
f0402a26 FT |
108 | void (*unmap_sg)(struct device *dev, |
109 | struct scatterlist *sg, int nents, | |
110 | enum dma_data_direction dir, | |
00085f1e | 111 | unsigned long attrs); |
ba409b31 NS |
112 | dma_addr_t (*map_resource)(struct device *dev, phys_addr_t phys_addr, |
113 | size_t size, enum dma_data_direction dir, | |
114 | unsigned long attrs); | |
115 | void (*unmap_resource)(struct device *dev, dma_addr_t dma_handle, | |
116 | size_t size, enum dma_data_direction dir, | |
117 | unsigned long attrs); | |
f0402a26 FT |
118 | void (*sync_single_for_cpu)(struct device *dev, |
119 | dma_addr_t dma_handle, size_t size, | |
120 | enum dma_data_direction dir); | |
121 | void (*sync_single_for_device)(struct device *dev, | |
122 | dma_addr_t dma_handle, size_t size, | |
123 | enum dma_data_direction dir); | |
f0402a26 FT |
124 | void (*sync_sg_for_cpu)(struct device *dev, |
125 | struct scatterlist *sg, int nents, | |
126 | enum dma_data_direction dir); | |
127 | void (*sync_sg_for_device)(struct device *dev, | |
128 | struct scatterlist *sg, int nents, | |
129 | enum dma_data_direction dir); | |
c9eb6172 CH |
130 | void (*cache_sync)(struct device *dev, void *vaddr, size_t size, |
131 | enum dma_data_direction direction); | |
f0402a26 FT |
132 | int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); |
133 | int (*dma_supported)(struct device *dev, u64 mask); | |
3a8f7558 MM |
134 | #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK |
135 | u64 (*get_required_mask)(struct device *dev); | |
136 | #endif | |
f0402a26 FT |
137 | int is_phys; |
138 | }; | |
139 | ||
5299709d | 140 | extern const struct dma_map_ops dma_noop_ops; |
551199ac | 141 | extern const struct dma_map_ops dma_virt_ops; |
a8463d4b | 142 | |
8f286c33 | 143 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
34c65384 | 144 | |
32e8f702 JB |
145 | #define DMA_MASK_NONE 0x0ULL |
146 | ||
d6bd3a39 REB |
147 | static inline int valid_dma_direction(int dma_direction) |
148 | { | |
149 | return ((dma_direction == DMA_BIDIRECTIONAL) || | |
150 | (dma_direction == DMA_TO_DEVICE) || | |
151 | (dma_direction == DMA_FROM_DEVICE)); | |
152 | } | |
153 | ||
32e8f702 JB |
154 | static inline int is_device_dma_capable(struct device *dev) |
155 | { | |
156 | return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE; | |
157 | } | |
158 | ||
20d666e4 CH |
159 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
160 | /* | |
161 | * These three functions are only for dma allocator. | |
162 | * Don't use them in device drivers. | |
163 | */ | |
43fc509c | 164 | int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size, |
20d666e4 | 165 | dma_addr_t *dma_handle, void **ret); |
43fc509c | 166 | int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr); |
20d666e4 | 167 | |
43fc509c | 168 | int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma, |
20d666e4 | 169 | void *cpu_addr, size_t size, int *ret); |
43fc509c VM |
170 | |
171 | void *dma_alloc_from_global_coherent(ssize_t size, dma_addr_t *dma_handle); | |
172 | int dma_release_from_global_coherent(int order, void *vaddr); | |
173 | int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr, | |
174 | size_t size, int *ret); | |
175 | ||
20d666e4 | 176 | #else |
43fc509c VM |
177 | #define dma_alloc_from_dev_coherent(dev, size, handle, ret) (0) |
178 | #define dma_release_from_dev_coherent(dev, order, vaddr) (0) | |
179 | #define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0) | |
180 | ||
181 | static inline void *dma_alloc_from_global_coherent(ssize_t size, | |
182 | dma_addr_t *dma_handle) | |
183 | { | |
184 | return NULL; | |
185 | } | |
186 | ||
187 | static inline int dma_release_from_global_coherent(int order, void *vaddr) | |
188 | { | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma, | |
193 | void *cpu_addr, size_t size, | |
194 | int *ret) | |
195 | { | |
196 | return 0; | |
197 | } | |
20d666e4 CH |
198 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
199 | ||
1b0fac45 | 200 | #ifdef CONFIG_HAS_DMA |
1da177e4 | 201 | #include <asm/dma-mapping.h> |
815dd187 BVA |
202 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) |
203 | { | |
204 | if (dev && dev->dma_ops) | |
205 | return dev->dma_ops; | |
206 | return get_arch_dma_ops(dev ? dev->bus : NULL); | |
207 | } | |
208 | ||
ca6e8e10 BVA |
209 | static inline void set_dma_ops(struct device *dev, |
210 | const struct dma_map_ops *dma_ops) | |
211 | { | |
212 | dev->dma_ops = dma_ops; | |
213 | } | |
1b0fac45 | 214 | #else |
e1c7e324 CH |
215 | /* |
216 | * Define the dma api to allow compilation but not linking of | |
217 | * dma dependent code. Code that depends on the dma-mapping | |
218 | * API needs to set 'depends on HAS_DMA' in its Kconfig | |
219 | */ | |
5299709d BVA |
220 | extern const struct dma_map_ops bad_dma_ops; |
221 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) | |
e1c7e324 CH |
222 | { |
223 | return &bad_dma_ops; | |
224 | } | |
225 | #endif | |
226 | ||
227 | static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, | |
228 | size_t size, | |
229 | enum dma_data_direction dir, | |
00085f1e | 230 | unsigned long attrs) |
e1c7e324 | 231 | { |
5299709d | 232 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
233 | dma_addr_t addr; |
234 | ||
235 | kmemcheck_mark_initialized(ptr, size); | |
236 | BUG_ON(!valid_dma_direction(dir)); | |
237 | addr = ops->map_page(dev, virt_to_page(ptr), | |
8e99469a | 238 | offset_in_page(ptr), size, |
e1c7e324 CH |
239 | dir, attrs); |
240 | debug_dma_map_page(dev, virt_to_page(ptr), | |
8e99469a | 241 | offset_in_page(ptr), size, |
e1c7e324 CH |
242 | dir, addr, true); |
243 | return addr; | |
244 | } | |
245 | ||
246 | static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, | |
247 | size_t size, | |
248 | enum dma_data_direction dir, | |
00085f1e | 249 | unsigned long attrs) |
e1c7e324 | 250 | { |
5299709d | 251 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
252 | |
253 | BUG_ON(!valid_dma_direction(dir)); | |
254 | if (ops->unmap_page) | |
255 | ops->unmap_page(dev, addr, size, dir, attrs); | |
256 | debug_dma_unmap_page(dev, addr, size, dir, true); | |
257 | } | |
258 | ||
259 | /* | |
260 | * dma_maps_sg_attrs returns 0 on error and > 0 on success. | |
261 | * It should never return a value < 0. | |
262 | */ | |
263 | static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, | |
264 | int nents, enum dma_data_direction dir, | |
00085f1e | 265 | unsigned long attrs) |
e1c7e324 | 266 | { |
5299709d | 267 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
268 | int i, ents; |
269 | struct scatterlist *s; | |
270 | ||
271 | for_each_sg(sg, s, nents, i) | |
272 | kmemcheck_mark_initialized(sg_virt(s), s->length); | |
273 | BUG_ON(!valid_dma_direction(dir)); | |
274 | ents = ops->map_sg(dev, sg, nents, dir, attrs); | |
275 | BUG_ON(ents < 0); | |
276 | debug_dma_map_sg(dev, sg, nents, ents, dir); | |
277 | ||
278 | return ents; | |
279 | } | |
280 | ||
281 | static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, | |
282 | int nents, enum dma_data_direction dir, | |
00085f1e | 283 | unsigned long attrs) |
e1c7e324 | 284 | { |
5299709d | 285 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
286 | |
287 | BUG_ON(!valid_dma_direction(dir)); | |
288 | debug_dma_unmap_sg(dev, sg, nents, dir); | |
289 | if (ops->unmap_sg) | |
290 | ops->unmap_sg(dev, sg, nents, dir, attrs); | |
291 | } | |
292 | ||
0495c3d3 AD |
293 | static inline dma_addr_t dma_map_page_attrs(struct device *dev, |
294 | struct page *page, | |
295 | size_t offset, size_t size, | |
296 | enum dma_data_direction dir, | |
297 | unsigned long attrs) | |
e1c7e324 | 298 | { |
5299709d | 299 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
300 | dma_addr_t addr; |
301 | ||
302 | kmemcheck_mark_initialized(page_address(page) + offset, size); | |
303 | BUG_ON(!valid_dma_direction(dir)); | |
0495c3d3 | 304 | addr = ops->map_page(dev, page, offset, size, dir, attrs); |
e1c7e324 CH |
305 | debug_dma_map_page(dev, page, offset, size, dir, addr, false); |
306 | ||
307 | return addr; | |
308 | } | |
309 | ||
0495c3d3 AD |
310 | static inline void dma_unmap_page_attrs(struct device *dev, |
311 | dma_addr_t addr, size_t size, | |
312 | enum dma_data_direction dir, | |
313 | unsigned long attrs) | |
e1c7e324 | 314 | { |
5299709d | 315 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
316 | |
317 | BUG_ON(!valid_dma_direction(dir)); | |
318 | if (ops->unmap_page) | |
0495c3d3 | 319 | ops->unmap_page(dev, addr, size, dir, attrs); |
e1c7e324 CH |
320 | debug_dma_unmap_page(dev, addr, size, dir, false); |
321 | } | |
322 | ||
6f3d8796 NS |
323 | static inline dma_addr_t dma_map_resource(struct device *dev, |
324 | phys_addr_t phys_addr, | |
325 | size_t size, | |
326 | enum dma_data_direction dir, | |
327 | unsigned long attrs) | |
328 | { | |
5299709d | 329 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
330 | dma_addr_t addr; |
331 | ||
332 | BUG_ON(!valid_dma_direction(dir)); | |
333 | ||
334 | /* Don't allow RAM to be mapped */ | |
3757dc48 | 335 | BUG_ON(pfn_valid(PHYS_PFN(phys_addr))); |
6f3d8796 NS |
336 | |
337 | addr = phys_addr; | |
338 | if (ops->map_resource) | |
339 | addr = ops->map_resource(dev, phys_addr, size, dir, attrs); | |
340 | ||
341 | debug_dma_map_resource(dev, phys_addr, size, dir, addr); | |
342 | ||
343 | return addr; | |
344 | } | |
345 | ||
346 | static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr, | |
347 | size_t size, enum dma_data_direction dir, | |
348 | unsigned long attrs) | |
349 | { | |
5299709d | 350 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
351 | |
352 | BUG_ON(!valid_dma_direction(dir)); | |
353 | if (ops->unmap_resource) | |
354 | ops->unmap_resource(dev, addr, size, dir, attrs); | |
355 | debug_dma_unmap_resource(dev, addr, size, dir); | |
356 | } | |
357 | ||
e1c7e324 CH |
358 | static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, |
359 | size_t size, | |
360 | enum dma_data_direction dir) | |
361 | { | |
5299709d | 362 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
363 | |
364 | BUG_ON(!valid_dma_direction(dir)); | |
365 | if (ops->sync_single_for_cpu) | |
366 | ops->sync_single_for_cpu(dev, addr, size, dir); | |
367 | debug_dma_sync_single_for_cpu(dev, addr, size, dir); | |
368 | } | |
369 | ||
370 | static inline void dma_sync_single_for_device(struct device *dev, | |
371 | dma_addr_t addr, size_t size, | |
372 | enum dma_data_direction dir) | |
373 | { | |
5299709d | 374 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
375 | |
376 | BUG_ON(!valid_dma_direction(dir)); | |
377 | if (ops->sync_single_for_device) | |
378 | ops->sync_single_for_device(dev, addr, size, dir); | |
379 | debug_dma_sync_single_for_device(dev, addr, size, dir); | |
380 | } | |
381 | ||
382 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | |
383 | dma_addr_t addr, | |
384 | unsigned long offset, | |
385 | size_t size, | |
386 | enum dma_data_direction dir) | |
387 | { | |
388 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
389 | ||
390 | BUG_ON(!valid_dma_direction(dir)); | |
391 | if (ops->sync_single_for_cpu) | |
392 | ops->sync_single_for_cpu(dev, addr + offset, size, dir); | |
393 | debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); | |
394 | } | |
395 | ||
396 | static inline void dma_sync_single_range_for_device(struct device *dev, | |
397 | dma_addr_t addr, | |
398 | unsigned long offset, | |
399 | size_t size, | |
400 | enum dma_data_direction dir) | |
401 | { | |
402 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
403 | ||
404 | BUG_ON(!valid_dma_direction(dir)); | |
405 | if (ops->sync_single_for_device) | |
406 | ops->sync_single_for_device(dev, addr + offset, size, dir); | |
407 | debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); | |
408 | } | |
409 | ||
410 | static inline void | |
411 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
412 | int nelems, enum dma_data_direction dir) | |
413 | { | |
5299709d | 414 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
415 | |
416 | BUG_ON(!valid_dma_direction(dir)); | |
417 | if (ops->sync_sg_for_cpu) | |
418 | ops->sync_sg_for_cpu(dev, sg, nelems, dir); | |
419 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); | |
420 | } | |
421 | ||
422 | static inline void | |
423 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
424 | int nelems, enum dma_data_direction dir) | |
425 | { | |
5299709d | 426 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
427 | |
428 | BUG_ON(!valid_dma_direction(dir)); | |
429 | if (ops->sync_sg_for_device) | |
430 | ops->sync_sg_for_device(dev, sg, nelems, dir); | |
431 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); | |
432 | ||
433 | } | |
434 | ||
00085f1e KK |
435 | #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0) |
436 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | |
437 | #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, 0) | |
438 | #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, 0) | |
0495c3d3 AD |
439 | #define dma_map_page(d, p, o, s, r) dma_map_page_attrs(d, p, o, s, r, 0) |
440 | #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0) | |
e1c7e324 | 441 | |
c9eb6172 CH |
442 | static inline void |
443 | dma_cache_sync(struct device *dev, void *vaddr, size_t size, | |
444 | enum dma_data_direction dir) | |
445 | { | |
446 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
447 | ||
448 | BUG_ON(!valid_dma_direction(dir)); | |
449 | if (ops->cache_sync) | |
450 | ops->cache_sync(dev, vaddr, size, dir); | |
451 | } | |
452 | ||
e1c7e324 CH |
453 | extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, |
454 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
455 | ||
456 | void *dma_common_contiguous_remap(struct page *page, size_t size, | |
457 | unsigned long vm_flags, | |
458 | pgprot_t prot, const void *caller); | |
459 | ||
460 | void *dma_common_pages_remap(struct page **pages, size_t size, | |
461 | unsigned long vm_flags, pgprot_t prot, | |
462 | const void *caller); | |
463 | void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags); | |
464 | ||
465 | /** | |
466 | * dma_mmap_attrs - map a coherent DMA allocation into user space | |
467 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
468 | * @vma: vm_area_struct describing requested user mapping | |
469 | * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs | |
470 | * @handle: device-view address returned from dma_alloc_attrs | |
471 | * @size: size of memory originally requested in dma_alloc_attrs | |
472 | * @attrs: attributes of mapping properties requested in dma_alloc_attrs | |
473 | * | |
474 | * Map a coherent DMA buffer previously allocated by dma_alloc_attrs | |
475 | * into user space. The coherent DMA buffer must not be freed by the | |
476 | * driver until the user space mapping has been released. | |
477 | */ | |
478 | static inline int | |
479 | dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 480 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
e1c7e324 | 481 | { |
5299709d | 482 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
483 | BUG_ON(!ops); |
484 | if (ops->mmap) | |
485 | return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
486 | return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); | |
487 | } | |
488 | ||
00085f1e | 489 | #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0) |
e1c7e324 CH |
490 | |
491 | int | |
492 | dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, | |
493 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
494 | ||
495 | static inline int | |
496 | dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, | |
00085f1e KK |
497 | dma_addr_t dma_addr, size_t size, |
498 | unsigned long attrs) | |
e1c7e324 | 499 | { |
5299709d | 500 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
501 | BUG_ON(!ops); |
502 | if (ops->get_sgtable) | |
503 | return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, | |
504 | attrs); | |
505 | return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); | |
506 | } | |
507 | ||
00085f1e | 508 | #define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0) |
e1c7e324 CH |
509 | |
510 | #ifndef arch_dma_alloc_attrs | |
511 | #define arch_dma_alloc_attrs(dev, flag) (true) | |
512 | #endif | |
513 | ||
514 | static inline void *dma_alloc_attrs(struct device *dev, size_t size, | |
515 | dma_addr_t *dma_handle, gfp_t flag, | |
00085f1e | 516 | unsigned long attrs) |
e1c7e324 | 517 | { |
5299709d | 518 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
519 | void *cpu_addr; |
520 | ||
521 | BUG_ON(!ops); | |
522 | ||
43fc509c | 523 | if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) |
e1c7e324 CH |
524 | return cpu_addr; |
525 | ||
526 | if (!arch_dma_alloc_attrs(&dev, &flag)) | |
527 | return NULL; | |
528 | if (!ops->alloc) | |
529 | return NULL; | |
530 | ||
531 | cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); | |
532 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
533 | return cpu_addr; | |
534 | } | |
535 | ||
536 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
537 | void *cpu_addr, dma_addr_t dma_handle, | |
00085f1e | 538 | unsigned long attrs) |
e1c7e324 | 539 | { |
5299709d | 540 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
541 | |
542 | BUG_ON(!ops); | |
543 | WARN_ON(irqs_disabled()); | |
544 | ||
43fc509c | 545 | if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr)) |
e1c7e324 CH |
546 | return; |
547 | ||
d6b7eaeb | 548 | if (!ops->free || !cpu_addr) |
e1c7e324 CH |
549 | return; |
550 | ||
551 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
552 | ops->free(dev, size, cpu_addr, dma_handle, attrs); | |
553 | } | |
554 | ||
555 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
556 | dma_addr_t *dma_handle, gfp_t flag) | |
557 | { | |
00085f1e | 558 | return dma_alloc_attrs(dev, size, dma_handle, flag, 0); |
e1c7e324 CH |
559 | } |
560 | ||
561 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
562 | void *cpu_addr, dma_addr_t dma_handle) | |
563 | { | |
00085f1e | 564 | return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0); |
e1c7e324 CH |
565 | } |
566 | ||
e1c7e324 CH |
567 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
568 | { | |
5237e95f | 569 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 | 570 | |
5237e95f RM |
571 | debug_dma_mapping_error(dev, dma_addr); |
572 | if (ops->mapping_error) | |
573 | return ops->mapping_error(dev, dma_addr); | |
e1c7e324 | 574 | return 0; |
e1c7e324 CH |
575 | } |
576 | ||
648babb7 TL |
577 | static inline void dma_check_mask(struct device *dev, u64 mask) |
578 | { | |
579 | if (sme_active() && (mask < (((u64)sme_get_me_mask() << 1) - 1))) | |
580 | dev_warn(dev, "SME is active, device will require DMA bounce buffers\n"); | |
581 | } | |
582 | ||
e1c7e324 CH |
583 | static inline int dma_supported(struct device *dev, u64 mask) |
584 | { | |
5299709d | 585 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
586 | |
587 | if (!ops) | |
588 | return 0; | |
589 | if (!ops->dma_supported) | |
590 | return 1; | |
591 | return ops->dma_supported(dev, mask); | |
592 | } | |
e1c7e324 CH |
593 | |
594 | #ifndef HAVE_ARCH_DMA_SET_MASK | |
595 | static inline int dma_set_mask(struct device *dev, u64 mask) | |
596 | { | |
e1c7e324 CH |
597 | if (!dev->dma_mask || !dma_supported(dev, mask)) |
598 | return -EIO; | |
648babb7 TL |
599 | |
600 | dma_check_mask(dev, mask); | |
601 | ||
e1c7e324 CH |
602 | *dev->dma_mask = mask; |
603 | return 0; | |
604 | } | |
1b0fac45 | 605 | #endif |
1da177e4 | 606 | |
589fc9a6 FT |
607 | static inline u64 dma_get_mask(struct device *dev) |
608 | { | |
07a2c01a | 609 | if (dev && dev->dma_mask && *dev->dma_mask) |
589fc9a6 | 610 | return *dev->dma_mask; |
284901a9 | 611 | return DMA_BIT_MASK(32); |
589fc9a6 FT |
612 | } |
613 | ||
58af4a24 | 614 | #ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK |
710224fa FT |
615 | int dma_set_coherent_mask(struct device *dev, u64 mask); |
616 | #else | |
6a1961f4 FT |
617 | static inline int dma_set_coherent_mask(struct device *dev, u64 mask) |
618 | { | |
619 | if (!dma_supported(dev, mask)) | |
620 | return -EIO; | |
648babb7 TL |
621 | |
622 | dma_check_mask(dev, mask); | |
623 | ||
6a1961f4 FT |
624 | dev->coherent_dma_mask = mask; |
625 | return 0; | |
626 | } | |
710224fa | 627 | #endif |
6a1961f4 | 628 | |
4aa806b7 RK |
629 | /* |
630 | * Set both the DMA mask and the coherent DMA mask to the same thing. | |
631 | * Note that we don't check the return value from dma_set_coherent_mask() | |
632 | * as the DMA API guarantees that the coherent DMA mask can be set to | |
633 | * the same or smaller than the streaming DMA mask. | |
634 | */ | |
635 | static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask) | |
636 | { | |
637 | int rc = dma_set_mask(dev, mask); | |
638 | if (rc == 0) | |
639 | dma_set_coherent_mask(dev, mask); | |
640 | return rc; | |
641 | } | |
642 | ||
fa6a8d6d RK |
643 | /* |
644 | * Similar to the above, except it deals with the case where the device | |
645 | * does not have dev->dma_mask appropriately setup. | |
646 | */ | |
647 | static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask) | |
648 | { | |
649 | dev->dma_mask = &dev->coherent_dma_mask; | |
650 | return dma_set_mask_and_coherent(dev, mask); | |
651 | } | |
652 | ||
1da177e4 LT |
653 | extern u64 dma_get_required_mask(struct device *dev); |
654 | ||
a3a60f81 | 655 | #ifndef arch_setup_dma_ops |
97890ba9 | 656 | static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, |
53c92d79 | 657 | u64 size, const struct iommu_ops *iommu, |
97890ba9 WD |
658 | bool coherent) { } |
659 | #endif | |
660 | ||
661 | #ifndef arch_teardown_dma_ops | |
662 | static inline void arch_teardown_dma_ops(struct device *dev) { } | |
591c1ee4 SS |
663 | #endif |
664 | ||
6b7b6510 FT |
665 | static inline unsigned int dma_get_max_seg_size(struct device *dev) |
666 | { | |
002edb6f RM |
667 | if (dev->dma_parms && dev->dma_parms->max_segment_size) |
668 | return dev->dma_parms->max_segment_size; | |
669 | return SZ_64K; | |
6b7b6510 FT |
670 | } |
671 | ||
672 | static inline unsigned int dma_set_max_seg_size(struct device *dev, | |
673 | unsigned int size) | |
674 | { | |
675 | if (dev->dma_parms) { | |
676 | dev->dma_parms->max_segment_size = size; | |
677 | return 0; | |
002edb6f RM |
678 | } |
679 | return -EIO; | |
6b7b6510 FT |
680 | } |
681 | ||
d22a6966 FT |
682 | static inline unsigned long dma_get_seg_boundary(struct device *dev) |
683 | { | |
002edb6f RM |
684 | if (dev->dma_parms && dev->dma_parms->segment_boundary_mask) |
685 | return dev->dma_parms->segment_boundary_mask; | |
686 | return DMA_BIT_MASK(32); | |
d22a6966 FT |
687 | } |
688 | ||
689 | static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) | |
690 | { | |
691 | if (dev->dma_parms) { | |
692 | dev->dma_parms->segment_boundary_mask = mask; | |
693 | return 0; | |
002edb6f RM |
694 | } |
695 | return -EIO; | |
d22a6966 FT |
696 | } |
697 | ||
00c8f162 SS |
698 | #ifndef dma_max_pfn |
699 | static inline unsigned long dma_max_pfn(struct device *dev) | |
700 | { | |
701 | return *dev->dma_mask >> PAGE_SHIFT; | |
702 | } | |
703 | #endif | |
704 | ||
842fa69f AM |
705 | static inline void *dma_zalloc_coherent(struct device *dev, size_t size, |
706 | dma_addr_t *dma_handle, gfp_t flag) | |
707 | { | |
ede23fa8 JP |
708 | void *ret = dma_alloc_coherent(dev, size, dma_handle, |
709 | flag | __GFP_ZERO); | |
842fa69f AM |
710 | return ret; |
711 | } | |
712 | ||
e259f191 | 713 | #ifdef CONFIG_HAS_DMA |
4565f017 FT |
714 | static inline int dma_get_cache_alignment(void) |
715 | { | |
716 | #ifdef ARCH_DMA_MINALIGN | |
717 | return ARCH_DMA_MINALIGN; | |
718 | #endif | |
719 | return 1; | |
720 | } | |
e259f191 | 721 | #endif |
4565f017 | 722 | |
1da177e4 | 723 | /* flags for the coherent memory api */ |
2436bdcd | 724 | #define DMA_MEMORY_EXCLUSIVE 0x01 |
1da177e4 | 725 | |
20d666e4 CH |
726 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
727 | int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, | |
728 | dma_addr_t device_addr, size_t size, int flags); | |
729 | void dma_release_declared_memory(struct device *dev); | |
730 | void *dma_mark_declared_memory_occupied(struct device *dev, | |
731 | dma_addr_t device_addr, size_t size); | |
732 | #else | |
1da177e4 | 733 | static inline int |
88a984ba | 734 | dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, |
1da177e4 LT |
735 | dma_addr_t device_addr, size_t size, int flags) |
736 | { | |
2436bdcd | 737 | return -ENOSYS; |
1da177e4 LT |
738 | } |
739 | ||
740 | static inline void | |
741 | dma_release_declared_memory(struct device *dev) | |
742 | { | |
743 | } | |
744 | ||
745 | static inline void * | |
746 | dma_mark_declared_memory_occupied(struct device *dev, | |
747 | dma_addr_t device_addr, size_t size) | |
748 | { | |
749 | return ERR_PTR(-EBUSY); | |
750 | } | |
20d666e4 | 751 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 752 | |
09515ef5 S |
753 | #ifdef CONFIG_HAS_DMA |
754 | int dma_configure(struct device *dev); | |
755 | void dma_deconfigure(struct device *dev); | |
756 | #else | |
757 | static inline int dma_configure(struct device *dev) | |
758 | { | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static inline void dma_deconfigure(struct device *dev) {} | |
763 | #endif | |
764 | ||
9ac7849e TH |
765 | /* |
766 | * Managed DMA API | |
767 | */ | |
768 | extern void *dmam_alloc_coherent(struct device *dev, size_t size, | |
769 | dma_addr_t *dma_handle, gfp_t gfp); | |
770 | extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, | |
771 | dma_addr_t dma_handle); | |
63d36c95 CH |
772 | extern void *dmam_alloc_attrs(struct device *dev, size_t size, |
773 | dma_addr_t *dma_handle, gfp_t gfp, | |
774 | unsigned long attrs); | |
20d666e4 | 775 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
88a984ba BH |
776 | extern int dmam_declare_coherent_memory(struct device *dev, |
777 | phys_addr_t phys_addr, | |
9ac7849e TH |
778 | dma_addr_t device_addr, size_t size, |
779 | int flags); | |
780 | extern void dmam_release_declared_memory(struct device *dev); | |
20d666e4 | 781 | #else /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
9ac7849e | 782 | static inline int dmam_declare_coherent_memory(struct device *dev, |
88a984ba | 783 | phys_addr_t phys_addr, dma_addr_t device_addr, |
9ac7849e TH |
784 | size_t size, gfp_t gfp) |
785 | { | |
786 | return 0; | |
787 | } | |
1da177e4 | 788 | |
9ac7849e TH |
789 | static inline void dmam_release_declared_memory(struct device *dev) |
790 | { | |
791 | } | |
20d666e4 | 792 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 793 | |
f6e45661 LR |
794 | static inline void *dma_alloc_wc(struct device *dev, size_t size, |
795 | dma_addr_t *dma_addr, gfp_t gfp) | |
b4bbb107 | 796 | { |
00085f1e KK |
797 | return dma_alloc_attrs(dev, size, dma_addr, gfp, |
798 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 799 | } |
f6e45661 LR |
800 | #ifndef dma_alloc_writecombine |
801 | #define dma_alloc_writecombine dma_alloc_wc | |
802 | #endif | |
b4bbb107 | 803 | |
f6e45661 LR |
804 | static inline void dma_free_wc(struct device *dev, size_t size, |
805 | void *cpu_addr, dma_addr_t dma_addr) | |
b4bbb107 | 806 | { |
00085f1e KK |
807 | return dma_free_attrs(dev, size, cpu_addr, dma_addr, |
808 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 809 | } |
f6e45661 LR |
810 | #ifndef dma_free_writecombine |
811 | #define dma_free_writecombine dma_free_wc | |
812 | #endif | |
b4bbb107 | 813 | |
f6e45661 LR |
814 | static inline int dma_mmap_wc(struct device *dev, |
815 | struct vm_area_struct *vma, | |
816 | void *cpu_addr, dma_addr_t dma_addr, | |
817 | size_t size) | |
b4bbb107 | 818 | { |
00085f1e KK |
819 | return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, |
820 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 821 | } |
f6e45661 LR |
822 | #ifndef dma_mmap_writecombine |
823 | #define dma_mmap_writecombine dma_mmap_wc | |
824 | #endif | |
74bc7cee | 825 | |
2481366a | 826 | #if defined(CONFIG_NEED_DMA_MAP_STATE) || defined(CONFIG_DMA_API_DEBUG) |
0acedc12 FT |
827 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME |
828 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME | |
829 | #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | |
830 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | |
831 | #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | |
832 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | |
833 | #else | |
834 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) | |
835 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) | |
836 | #define dma_unmap_addr(PTR, ADDR_NAME) (0) | |
837 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
838 | #define dma_unmap_len(PTR, LEN_NAME) (0) | |
839 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
840 | #endif | |
841 | ||
9ac7849e | 842 | #endif |