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96532bab RD |
1 | #ifndef _LINUX_DMA_MAPPING_H |
2 | #define _LINUX_DMA_MAPPING_H | |
1da177e4 | 3 | |
002edb6f | 4 | #include <linux/sizes.h> |
842fa69f | 5 | #include <linux/string.h> |
1da177e4 LT |
6 | #include <linux/device.h> |
7 | #include <linux/err.h> | |
e1c7e324 | 8 | #include <linux/dma-debug.h> |
b7f080cf | 9 | #include <linux/dma-direction.h> |
f0402a26 | 10 | #include <linux/scatterlist.h> |
e1c7e324 CH |
11 | #include <linux/kmemcheck.h> |
12 | #include <linux/bug.h> | |
1da177e4 | 13 | |
00085f1e KK |
14 | /** |
15 | * List of possible attributes associated with a DMA mapping. The semantics | |
16 | * of each attribute should be defined in Documentation/DMA-attributes.txt. | |
17 | * | |
18 | * DMA_ATTR_WRITE_BARRIER: DMA to a memory region with this attribute | |
19 | * forces all pending DMA writes to complete. | |
20 | */ | |
21 | #define DMA_ATTR_WRITE_BARRIER (1UL << 0) | |
22 | /* | |
23 | * DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping | |
24 | * may be weakly ordered, that is that reads and writes may pass each other. | |
25 | */ | |
26 | #define DMA_ATTR_WEAK_ORDERING (1UL << 1) | |
27 | /* | |
28 | * DMA_ATTR_WRITE_COMBINE: Specifies that writes to the mapping may be | |
29 | * buffered to improve performance. | |
30 | */ | |
31 | #define DMA_ATTR_WRITE_COMBINE (1UL << 2) | |
32 | /* | |
33 | * DMA_ATTR_NON_CONSISTENT: Lets the platform to choose to return either | |
34 | * consistent or non-consistent memory as it sees fit. | |
35 | */ | |
36 | #define DMA_ATTR_NON_CONSISTENT (1UL << 3) | |
37 | /* | |
38 | * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platform to avoid creating a kernel | |
39 | * virtual mapping for the allocated buffer. | |
40 | */ | |
41 | #define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4) | |
42 | /* | |
43 | * DMA_ATTR_SKIP_CPU_SYNC: Allows platform code to skip synchronization of | |
44 | * the CPU cache for the given buffer assuming that it has been already | |
45 | * transferred to 'device' domain. | |
46 | */ | |
47 | #define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5) | |
48 | /* | |
49 | * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguous allocation of the buffer | |
50 | * in physical memory. | |
51 | */ | |
52 | #define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6) | |
53 | /* | |
54 | * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint to the DMA-mapping subsystem | |
55 | * that it's probably not worth the time to try to allocate memory to in a way | |
56 | * that gives better TLB efficiency. | |
57 | */ | |
58 | #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7) | |
a9a62c93 MFO |
59 | /* |
60 | * DMA_ATTR_NO_WARN: This tells the DMA-mapping subsystem to suppress | |
61 | * allocation failure reports (similarly to __GFP_NOWARN). | |
62 | */ | |
63 | #define DMA_ATTR_NO_WARN (1UL << 8) | |
00085f1e | 64 | |
b2fb3664 MH |
65 | /* |
66 | * DMA_ATTR_PRIVILEGED: used to indicate that the buffer is fully | |
67 | * accessible at an elevated privilege level (and ideally inaccessible or | |
68 | * at least read-only at lesser-privileged levels). | |
69 | */ | |
70 | #define DMA_ATTR_PRIVILEGED (1UL << 9) | |
71 | ||
77f2ea2f BH |
72 | /* |
73 | * A dma_addr_t can hold any valid DMA or bus address for the platform. | |
74 | * It can be given to a device to use as a DMA source or target. A CPU cannot | |
75 | * reference a dma_addr_t directly because there may be translation between | |
76 | * its physical address space and the bus address space. | |
77 | */ | |
f0402a26 | 78 | struct dma_map_ops { |
613c4578 MS |
79 | void* (*alloc)(struct device *dev, size_t size, |
80 | dma_addr_t *dma_handle, gfp_t gfp, | |
00085f1e | 81 | unsigned long attrs); |
613c4578 MS |
82 | void (*free)(struct device *dev, size_t size, |
83 | void *vaddr, dma_addr_t dma_handle, | |
00085f1e | 84 | unsigned long attrs); |
9adc5374 | 85 | int (*mmap)(struct device *, struct vm_area_struct *, |
00085f1e KK |
86 | void *, dma_addr_t, size_t, |
87 | unsigned long attrs); | |
9adc5374 | 88 | |
d2b7428e | 89 | int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *, |
00085f1e | 90 | dma_addr_t, size_t, unsigned long attrs); |
d2b7428e | 91 | |
f0402a26 FT |
92 | dma_addr_t (*map_page)(struct device *dev, struct page *page, |
93 | unsigned long offset, size_t size, | |
94 | enum dma_data_direction dir, | |
00085f1e | 95 | unsigned long attrs); |
f0402a26 FT |
96 | void (*unmap_page)(struct device *dev, dma_addr_t dma_handle, |
97 | size_t size, enum dma_data_direction dir, | |
00085f1e | 98 | unsigned long attrs); |
04abab69 RRD |
99 | /* |
100 | * map_sg returns 0 on error and a value > 0 on success. | |
101 | * It should never return a value < 0. | |
102 | */ | |
f0402a26 FT |
103 | int (*map_sg)(struct device *dev, struct scatterlist *sg, |
104 | int nents, enum dma_data_direction dir, | |
00085f1e | 105 | unsigned long attrs); |
f0402a26 FT |
106 | void (*unmap_sg)(struct device *dev, |
107 | struct scatterlist *sg, int nents, | |
108 | enum dma_data_direction dir, | |
00085f1e | 109 | unsigned long attrs); |
ba409b31 NS |
110 | dma_addr_t (*map_resource)(struct device *dev, phys_addr_t phys_addr, |
111 | size_t size, enum dma_data_direction dir, | |
112 | unsigned long attrs); | |
113 | void (*unmap_resource)(struct device *dev, dma_addr_t dma_handle, | |
114 | size_t size, enum dma_data_direction dir, | |
115 | unsigned long attrs); | |
f0402a26 FT |
116 | void (*sync_single_for_cpu)(struct device *dev, |
117 | dma_addr_t dma_handle, size_t size, | |
118 | enum dma_data_direction dir); | |
119 | void (*sync_single_for_device)(struct device *dev, | |
120 | dma_addr_t dma_handle, size_t size, | |
121 | enum dma_data_direction dir); | |
f0402a26 FT |
122 | void (*sync_sg_for_cpu)(struct device *dev, |
123 | struct scatterlist *sg, int nents, | |
124 | enum dma_data_direction dir); | |
125 | void (*sync_sg_for_device)(struct device *dev, | |
126 | struct scatterlist *sg, int nents, | |
127 | enum dma_data_direction dir); | |
128 | int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); | |
129 | int (*dma_supported)(struct device *dev, u64 mask); | |
3a8f7558 MM |
130 | #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK |
131 | u64 (*get_required_mask)(struct device *dev); | |
132 | #endif | |
f0402a26 FT |
133 | int is_phys; |
134 | }; | |
135 | ||
5299709d | 136 | extern const struct dma_map_ops dma_noop_ops; |
551199ac | 137 | extern const struct dma_map_ops dma_virt_ops; |
a8463d4b | 138 | |
8f286c33 | 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
34c65384 | 140 | |
32e8f702 JB |
141 | #define DMA_MASK_NONE 0x0ULL |
142 | ||
d6bd3a39 REB |
143 | static inline int valid_dma_direction(int dma_direction) |
144 | { | |
145 | return ((dma_direction == DMA_BIDIRECTIONAL) || | |
146 | (dma_direction == DMA_TO_DEVICE) || | |
147 | (dma_direction == DMA_FROM_DEVICE)); | |
148 | } | |
149 | ||
32e8f702 JB |
150 | static inline int is_device_dma_capable(struct device *dev) |
151 | { | |
152 | return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE; | |
153 | } | |
154 | ||
20d666e4 CH |
155 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
156 | /* | |
157 | * These three functions are only for dma allocator. | |
158 | * Don't use them in device drivers. | |
159 | */ | |
43fc509c | 160 | int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size, |
20d666e4 | 161 | dma_addr_t *dma_handle, void **ret); |
43fc509c | 162 | int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr); |
20d666e4 | 163 | |
43fc509c | 164 | int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma, |
20d666e4 | 165 | void *cpu_addr, size_t size, int *ret); |
43fc509c VM |
166 | |
167 | void *dma_alloc_from_global_coherent(ssize_t size, dma_addr_t *dma_handle); | |
168 | int dma_release_from_global_coherent(int order, void *vaddr); | |
169 | int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr, | |
170 | size_t size, int *ret); | |
171 | ||
20d666e4 | 172 | #else |
43fc509c VM |
173 | #define dma_alloc_from_dev_coherent(dev, size, handle, ret) (0) |
174 | #define dma_release_from_dev_coherent(dev, order, vaddr) (0) | |
175 | #define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0) | |
176 | ||
177 | static inline void *dma_alloc_from_global_coherent(ssize_t size, | |
178 | dma_addr_t *dma_handle) | |
179 | { | |
180 | return NULL; | |
181 | } | |
182 | ||
183 | static inline int dma_release_from_global_coherent(int order, void *vaddr) | |
184 | { | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma, | |
189 | void *cpu_addr, size_t size, | |
190 | int *ret) | |
191 | { | |
192 | return 0; | |
193 | } | |
20d666e4 CH |
194 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
195 | ||
1b0fac45 | 196 | #ifdef CONFIG_HAS_DMA |
1da177e4 | 197 | #include <asm/dma-mapping.h> |
815dd187 BVA |
198 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) |
199 | { | |
200 | if (dev && dev->dma_ops) | |
201 | return dev->dma_ops; | |
202 | return get_arch_dma_ops(dev ? dev->bus : NULL); | |
203 | } | |
204 | ||
ca6e8e10 BVA |
205 | static inline void set_dma_ops(struct device *dev, |
206 | const struct dma_map_ops *dma_ops) | |
207 | { | |
208 | dev->dma_ops = dma_ops; | |
209 | } | |
1b0fac45 | 210 | #else |
e1c7e324 CH |
211 | /* |
212 | * Define the dma api to allow compilation but not linking of | |
213 | * dma dependent code. Code that depends on the dma-mapping | |
214 | * API needs to set 'depends on HAS_DMA' in its Kconfig | |
215 | */ | |
5299709d BVA |
216 | extern const struct dma_map_ops bad_dma_ops; |
217 | static inline const struct dma_map_ops *get_dma_ops(struct device *dev) | |
e1c7e324 CH |
218 | { |
219 | return &bad_dma_ops; | |
220 | } | |
221 | #endif | |
222 | ||
223 | static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, | |
224 | size_t size, | |
225 | enum dma_data_direction dir, | |
00085f1e | 226 | unsigned long attrs) |
e1c7e324 | 227 | { |
5299709d | 228 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
229 | dma_addr_t addr; |
230 | ||
231 | kmemcheck_mark_initialized(ptr, size); | |
232 | BUG_ON(!valid_dma_direction(dir)); | |
233 | addr = ops->map_page(dev, virt_to_page(ptr), | |
8e99469a | 234 | offset_in_page(ptr), size, |
e1c7e324 CH |
235 | dir, attrs); |
236 | debug_dma_map_page(dev, virt_to_page(ptr), | |
8e99469a | 237 | offset_in_page(ptr), size, |
e1c7e324 CH |
238 | dir, addr, true); |
239 | return addr; | |
240 | } | |
241 | ||
242 | static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, | |
243 | size_t size, | |
244 | enum dma_data_direction dir, | |
00085f1e | 245 | unsigned long attrs) |
e1c7e324 | 246 | { |
5299709d | 247 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
248 | |
249 | BUG_ON(!valid_dma_direction(dir)); | |
250 | if (ops->unmap_page) | |
251 | ops->unmap_page(dev, addr, size, dir, attrs); | |
252 | debug_dma_unmap_page(dev, addr, size, dir, true); | |
253 | } | |
254 | ||
255 | /* | |
256 | * dma_maps_sg_attrs returns 0 on error and > 0 on success. | |
257 | * It should never return a value < 0. | |
258 | */ | |
259 | static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, | |
260 | int nents, enum dma_data_direction dir, | |
00085f1e | 261 | unsigned long attrs) |
e1c7e324 | 262 | { |
5299709d | 263 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
264 | int i, ents; |
265 | struct scatterlist *s; | |
266 | ||
267 | for_each_sg(sg, s, nents, i) | |
268 | kmemcheck_mark_initialized(sg_virt(s), s->length); | |
269 | BUG_ON(!valid_dma_direction(dir)); | |
270 | ents = ops->map_sg(dev, sg, nents, dir, attrs); | |
271 | BUG_ON(ents < 0); | |
272 | debug_dma_map_sg(dev, sg, nents, ents, dir); | |
273 | ||
274 | return ents; | |
275 | } | |
276 | ||
277 | static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, | |
278 | int nents, enum dma_data_direction dir, | |
00085f1e | 279 | unsigned long attrs) |
e1c7e324 | 280 | { |
5299709d | 281 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
282 | |
283 | BUG_ON(!valid_dma_direction(dir)); | |
284 | debug_dma_unmap_sg(dev, sg, nents, dir); | |
285 | if (ops->unmap_sg) | |
286 | ops->unmap_sg(dev, sg, nents, dir, attrs); | |
287 | } | |
288 | ||
0495c3d3 AD |
289 | static inline dma_addr_t dma_map_page_attrs(struct device *dev, |
290 | struct page *page, | |
291 | size_t offset, size_t size, | |
292 | enum dma_data_direction dir, | |
293 | unsigned long attrs) | |
e1c7e324 | 294 | { |
5299709d | 295 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
296 | dma_addr_t addr; |
297 | ||
298 | kmemcheck_mark_initialized(page_address(page) + offset, size); | |
299 | BUG_ON(!valid_dma_direction(dir)); | |
0495c3d3 | 300 | addr = ops->map_page(dev, page, offset, size, dir, attrs); |
e1c7e324 CH |
301 | debug_dma_map_page(dev, page, offset, size, dir, addr, false); |
302 | ||
303 | return addr; | |
304 | } | |
305 | ||
0495c3d3 AD |
306 | static inline void dma_unmap_page_attrs(struct device *dev, |
307 | dma_addr_t addr, size_t size, | |
308 | enum dma_data_direction dir, | |
309 | unsigned long attrs) | |
e1c7e324 | 310 | { |
5299709d | 311 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
312 | |
313 | BUG_ON(!valid_dma_direction(dir)); | |
314 | if (ops->unmap_page) | |
0495c3d3 | 315 | ops->unmap_page(dev, addr, size, dir, attrs); |
e1c7e324 CH |
316 | debug_dma_unmap_page(dev, addr, size, dir, false); |
317 | } | |
318 | ||
6f3d8796 NS |
319 | static inline dma_addr_t dma_map_resource(struct device *dev, |
320 | phys_addr_t phys_addr, | |
321 | size_t size, | |
322 | enum dma_data_direction dir, | |
323 | unsigned long attrs) | |
324 | { | |
5299709d | 325 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
326 | dma_addr_t addr; |
327 | ||
328 | BUG_ON(!valid_dma_direction(dir)); | |
329 | ||
330 | /* Don't allow RAM to be mapped */ | |
3757dc48 | 331 | BUG_ON(pfn_valid(PHYS_PFN(phys_addr))); |
6f3d8796 NS |
332 | |
333 | addr = phys_addr; | |
334 | if (ops->map_resource) | |
335 | addr = ops->map_resource(dev, phys_addr, size, dir, attrs); | |
336 | ||
337 | debug_dma_map_resource(dev, phys_addr, size, dir, addr); | |
338 | ||
339 | return addr; | |
340 | } | |
341 | ||
342 | static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr, | |
343 | size_t size, enum dma_data_direction dir, | |
344 | unsigned long attrs) | |
345 | { | |
5299709d | 346 | const struct dma_map_ops *ops = get_dma_ops(dev); |
6f3d8796 NS |
347 | |
348 | BUG_ON(!valid_dma_direction(dir)); | |
349 | if (ops->unmap_resource) | |
350 | ops->unmap_resource(dev, addr, size, dir, attrs); | |
351 | debug_dma_unmap_resource(dev, addr, size, dir); | |
352 | } | |
353 | ||
e1c7e324 CH |
354 | static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, |
355 | size_t size, | |
356 | enum dma_data_direction dir) | |
357 | { | |
5299709d | 358 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
359 | |
360 | BUG_ON(!valid_dma_direction(dir)); | |
361 | if (ops->sync_single_for_cpu) | |
362 | ops->sync_single_for_cpu(dev, addr, size, dir); | |
363 | debug_dma_sync_single_for_cpu(dev, addr, size, dir); | |
364 | } | |
365 | ||
366 | static inline void dma_sync_single_for_device(struct device *dev, | |
367 | dma_addr_t addr, size_t size, | |
368 | enum dma_data_direction dir) | |
369 | { | |
5299709d | 370 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
371 | |
372 | BUG_ON(!valid_dma_direction(dir)); | |
373 | if (ops->sync_single_for_device) | |
374 | ops->sync_single_for_device(dev, addr, size, dir); | |
375 | debug_dma_sync_single_for_device(dev, addr, size, dir); | |
376 | } | |
377 | ||
378 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | |
379 | dma_addr_t addr, | |
380 | unsigned long offset, | |
381 | size_t size, | |
382 | enum dma_data_direction dir) | |
383 | { | |
384 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
385 | ||
386 | BUG_ON(!valid_dma_direction(dir)); | |
387 | if (ops->sync_single_for_cpu) | |
388 | ops->sync_single_for_cpu(dev, addr + offset, size, dir); | |
389 | debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); | |
390 | } | |
391 | ||
392 | static inline void dma_sync_single_range_for_device(struct device *dev, | |
393 | dma_addr_t addr, | |
394 | unsigned long offset, | |
395 | size_t size, | |
396 | enum dma_data_direction dir) | |
397 | { | |
398 | const struct dma_map_ops *ops = get_dma_ops(dev); | |
399 | ||
400 | BUG_ON(!valid_dma_direction(dir)); | |
401 | if (ops->sync_single_for_device) | |
402 | ops->sync_single_for_device(dev, addr + offset, size, dir); | |
403 | debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); | |
404 | } | |
405 | ||
406 | static inline void | |
407 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
408 | int nelems, enum dma_data_direction dir) | |
409 | { | |
5299709d | 410 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
411 | |
412 | BUG_ON(!valid_dma_direction(dir)); | |
413 | if (ops->sync_sg_for_cpu) | |
414 | ops->sync_sg_for_cpu(dev, sg, nelems, dir); | |
415 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); | |
416 | } | |
417 | ||
418 | static inline void | |
419 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
420 | int nelems, enum dma_data_direction dir) | |
421 | { | |
5299709d | 422 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
423 | |
424 | BUG_ON(!valid_dma_direction(dir)); | |
425 | if (ops->sync_sg_for_device) | |
426 | ops->sync_sg_for_device(dev, sg, nelems, dir); | |
427 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); | |
428 | ||
429 | } | |
430 | ||
00085f1e KK |
431 | #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0) |
432 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | |
433 | #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, 0) | |
434 | #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, 0) | |
0495c3d3 AD |
435 | #define dma_map_page(d, p, o, s, r) dma_map_page_attrs(d, p, o, s, r, 0) |
436 | #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0) | |
e1c7e324 CH |
437 | |
438 | extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, | |
439 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
440 | ||
441 | void *dma_common_contiguous_remap(struct page *page, size_t size, | |
442 | unsigned long vm_flags, | |
443 | pgprot_t prot, const void *caller); | |
444 | ||
445 | void *dma_common_pages_remap(struct page **pages, size_t size, | |
446 | unsigned long vm_flags, pgprot_t prot, | |
447 | const void *caller); | |
448 | void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags); | |
449 | ||
450 | /** | |
451 | * dma_mmap_attrs - map a coherent DMA allocation into user space | |
452 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
453 | * @vma: vm_area_struct describing requested user mapping | |
454 | * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs | |
455 | * @handle: device-view address returned from dma_alloc_attrs | |
456 | * @size: size of memory originally requested in dma_alloc_attrs | |
457 | * @attrs: attributes of mapping properties requested in dma_alloc_attrs | |
458 | * | |
459 | * Map a coherent DMA buffer previously allocated by dma_alloc_attrs | |
460 | * into user space. The coherent DMA buffer must not be freed by the | |
461 | * driver until the user space mapping has been released. | |
462 | */ | |
463 | static inline int | |
464 | dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 465 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
e1c7e324 | 466 | { |
5299709d | 467 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
468 | BUG_ON(!ops); |
469 | if (ops->mmap) | |
470 | return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
471 | return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); | |
472 | } | |
473 | ||
00085f1e | 474 | #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0) |
e1c7e324 CH |
475 | |
476 | int | |
477 | dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, | |
478 | void *cpu_addr, dma_addr_t dma_addr, size_t size); | |
479 | ||
480 | static inline int | |
481 | dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, | |
00085f1e KK |
482 | dma_addr_t dma_addr, size_t size, |
483 | unsigned long attrs) | |
e1c7e324 | 484 | { |
5299709d | 485 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
486 | BUG_ON(!ops); |
487 | if (ops->get_sgtable) | |
488 | return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, | |
489 | attrs); | |
490 | return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); | |
491 | } | |
492 | ||
00085f1e | 493 | #define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0) |
e1c7e324 CH |
494 | |
495 | #ifndef arch_dma_alloc_attrs | |
496 | #define arch_dma_alloc_attrs(dev, flag) (true) | |
497 | #endif | |
498 | ||
499 | static inline void *dma_alloc_attrs(struct device *dev, size_t size, | |
500 | dma_addr_t *dma_handle, gfp_t flag, | |
00085f1e | 501 | unsigned long attrs) |
e1c7e324 | 502 | { |
5299709d | 503 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
504 | void *cpu_addr; |
505 | ||
506 | BUG_ON(!ops); | |
507 | ||
43fc509c | 508 | if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) |
e1c7e324 CH |
509 | return cpu_addr; |
510 | ||
511 | if (!arch_dma_alloc_attrs(&dev, &flag)) | |
512 | return NULL; | |
513 | if (!ops->alloc) | |
514 | return NULL; | |
515 | ||
516 | cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); | |
517 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
518 | return cpu_addr; | |
519 | } | |
520 | ||
521 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
522 | void *cpu_addr, dma_addr_t dma_handle, | |
00085f1e | 523 | unsigned long attrs) |
e1c7e324 | 524 | { |
5299709d | 525 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
526 | |
527 | BUG_ON(!ops); | |
528 | WARN_ON(irqs_disabled()); | |
529 | ||
43fc509c | 530 | if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr)) |
e1c7e324 CH |
531 | return; |
532 | ||
d6b7eaeb | 533 | if (!ops->free || !cpu_addr) |
e1c7e324 CH |
534 | return; |
535 | ||
536 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
537 | ops->free(dev, size, cpu_addr, dma_handle, attrs); | |
538 | } | |
539 | ||
540 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
541 | dma_addr_t *dma_handle, gfp_t flag) | |
542 | { | |
00085f1e | 543 | return dma_alloc_attrs(dev, size, dma_handle, flag, 0); |
e1c7e324 CH |
544 | } |
545 | ||
546 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
547 | void *cpu_addr, dma_addr_t dma_handle) | |
548 | { | |
00085f1e | 549 | return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0); |
e1c7e324 CH |
550 | } |
551 | ||
552 | static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, | |
553 | dma_addr_t *dma_handle, gfp_t gfp) | |
554 | { | |
00085f1e KK |
555 | return dma_alloc_attrs(dev, size, dma_handle, gfp, |
556 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
557 | } |
558 | ||
559 | static inline void dma_free_noncoherent(struct device *dev, size_t size, | |
560 | void *cpu_addr, dma_addr_t dma_handle) | |
561 | { | |
00085f1e KK |
562 | dma_free_attrs(dev, size, cpu_addr, dma_handle, |
563 | DMA_ATTR_NON_CONSISTENT); | |
e1c7e324 CH |
564 | } |
565 | ||
566 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
567 | { | |
568 | debug_dma_mapping_error(dev, dma_addr); | |
569 | ||
570 | if (get_dma_ops(dev)->mapping_error) | |
571 | return get_dma_ops(dev)->mapping_error(dev, dma_addr); | |
e1c7e324 | 572 | return 0; |
e1c7e324 CH |
573 | } |
574 | ||
e1c7e324 CH |
575 | static inline int dma_supported(struct device *dev, u64 mask) |
576 | { | |
5299709d | 577 | const struct dma_map_ops *ops = get_dma_ops(dev); |
e1c7e324 CH |
578 | |
579 | if (!ops) | |
580 | return 0; | |
581 | if (!ops->dma_supported) | |
582 | return 1; | |
583 | return ops->dma_supported(dev, mask); | |
584 | } | |
e1c7e324 CH |
585 | |
586 | #ifndef HAVE_ARCH_DMA_SET_MASK | |
587 | static inline int dma_set_mask(struct device *dev, u64 mask) | |
588 | { | |
e1c7e324 CH |
589 | if (!dev->dma_mask || !dma_supported(dev, mask)) |
590 | return -EIO; | |
591 | *dev->dma_mask = mask; | |
592 | return 0; | |
593 | } | |
1b0fac45 | 594 | #endif |
1da177e4 | 595 | |
589fc9a6 FT |
596 | static inline u64 dma_get_mask(struct device *dev) |
597 | { | |
07a2c01a | 598 | if (dev && dev->dma_mask && *dev->dma_mask) |
589fc9a6 | 599 | return *dev->dma_mask; |
284901a9 | 600 | return DMA_BIT_MASK(32); |
589fc9a6 FT |
601 | } |
602 | ||
58af4a24 | 603 | #ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK |
710224fa FT |
604 | int dma_set_coherent_mask(struct device *dev, u64 mask); |
605 | #else | |
6a1961f4 FT |
606 | static inline int dma_set_coherent_mask(struct device *dev, u64 mask) |
607 | { | |
608 | if (!dma_supported(dev, mask)) | |
609 | return -EIO; | |
610 | dev->coherent_dma_mask = mask; | |
611 | return 0; | |
612 | } | |
710224fa | 613 | #endif |
6a1961f4 | 614 | |
4aa806b7 RK |
615 | /* |
616 | * Set both the DMA mask and the coherent DMA mask to the same thing. | |
617 | * Note that we don't check the return value from dma_set_coherent_mask() | |
618 | * as the DMA API guarantees that the coherent DMA mask can be set to | |
619 | * the same or smaller than the streaming DMA mask. | |
620 | */ | |
621 | static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask) | |
622 | { | |
623 | int rc = dma_set_mask(dev, mask); | |
624 | if (rc == 0) | |
625 | dma_set_coherent_mask(dev, mask); | |
626 | return rc; | |
627 | } | |
628 | ||
fa6a8d6d RK |
629 | /* |
630 | * Similar to the above, except it deals with the case where the device | |
631 | * does not have dev->dma_mask appropriately setup. | |
632 | */ | |
633 | static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask) | |
634 | { | |
635 | dev->dma_mask = &dev->coherent_dma_mask; | |
636 | return dma_set_mask_and_coherent(dev, mask); | |
637 | } | |
638 | ||
1da177e4 LT |
639 | extern u64 dma_get_required_mask(struct device *dev); |
640 | ||
a3a60f81 | 641 | #ifndef arch_setup_dma_ops |
97890ba9 | 642 | static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, |
53c92d79 | 643 | u64 size, const struct iommu_ops *iommu, |
97890ba9 WD |
644 | bool coherent) { } |
645 | #endif | |
646 | ||
647 | #ifndef arch_teardown_dma_ops | |
648 | static inline void arch_teardown_dma_ops(struct device *dev) { } | |
591c1ee4 SS |
649 | #endif |
650 | ||
6b7b6510 FT |
651 | static inline unsigned int dma_get_max_seg_size(struct device *dev) |
652 | { | |
002edb6f RM |
653 | if (dev->dma_parms && dev->dma_parms->max_segment_size) |
654 | return dev->dma_parms->max_segment_size; | |
655 | return SZ_64K; | |
6b7b6510 FT |
656 | } |
657 | ||
658 | static inline unsigned int dma_set_max_seg_size(struct device *dev, | |
659 | unsigned int size) | |
660 | { | |
661 | if (dev->dma_parms) { | |
662 | dev->dma_parms->max_segment_size = size; | |
663 | return 0; | |
002edb6f RM |
664 | } |
665 | return -EIO; | |
6b7b6510 FT |
666 | } |
667 | ||
d22a6966 FT |
668 | static inline unsigned long dma_get_seg_boundary(struct device *dev) |
669 | { | |
002edb6f RM |
670 | if (dev->dma_parms && dev->dma_parms->segment_boundary_mask) |
671 | return dev->dma_parms->segment_boundary_mask; | |
672 | return DMA_BIT_MASK(32); | |
d22a6966 FT |
673 | } |
674 | ||
675 | static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) | |
676 | { | |
677 | if (dev->dma_parms) { | |
678 | dev->dma_parms->segment_boundary_mask = mask; | |
679 | return 0; | |
002edb6f RM |
680 | } |
681 | return -EIO; | |
d22a6966 FT |
682 | } |
683 | ||
00c8f162 SS |
684 | #ifndef dma_max_pfn |
685 | static inline unsigned long dma_max_pfn(struct device *dev) | |
686 | { | |
687 | return *dev->dma_mask >> PAGE_SHIFT; | |
688 | } | |
689 | #endif | |
690 | ||
842fa69f AM |
691 | static inline void *dma_zalloc_coherent(struct device *dev, size_t size, |
692 | dma_addr_t *dma_handle, gfp_t flag) | |
693 | { | |
ede23fa8 JP |
694 | void *ret = dma_alloc_coherent(dev, size, dma_handle, |
695 | flag | __GFP_ZERO); | |
842fa69f AM |
696 | return ret; |
697 | } | |
698 | ||
e259f191 | 699 | #ifdef CONFIG_HAS_DMA |
4565f017 FT |
700 | static inline int dma_get_cache_alignment(void) |
701 | { | |
702 | #ifdef ARCH_DMA_MINALIGN | |
703 | return ARCH_DMA_MINALIGN; | |
704 | #endif | |
705 | return 1; | |
706 | } | |
e259f191 | 707 | #endif |
4565f017 | 708 | |
1da177e4 LT |
709 | /* flags for the coherent memory api */ |
710 | #define DMA_MEMORY_MAP 0x01 | |
711 | #define DMA_MEMORY_IO 0x02 | |
712 | #define DMA_MEMORY_INCLUDES_CHILDREN 0x04 | |
713 | #define DMA_MEMORY_EXCLUSIVE 0x08 | |
714 | ||
20d666e4 CH |
715 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
716 | int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, | |
717 | dma_addr_t device_addr, size_t size, int flags); | |
718 | void dma_release_declared_memory(struct device *dev); | |
719 | void *dma_mark_declared_memory_occupied(struct device *dev, | |
720 | dma_addr_t device_addr, size_t size); | |
721 | #else | |
1da177e4 | 722 | static inline int |
88a984ba | 723 | dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, |
1da177e4 LT |
724 | dma_addr_t device_addr, size_t size, int flags) |
725 | { | |
726 | return 0; | |
727 | } | |
728 | ||
729 | static inline void | |
730 | dma_release_declared_memory(struct device *dev) | |
731 | { | |
732 | } | |
733 | ||
734 | static inline void * | |
735 | dma_mark_declared_memory_occupied(struct device *dev, | |
736 | dma_addr_t device_addr, size_t size) | |
737 | { | |
738 | return ERR_PTR(-EBUSY); | |
739 | } | |
20d666e4 | 740 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 741 | |
09515ef5 S |
742 | #ifdef CONFIG_HAS_DMA |
743 | int dma_configure(struct device *dev); | |
744 | void dma_deconfigure(struct device *dev); | |
745 | #else | |
746 | static inline int dma_configure(struct device *dev) | |
747 | { | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static inline void dma_deconfigure(struct device *dev) {} | |
752 | #endif | |
753 | ||
9ac7849e TH |
754 | /* |
755 | * Managed DMA API | |
756 | */ | |
757 | extern void *dmam_alloc_coherent(struct device *dev, size_t size, | |
758 | dma_addr_t *dma_handle, gfp_t gfp); | |
759 | extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, | |
760 | dma_addr_t dma_handle); | |
63d36c95 CH |
761 | extern void *dmam_alloc_attrs(struct device *dev, size_t size, |
762 | dma_addr_t *dma_handle, gfp_t gfp, | |
763 | unsigned long attrs); | |
20d666e4 | 764 | #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT |
88a984ba BH |
765 | extern int dmam_declare_coherent_memory(struct device *dev, |
766 | phys_addr_t phys_addr, | |
9ac7849e TH |
767 | dma_addr_t device_addr, size_t size, |
768 | int flags); | |
769 | extern void dmam_release_declared_memory(struct device *dev); | |
20d666e4 | 770 | #else /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
9ac7849e | 771 | static inline int dmam_declare_coherent_memory(struct device *dev, |
88a984ba | 772 | phys_addr_t phys_addr, dma_addr_t device_addr, |
9ac7849e TH |
773 | size_t size, gfp_t gfp) |
774 | { | |
775 | return 0; | |
776 | } | |
1da177e4 | 777 | |
9ac7849e TH |
778 | static inline void dmam_release_declared_memory(struct device *dev) |
779 | { | |
780 | } | |
20d666e4 | 781 | #endif /* CONFIG_HAVE_GENERIC_DMA_COHERENT */ |
1da177e4 | 782 | |
f6e45661 LR |
783 | static inline void *dma_alloc_wc(struct device *dev, size_t size, |
784 | dma_addr_t *dma_addr, gfp_t gfp) | |
b4bbb107 | 785 | { |
00085f1e KK |
786 | return dma_alloc_attrs(dev, size, dma_addr, gfp, |
787 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 788 | } |
f6e45661 LR |
789 | #ifndef dma_alloc_writecombine |
790 | #define dma_alloc_writecombine dma_alloc_wc | |
791 | #endif | |
b4bbb107 | 792 | |
f6e45661 LR |
793 | static inline void dma_free_wc(struct device *dev, size_t size, |
794 | void *cpu_addr, dma_addr_t dma_addr) | |
b4bbb107 | 795 | { |
00085f1e KK |
796 | return dma_free_attrs(dev, size, cpu_addr, dma_addr, |
797 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 798 | } |
f6e45661 LR |
799 | #ifndef dma_free_writecombine |
800 | #define dma_free_writecombine dma_free_wc | |
801 | #endif | |
b4bbb107 | 802 | |
f6e45661 LR |
803 | static inline int dma_mmap_wc(struct device *dev, |
804 | struct vm_area_struct *vma, | |
805 | void *cpu_addr, dma_addr_t dma_addr, | |
806 | size_t size) | |
b4bbb107 | 807 | { |
00085f1e KK |
808 | return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, |
809 | DMA_ATTR_WRITE_COMBINE); | |
b4bbb107 | 810 | } |
f6e45661 LR |
811 | #ifndef dma_mmap_writecombine |
812 | #define dma_mmap_writecombine dma_mmap_wc | |
813 | #endif | |
74bc7cee | 814 | |
2481366a | 815 | #if defined(CONFIG_NEED_DMA_MAP_STATE) || defined(CONFIG_DMA_API_DEBUG) |
0acedc12 FT |
816 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME |
817 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME | |
818 | #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | |
819 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | |
820 | #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | |
821 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | |
822 | #else | |
823 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) | |
824 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) | |
825 | #define dma_unmap_addr(PTR, ADDR_NAME) (0) | |
826 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
827 | #define dma_unmap_len(PTR, LEN_NAME) (0) | |
828 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
829 | #endif | |
830 | ||
9ac7849e | 831 | #endif |