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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2#ifndef _DMA_REMAPPING_H
3#define _DMA_REMAPPING_H
4
5/*
5b6985ce 6 * VT-d hardware uses 4KiB page size regardless of host page size.
e61d98d8 7 */
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8#define VTD_PAGE_SHIFT (12)
9#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
10#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
11#define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
e61d98d8 12
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13#define VTD_STRIDE_SHIFT (9)
14#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
15
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16#define DMA_PTE_READ (1)
17#define DMA_PTE_WRITE (2)
6dd9a7c7 18#define DMA_PTE_LARGE_PAGE (1 << 7)
9cf06697 19#define DMA_PTE_SNP (1 << 11)
e61d98d8 20
4ed0d3e6 21#define CONTEXT_TT_MULTI_LEVEL 0
93a23a72 22#define CONTEXT_TT_DEV_IOTLB 1
4ed0d3e6 23#define CONTEXT_TT_PASS_THROUGH 2
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24/* Extended context entry types */
25#define CONTEXT_TT_PT_PASID 4
26#define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
27#define CONTEXT_TT_MASK (7ULL << 2)
28
907fea34 29#define CONTEXT_DINVE (1ULL << 8)
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30#define CONTEXT_PRS (1ULL << 9)
31#define CONTEXT_PASIDE (1ULL << 11)
4ed0d3e6 32
e61d98d8 33struct intel_iommu;
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34struct dmar_domain;
35struct root_entry;
e61d98d8 36
c66b9906 37
d3f13810 38#ifdef CONFIG_INTEL_IOMMU
1b573683 39extern int iommu_calculate_agaw(struct intel_iommu *iommu);
4ed0d3e6 40extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
f5d1b97b 41extern int dmar_disabled;
8bc1f85c 42extern int intel_iommu_enabled;
bfd20f1c 43extern int intel_iommu_tboot_noforce;
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44#else
45static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
46{
47 return 0;
48}
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49static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
50{
51 return 0;
52}
f5d1b97b 53#define dmar_disabled (1)
8bc1f85c 54#define intel_iommu_enabled (0)
c66b9906 55#endif
e61d98d8 56
2ae21010 57
e61d98d8 58#endif