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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
7405f74b | 26 | #include <linux/dma-mapping.h> |
c13c8260 | 27 | |
c13c8260 | 28 | /** |
fe4ada2d | 29 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
30 | * |
31 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
32 | */ | |
33 | typedef s32 dma_cookie_t; | |
76bd061f SM |
34 | #define DMA_MIN_COOKIE 1 |
35 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 CL |
36 | |
37 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
38 | ||
39 | /** | |
40 | * enum dma_status - DMA transaction status | |
41 | * @DMA_SUCCESS: transaction completed successfully | |
42 | * @DMA_IN_PROGRESS: transaction not yet processed | |
43 | * @DMA_ERROR: transaction failed | |
44 | */ | |
45 | enum dma_status { | |
46 | DMA_SUCCESS, | |
47 | DMA_IN_PROGRESS, | |
48 | DMA_ERROR, | |
49 | }; | |
50 | ||
7405f74b DW |
51 | /** |
52 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
53 | * |
54 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
55 | * automatically set as dma devices are registered. | |
7405f74b DW |
56 | */ |
57 | enum dma_transaction_type { | |
58 | DMA_MEMCPY, | |
59 | DMA_XOR, | |
b2f46fd8 | 60 | DMA_PQ, |
099f53cb DW |
61 | DMA_XOR_VAL, |
62 | DMA_PQ_VAL, | |
7405f74b | 63 | DMA_MEMSET, |
7405f74b | 64 | DMA_INTERRUPT, |
59b5ec21 | 65 | DMA_PRIVATE, |
138f4c35 | 66 | DMA_ASYNC_TX, |
dc0ee643 | 67 | DMA_SLAVE, |
7405f74b DW |
68 | }; |
69 | ||
70 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
71 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
72 | ||
7405f74b | 73 | |
d4c56f97 | 74 | /** |
636bdeaa | 75 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 76 | * control completion, and communicate status. |
d4c56f97 | 77 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 78 | * this transaction |
a88f6667 | 79 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
80 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
81 | * chains | |
e1d181ef DW |
82 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
83 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
4f005dbe MS |
84 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
85 | * (if not set, do the source dma-unmapping as page) | |
86 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single | |
87 | * (if not set, do the destination dma-unmapping as page) | |
b2f46fd8 DW |
88 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
89 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
90 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
91 | * sources that were the result of a previous operation, in the case of a PQ | |
92 | * operation it continues the calculation with new sources | |
0403e382 DW |
93 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
94 | * on the result of this operation | |
d4c56f97 | 95 | */ |
636bdeaa | 96 | enum dma_ctrl_flags { |
d4c56f97 | 97 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 98 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
99 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
100 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
4f005dbe MS |
101 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
102 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), | |
f9dd2134 DW |
103 | DMA_PREP_PQ_DISABLE_P = (1 << 6), |
104 | DMA_PREP_PQ_DISABLE_Q = (1 << 7), | |
105 | DMA_PREP_CONTINUE = (1 << 8), | |
0403e382 | 106 | DMA_PREP_FENCE = (1 << 9), |
d4c56f97 DW |
107 | }; |
108 | ||
ad283ea4 DW |
109 | /** |
110 | * enum sum_check_bits - bit position of pq_check_flags | |
111 | */ | |
112 | enum sum_check_bits { | |
113 | SUM_CHECK_P = 0, | |
114 | SUM_CHECK_Q = 1, | |
115 | }; | |
116 | ||
117 | /** | |
118 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
119 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
120 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
121 | */ | |
122 | enum sum_check_flags { | |
123 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
124 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
125 | }; | |
126 | ||
127 | ||
7405f74b DW |
128 | /** |
129 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
130 | * See linux/cpumask.h | |
131 | */ | |
132 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
133 | ||
c13c8260 CL |
134 | /** |
135 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
136 | * @memcpy_count: transaction counter |
137 | * @bytes_transferred: byte counter | |
138 | */ | |
139 | ||
140 | struct dma_chan_percpu { | |
c13c8260 CL |
141 | /* stats */ |
142 | unsigned long memcpy_count; | |
143 | unsigned long bytes_transferred; | |
144 | }; | |
145 | ||
146 | /** | |
147 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 148 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 149 | * @cookie: last cookie value returned to client |
fe4ada2d | 150 | * @chan_id: channel ID for sysfs |
41d5e59c | 151 | * @dev: class device for sysfs |
c13c8260 CL |
152 | * @device_node: used to add this to the device chan list |
153 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 154 | * @client-count: how many clients are using this channel |
bec08513 | 155 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 156 | * @private: private data for certain client-channel associations |
c13c8260 CL |
157 | */ |
158 | struct dma_chan { | |
c13c8260 CL |
159 | struct dma_device *device; |
160 | dma_cookie_t cookie; | |
161 | ||
162 | /* sysfs */ | |
163 | int chan_id; | |
41d5e59c | 164 | struct dma_chan_dev *dev; |
c13c8260 | 165 | |
c13c8260 | 166 | struct list_head device_node; |
a29d8b8e | 167 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 168 | int client_count; |
bec08513 | 169 | int table_count; |
287d8592 | 170 | void *private; |
c13c8260 CL |
171 | }; |
172 | ||
41d5e59c DW |
173 | /** |
174 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
175 | * @chan - driver channel device | |
176 | * @device - sysfs device | |
864498aa DW |
177 | * @dev_id - parent dma_device dev_id |
178 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
179 | */ |
180 | struct dma_chan_dev { | |
181 | struct dma_chan *chan; | |
182 | struct device device; | |
864498aa DW |
183 | int dev_id; |
184 | atomic_t *idr_ref; | |
41d5e59c DW |
185 | }; |
186 | ||
187 | static inline const char *dma_chan_name(struct dma_chan *chan) | |
188 | { | |
189 | return dev_name(&chan->dev->device); | |
190 | } | |
d379b01e | 191 | |
c13c8260 CL |
192 | void dma_chan_cleanup(struct kref *kref); |
193 | ||
59b5ec21 DW |
194 | /** |
195 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
196 | * @chan: channel to be reviewed | |
197 | * @filter_param: opaque parameter passed through dma_request_channel | |
198 | * | |
199 | * When this optional parameter is specified in a call to dma_request_channel a | |
200 | * suitable channel is passed to this routine for further dispositioning before | |
201 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
202 | * satisfies the given capability mask. It returns 'true' to indicate that the |
203 | * channel is suitable. | |
59b5ec21 | 204 | */ |
7dd60251 | 205 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 206 | |
7405f74b DW |
207 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
208 | /** | |
209 | * struct dma_async_tx_descriptor - async transaction descriptor | |
210 | * ---dma generic offload fields--- | |
211 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
212 | * this tx is sitting on a dependency list | |
636bdeaa DW |
213 | * @flags: flags to augment operation preparation, control completion, and |
214 | * communicate status | |
7405f74b | 215 | * @phys: physical address of the descriptor |
7405f74b DW |
216 | * @chan: target channel for this operation |
217 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
218 | * @callback: routine to call after this operation is complete |
219 | * @callback_param: general parameter to pass to the callback routine | |
220 | * ---async_tx api specific fields--- | |
19242d72 | 221 | * @next: at completion submit this descriptor |
7405f74b | 222 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 223 | * @lock: protect the parent and next pointers |
7405f74b DW |
224 | */ |
225 | struct dma_async_tx_descriptor { | |
226 | dma_cookie_t cookie; | |
636bdeaa | 227 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 228 | dma_addr_t phys; |
7405f74b DW |
229 | struct dma_chan *chan; |
230 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
231 | dma_async_tx_callback callback; |
232 | void *callback_param; | |
19242d72 | 233 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
234 | struct dma_async_tx_descriptor *parent; |
235 | spinlock_t lock; | |
236 | }; | |
237 | ||
c13c8260 CL |
238 | /** |
239 | * struct dma_device - info on the entity supplying DMA services | |
240 | * @chancnt: how many DMA channels are supported | |
0f571515 | 241 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
242 | * @channels: the list of struct dma_chan |
243 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
244 | * @cap_mask: one or more dma_capability flags |
245 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 246 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
247 | * @copy_align: alignment shift for memcpy operations |
248 | * @xor_align: alignment shift for xor operations | |
249 | * @pq_align: alignment shift for pq operations | |
250 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 251 | * @dev_id: unique device ID |
7405f74b | 252 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
253 | * @device_alloc_chan_resources: allocate resources and return the |
254 | * number of allocated descriptors | |
255 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
256 | * @device_prep_dma_memcpy: prepares a memcpy operation |
257 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 258 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
259 | * @device_prep_dma_pq: prepares a pq operation |
260 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b DW |
261 | * @device_prep_dma_memset: prepares a memset operation |
262 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
263 | * @device_prep_slave_sg: prepares a slave dma operation |
264 | * @device_terminate_all: terminate all pending operations | |
1d93e52e | 265 | * @device_is_tx_complete: poll for transaction completion |
7405f74b | 266 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
267 | */ |
268 | struct dma_device { | |
269 | ||
270 | unsigned int chancnt; | |
0f571515 | 271 | unsigned int privatecnt; |
c13c8260 CL |
272 | struct list_head channels; |
273 | struct list_head global_node; | |
7405f74b | 274 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
275 | unsigned short max_xor; |
276 | unsigned short max_pq; | |
83544ae9 DW |
277 | u8 copy_align; |
278 | u8 xor_align; | |
279 | u8 pq_align; | |
280 | u8 fill_align; | |
b2f46fd8 | 281 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 282 | |
c13c8260 | 283 | int dev_id; |
7405f74b | 284 | struct device *dev; |
c13c8260 | 285 | |
aa1e6f1a | 286 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 287 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
288 | |
289 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 290 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 291 | size_t len, unsigned long flags); |
7405f74b | 292 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 293 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 294 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 295 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 296 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 297 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
298 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
299 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
300 | unsigned int src_cnt, const unsigned char *scf, | |
301 | size_t len, unsigned long flags); | |
302 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
303 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
304 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
305 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 306 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 307 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 308 | unsigned long flags); |
7405f74b | 309 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 310 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 311 | |
dc0ee643 HS |
312 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
313 | struct dma_chan *chan, struct scatterlist *sgl, | |
314 | unsigned int sg_len, enum dma_data_direction direction, | |
315 | unsigned long flags); | |
316 | void (*device_terminate_all)(struct dma_chan *chan); | |
317 | ||
7405f74b | 318 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
319 | dma_cookie_t cookie, dma_cookie_t *last, |
320 | dma_cookie_t *used); | |
7405f74b | 321 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
322 | }; |
323 | ||
83544ae9 DW |
324 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
325 | { | |
326 | size_t mask; | |
327 | ||
328 | if (!align) | |
329 | return true; | |
330 | mask = (1 << align) - 1; | |
331 | if (mask & (off1 | off2 | len)) | |
332 | return false; | |
333 | return true; | |
334 | } | |
335 | ||
336 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
337 | size_t off2, size_t len) | |
338 | { | |
339 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
340 | } | |
341 | ||
342 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
343 | size_t off2, size_t len) | |
344 | { | |
345 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
346 | } | |
347 | ||
348 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
349 | size_t off2, size_t len) | |
350 | { | |
351 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
352 | } | |
353 | ||
354 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
355 | size_t off2, size_t len) | |
356 | { | |
357 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
358 | } | |
359 | ||
b2f46fd8 DW |
360 | static inline void |
361 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
362 | { | |
363 | dma->max_pq = maxpq; | |
364 | if (has_pq_continue) | |
365 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
366 | } | |
367 | ||
368 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
369 | { | |
370 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
371 | } | |
372 | ||
373 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
374 | { | |
375 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
376 | ||
377 | return (flags & mask) == mask; | |
378 | } | |
379 | ||
380 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
381 | { | |
382 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
383 | } | |
384 | ||
385 | static unsigned short dma_dev_to_maxpq(struct dma_device *dma) | |
386 | { | |
387 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
388 | } | |
389 | ||
390 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
391 | * @dma - dma device with PQ capability | |
392 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
393 | * | |
394 | * When an engine does not support native continuation we need 3 extra | |
395 | * source slots to reuse P and Q with the following coefficients: | |
396 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
397 | * 2/ {01} * Q : use Q to continue Q' calculation | |
398 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
399 | * | |
400 | * In the case where P is disabled we only need 1 extra source: | |
401 | * 1/ {01} * Q : use Q to continue Q' calculation | |
402 | */ | |
403 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
404 | { | |
405 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
406 | return dma_dev_to_maxpq(dma); | |
407 | else if (dmaf_p_disabled_continue(flags)) | |
408 | return dma_dev_to_maxpq(dma) - 1; | |
409 | else if (dmaf_continue(flags)) | |
410 | return dma_dev_to_maxpq(dma) - 3; | |
411 | BUG(); | |
412 | } | |
413 | ||
c13c8260 CL |
414 | /* --- public DMA engine API --- */ |
415 | ||
649274d9 | 416 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
417 | void dmaengine_get(void); |
418 | void dmaengine_put(void); | |
649274d9 DW |
419 | #else |
420 | static inline void dmaengine_get(void) | |
421 | { | |
422 | } | |
423 | static inline void dmaengine_put(void) | |
424 | { | |
425 | } | |
426 | #endif | |
427 | ||
b4bd07c2 DM |
428 | #ifdef CONFIG_NET_DMA |
429 | #define net_dmaengine_get() dmaengine_get() | |
430 | #define net_dmaengine_put() dmaengine_put() | |
431 | #else | |
432 | static inline void net_dmaengine_get(void) | |
433 | { | |
434 | } | |
435 | static inline void net_dmaengine_put(void) | |
436 | { | |
437 | } | |
438 | #endif | |
439 | ||
729b5d1b DW |
440 | #ifdef CONFIG_ASYNC_TX_DMA |
441 | #define async_dmaengine_get() dmaengine_get() | |
442 | #define async_dmaengine_put() dmaengine_put() | |
138f4c35 DW |
443 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
444 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) | |
445 | #else | |
729b5d1b | 446 | #define async_dma_find_channel(type) dma_find_channel(type) |
138f4c35 | 447 | #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
448 | #else |
449 | static inline void async_dmaengine_get(void) | |
450 | { | |
451 | } | |
452 | static inline void async_dmaengine_put(void) | |
453 | { | |
454 | } | |
455 | static inline struct dma_chan * | |
456 | async_dma_find_channel(enum dma_transaction_type type) | |
457 | { | |
458 | return NULL; | |
459 | } | |
138f4c35 | 460 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 461 | |
7405f74b DW |
462 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
463 | void *dest, void *src, size_t len); | |
464 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
465 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
466 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
467 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
468 | unsigned int src_off, size_t len); | |
469 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
470 | struct dma_chan *chan); | |
c13c8260 | 471 | |
0839875e | 472 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 473 | { |
636bdeaa DW |
474 | tx->flags |= DMA_CTRL_ACK; |
475 | } | |
476 | ||
ef560682 GL |
477 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
478 | { | |
479 | tx->flags &= ~DMA_CTRL_ACK; | |
480 | } | |
481 | ||
0839875e | 482 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 483 | { |
0839875e | 484 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
485 | } |
486 | ||
7405f74b DW |
487 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
488 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 489 | { |
7405f74b DW |
490 | return min_t(int, DMA_TX_TYPE_END, |
491 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
492 | } | |
c13c8260 | 493 | |
7405f74b DW |
494 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
495 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
496 | { | |
497 | return min_t(int, DMA_TX_TYPE_END, | |
498 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
499 | } |
500 | ||
7405f74b DW |
501 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
502 | static inline void | |
503 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 504 | { |
7405f74b DW |
505 | set_bit(tx_type, dstp->bits); |
506 | } | |
c13c8260 | 507 | |
0f571515 AN |
508 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
509 | static inline void | |
510 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
511 | { | |
512 | clear_bit(tx_type, dstp->bits); | |
513 | } | |
514 | ||
33df8ca0 DW |
515 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
516 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
517 | { | |
518 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
519 | } | |
520 | ||
7405f74b DW |
521 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
522 | static inline int | |
523 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
524 | { | |
525 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
526 | } |
527 | ||
7405f74b DW |
528 | #define for_each_dma_cap_mask(cap, mask) \ |
529 | for ((cap) = first_dma_cap(mask); \ | |
530 | (cap) < DMA_TX_TYPE_END; \ | |
531 | (cap) = next_dma_cap((cap), (mask))) | |
532 | ||
c13c8260 | 533 | /** |
7405f74b | 534 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 535 | * @chan: target DMA channel |
c13c8260 CL |
536 | * |
537 | * This allows drivers to push copies to HW in batches, | |
538 | * reducing MMIO writes where possible. | |
539 | */ | |
7405f74b | 540 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 541 | { |
ec8670f1 | 542 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
543 | } |
544 | ||
7405f74b DW |
545 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
546 | ||
c13c8260 | 547 | /** |
7405f74b | 548 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
549 | * @chan: DMA channel |
550 | * @cookie: transaction identifier to check status of | |
551 | * @last: returns last completed cookie, can be NULL | |
552 | * @used: returns last issued cookie, can be NULL | |
553 | * | |
554 | * If @last and @used are passed in, upon return they reflect the driver | |
555 | * internal state and can be used with dma_async_is_complete() to check | |
556 | * the status of multiple cookies without re-checking hardware state. | |
557 | */ | |
7405f74b | 558 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
559 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
560 | { | |
7405f74b | 561 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
562 | } |
563 | ||
7405f74b DW |
564 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
565 | dma_async_is_tx_complete(chan, cookie, last, used) | |
566 | ||
c13c8260 CL |
567 | /** |
568 | * dma_async_is_complete - test a cookie against chan state | |
569 | * @cookie: transaction identifier to test status of | |
570 | * @last_complete: last know completed transaction | |
571 | * @last_used: last cookie value handed out | |
572 | * | |
573 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 574 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
575 | */ |
576 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
577 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
578 | { | |
579 | if (last_complete <= last_used) { | |
580 | if ((cookie <= last_complete) || (cookie > last_used)) | |
581 | return DMA_SUCCESS; | |
582 | } else { | |
583 | if ((cookie <= last_complete) && (cookie > last_used)) | |
584 | return DMA_SUCCESS; | |
585 | } | |
586 | return DMA_IN_PROGRESS; | |
587 | } | |
588 | ||
7405f74b | 589 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
590 | #ifdef CONFIG_DMA_ENGINE |
591 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 592 | void dma_issue_pending_all(void); |
07f2211e DW |
593 | #else |
594 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
595 | { | |
596 | return DMA_SUCCESS; | |
597 | } | |
c50331e8 DW |
598 | static inline void dma_issue_pending_all(void) |
599 | { | |
600 | do { } while (0); | |
601 | } | |
07f2211e | 602 | #endif |
c13c8260 CL |
603 | |
604 | /* --- DMA device --- */ | |
605 | ||
606 | int dma_async_device_register(struct dma_device *device); | |
607 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 608 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 609 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
59b5ec21 DW |
610 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
611 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
612 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 613 | |
de5506e1 CL |
614 | /* --- Helper iov-locking functions --- */ |
615 | ||
616 | struct dma_page_list { | |
b2ddb901 | 617 | char __user *base_address; |
de5506e1 CL |
618 | int nr_pages; |
619 | struct page **pages; | |
620 | }; | |
621 | ||
622 | struct dma_pinned_list { | |
623 | int nr_iovecs; | |
624 | struct dma_page_list page_list[0]; | |
625 | }; | |
626 | ||
627 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
628 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
629 | ||
630 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
631 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
632 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
633 | struct dma_pinned_list *pinned_list, struct page *page, | |
634 | unsigned int offset, size_t len); | |
635 | ||
c13c8260 | 636 | #endif /* DMAENGINE_H */ |