]>
Commit | Line | Data |
---|---|---|
c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
d2ebfb33 RKAL |
21 | #ifndef LINUX_DMAENGINE_H |
22 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
187f1882 | 26 | #include <linux/bug.h> |
90b44f8f | 27 | #include <linux/scatterlist.h> |
a8efa9d6 | 28 | #include <linux/bitmap.h> |
dcc043dc | 29 | #include <linux/types.h> |
a8efa9d6 | 30 | #include <asm/page.h> |
b7f080cf | 31 | |
c13c8260 | 32 | /** |
fe4ada2d | 33 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
34 | * |
35 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
36 | */ | |
37 | typedef s32 dma_cookie_t; | |
76bd061f SM |
38 | #define DMA_MIN_COOKIE 1 |
39 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 | 40 | |
71ea1483 DC |
41 | static inline int dma_submit_error(dma_cookie_t cookie) |
42 | { | |
43 | return cookie < 0 ? cookie : 0; | |
44 | } | |
c13c8260 CL |
45 | |
46 | /** | |
47 | * enum dma_status - DMA transaction status | |
adfedd9a | 48 | * @DMA_COMPLETE: transaction completed |
c13c8260 | 49 | * @DMA_IN_PROGRESS: transaction not yet processed |
07934481 | 50 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
51 | * @DMA_ERROR: transaction failed |
52 | */ | |
53 | enum dma_status { | |
7db5f727 | 54 | DMA_COMPLETE, |
c13c8260 | 55 | DMA_IN_PROGRESS, |
07934481 | 56 | DMA_PAUSED, |
c13c8260 CL |
57 | DMA_ERROR, |
58 | }; | |
59 | ||
7405f74b DW |
60 | /** |
61 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
62 | * |
63 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
64 | * automatically set as dma devices are registered. | |
7405f74b DW |
65 | */ |
66 | enum dma_transaction_type { | |
67 | DMA_MEMCPY, | |
68 | DMA_XOR, | |
b2f46fd8 | 69 | DMA_PQ, |
099f53cb DW |
70 | DMA_XOR_VAL, |
71 | DMA_PQ_VAL, | |
7405f74b | 72 | DMA_INTERRUPT, |
a86ee03c | 73 | DMA_SG, |
59b5ec21 | 74 | DMA_PRIVATE, |
138f4c35 | 75 | DMA_ASYNC_TX, |
dc0ee643 | 76 | DMA_SLAVE, |
782bc950 | 77 | DMA_CYCLIC, |
b14dab79 | 78 | DMA_INTERLEAVE, |
7405f74b | 79 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
80 | DMA_TX_TYPE_END, |
81 | }; | |
dc0ee643 | 82 | |
49920bc6 VK |
83 | /** |
84 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
85 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
86 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
87 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
88 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
89 | */ | |
90 | enum dma_transfer_direction { | |
91 | DMA_MEM_TO_MEM, | |
92 | DMA_MEM_TO_DEV, | |
93 | DMA_DEV_TO_MEM, | |
94 | DMA_DEV_TO_DEV, | |
62268ce9 | 95 | DMA_TRANS_NONE, |
49920bc6 | 96 | }; |
7405f74b | 97 | |
b14dab79 JB |
98 | /** |
99 | * Interleaved Transfer Request | |
100 | * ---------------------------- | |
101 | * A chunk is collection of contiguous bytes to be transfered. | |
102 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
103 | * ICGs may or maynot change between chunks. | |
104 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
105 | * that when repeated an integral number of times, specifies the transfer. | |
106 | * A transfer template is specification of a Frame, the number of times | |
107 | * it is to be repeated and other per-transfer attributes. | |
108 | * | |
109 | * Practically, a client driver would have ready a template for each | |
110 | * type of transfer it is going to need during its lifetime and | |
111 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
112 | * | |
113 | * | |
114 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
115 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
116 | * | |
117 | * == Chunk size | |
118 | * ... ICG | |
119 | */ | |
120 | ||
121 | /** | |
122 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
123 | * @size: Number of bytes to read from source. | |
124 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
125 | * @icg: Number of bytes to jump after last src/dst address of this | |
126 | * chunk and before first src/dst address for next chunk. | |
127 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
128 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
129 | */ | |
130 | struct data_chunk { | |
131 | size_t size; | |
132 | size_t icg; | |
133 | }; | |
134 | ||
135 | /** | |
136 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
137 | * and attributes. | |
138 | * @src_start: Bus address of source for the first chunk. | |
139 | * @dst_start: Bus address of destination for the first chunk. | |
140 | * @dir: Specifies the type of Source and Destination. | |
141 | * @src_inc: If the source address increments after reading from it. | |
142 | * @dst_inc: If the destination address increments after writing to it. | |
143 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
144 | * Otherwise, source is read contiguously (icg ignored). | |
145 | * Ignored if src_inc is false. | |
146 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
147 | * Otherwise, destination is filled contiguously (icg ignored). | |
148 | * Ignored if dst_inc is false. | |
149 | * @numf: Number of frames in this template. | |
150 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
151 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
152 | */ | |
153 | struct dma_interleaved_template { | |
154 | dma_addr_t src_start; | |
155 | dma_addr_t dst_start; | |
156 | enum dma_transfer_direction dir; | |
157 | bool src_inc; | |
158 | bool dst_inc; | |
159 | bool src_sgl; | |
160 | bool dst_sgl; | |
161 | size_t numf; | |
162 | size_t frame_size; | |
163 | struct data_chunk sgl[0]; | |
164 | }; | |
165 | ||
d4c56f97 | 166 | /** |
636bdeaa | 167 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 168 | * control completion, and communicate status. |
d4c56f97 | 169 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 170 | * this transaction |
a88f6667 | 171 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
172 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
173 | * chains | |
b2f46fd8 DW |
174 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
175 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
176 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
177 | * sources that were the result of a previous operation, in the case of a PQ | |
178 | * operation it continues the calculation with new sources | |
0403e382 DW |
179 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
180 | * on the result of this operation | |
d4c56f97 | 181 | */ |
636bdeaa | 182 | enum dma_ctrl_flags { |
d4c56f97 | 183 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 184 | DMA_CTRL_ACK = (1 << 1), |
0776ae7b BZ |
185 | DMA_PREP_PQ_DISABLE_P = (1 << 2), |
186 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
187 | DMA_PREP_CONTINUE = (1 << 4), | |
188 | DMA_PREP_FENCE = (1 << 5), | |
d4c56f97 DW |
189 | }; |
190 | ||
c3635c78 LW |
191 | /** |
192 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised | |
193 | * on a running channel. | |
194 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers | |
195 | * @DMA_PAUSE: pause ongoing transfers | |
196 | * @DMA_RESUME: resume paused transfer | |
c156d0a5 LW |
197 | * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers |
198 | * that need to runtime reconfigure the slave channels (as opposed to passing | |
199 | * configuration data in statically from the platform). An additional | |
200 | * argument of struct dma_slave_config must be passed in with this | |
201 | * command. | |
968f19ae IS |
202 | * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller |
203 | * into external start mode. | |
c3635c78 LW |
204 | */ |
205 | enum dma_ctrl_cmd { | |
206 | DMA_TERMINATE_ALL, | |
207 | DMA_PAUSE, | |
208 | DMA_RESUME, | |
c156d0a5 | 209 | DMA_SLAVE_CONFIG, |
968f19ae | 210 | FSLDMA_EXTERNAL_START, |
c3635c78 LW |
211 | }; |
212 | ||
ad283ea4 DW |
213 | /** |
214 | * enum sum_check_bits - bit position of pq_check_flags | |
215 | */ | |
216 | enum sum_check_bits { | |
217 | SUM_CHECK_P = 0, | |
218 | SUM_CHECK_Q = 1, | |
219 | }; | |
220 | ||
221 | /** | |
222 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
223 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
224 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
225 | */ | |
226 | enum sum_check_flags { | |
227 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
228 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
229 | }; | |
230 | ||
231 | ||
7405f74b DW |
232 | /** |
233 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
234 | * See linux/cpumask.h | |
235 | */ | |
236 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
237 | ||
c13c8260 CL |
238 | /** |
239 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
240 | * @memcpy_count: transaction counter |
241 | * @bytes_transferred: byte counter | |
242 | */ | |
243 | ||
244 | struct dma_chan_percpu { | |
c13c8260 CL |
245 | /* stats */ |
246 | unsigned long memcpy_count; | |
247 | unsigned long bytes_transferred; | |
248 | }; | |
249 | ||
250 | /** | |
251 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 252 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 253 | * @cookie: last cookie value returned to client |
4d4e58de | 254 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 255 | * @chan_id: channel ID for sysfs |
41d5e59c | 256 | * @dev: class device for sysfs |
c13c8260 CL |
257 | * @device_node: used to add this to the device chan list |
258 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 259 | * @client-count: how many clients are using this channel |
bec08513 | 260 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 261 | * @private: private data for certain client-channel associations |
c13c8260 CL |
262 | */ |
263 | struct dma_chan { | |
c13c8260 CL |
264 | struct dma_device *device; |
265 | dma_cookie_t cookie; | |
4d4e58de | 266 | dma_cookie_t completed_cookie; |
c13c8260 CL |
267 | |
268 | /* sysfs */ | |
269 | int chan_id; | |
41d5e59c | 270 | struct dma_chan_dev *dev; |
c13c8260 | 271 | |
c13c8260 | 272 | struct list_head device_node; |
a29d8b8e | 273 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 274 | int client_count; |
bec08513 | 275 | int table_count; |
287d8592 | 276 | void *private; |
c13c8260 CL |
277 | }; |
278 | ||
41d5e59c DW |
279 | /** |
280 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
281 | * @chan - driver channel device | |
282 | * @device - sysfs device | |
864498aa DW |
283 | * @dev_id - parent dma_device dev_id |
284 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
285 | */ |
286 | struct dma_chan_dev { | |
287 | struct dma_chan *chan; | |
288 | struct device device; | |
864498aa DW |
289 | int dev_id; |
290 | atomic_t *idr_ref; | |
41d5e59c DW |
291 | }; |
292 | ||
c156d0a5 LW |
293 | /** |
294 | * enum dma_slave_buswidth - defines bus with of the DMA slave | |
295 | * device, source or target buses | |
296 | */ | |
297 | enum dma_slave_buswidth { | |
298 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
299 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
300 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
301 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, | |
302 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
303 | }; | |
304 | ||
305 | /** | |
306 | * struct dma_slave_config - dma slave channel runtime config | |
307 | * @direction: whether the data shall go in or out on this slave | |
308 | * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are | |
309 | * legal values, DMA_BIDIRECTIONAL is not acceptable since we | |
310 | * need to differentiate source and target addresses. | |
311 | * @src_addr: this is the physical address where DMA slave data | |
312 | * should be read (RX), if the source is memory this argument is | |
313 | * ignored. | |
314 | * @dst_addr: this is the physical address where DMA slave data | |
315 | * should be written (TX), if the source is memory this argument | |
316 | * is ignored. | |
317 | * @src_addr_width: this is the width in bytes of the source (RX) | |
318 | * register where DMA data shall be read. If the source | |
319 | * is memory this may be ignored depending on architecture. | |
320 | * Legal values: 1, 2, 4, 8. | |
321 | * @dst_addr_width: same as src_addr_width but for destination | |
322 | * target (TX) mutatis mutandis. | |
323 | * @src_maxburst: the maximum number of words (note: words, as in | |
324 | * units of the src_addr_width member, not bytes) that can be sent | |
325 | * in one burst to the device. Typically something like half the | |
326 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
327 | * may or may not be applicable on memory sources. | |
328 | * @dst_maxburst: same as src_maxburst but for destination target | |
329 | * mutatis mutandis. | |
dcc043dc VK |
330 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
331 | * with 'true' if peripheral should be flow controller. Direction will be | |
332 | * selected at Runtime. | |
4fd1e324 LD |
333 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
334 | * slave peripheral will have unique id as dma requester which need to be | |
335 | * pass as slave config. | |
c156d0a5 LW |
336 | * |
337 | * This struct is passed in as configuration data to a DMA engine | |
338 | * in order to set up a certain channel for DMA transport at runtime. | |
339 | * The DMA device/engine has to provide support for an additional | |
340 | * command in the channel config interface, DMA_SLAVE_CONFIG | |
341 | * and this struct will then be passed in as an argument to the | |
342 | * DMA engine device_control() function. | |
343 | * | |
344 | * The rationale for adding configuration information to this struct | |
345 | * is as follows: if it is likely that most DMA slave controllers in | |
346 | * the world will support the configuration option, then make it | |
347 | * generic. If not: if it is fixed so that it be sent in static from | |
348 | * the platform data, then prefer to do that. Else, if it is neither | |
349 | * fixed at runtime, nor generic enough (such as bus mastership on | |
350 | * some CPU family and whatnot) then create a custom slave config | |
351 | * struct and pass that, then make this config a member of that | |
352 | * struct, if applicable. | |
353 | */ | |
354 | struct dma_slave_config { | |
49920bc6 | 355 | enum dma_transfer_direction direction; |
c156d0a5 LW |
356 | dma_addr_t src_addr; |
357 | dma_addr_t dst_addr; | |
358 | enum dma_slave_buswidth src_addr_width; | |
359 | enum dma_slave_buswidth dst_addr_width; | |
360 | u32 src_maxburst; | |
361 | u32 dst_maxburst; | |
dcc043dc | 362 | bool device_fc; |
4fd1e324 | 363 | unsigned int slave_id; |
c156d0a5 LW |
364 | }; |
365 | ||
221a27c7 VK |
366 | /* struct dma_slave_caps - expose capabilities of a slave channel only |
367 | * | |
368 | * @src_addr_widths: bit mask of src addr widths the channel supports | |
369 | * @dstn_addr_widths: bit mask of dstn addr widths the channel supports | |
370 | * @directions: bit mask of slave direction the channel supported | |
371 | * since the enum dma_transfer_direction is not defined as bits for each | |
372 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | |
373 | * should be checked by controller as well | |
374 | * @cmd_pause: true, if pause and thereby resume is supported | |
375 | * @cmd_terminate: true, if terminate cmd is supported | |
221a27c7 VK |
376 | */ |
377 | struct dma_slave_caps { | |
378 | u32 src_addr_widths; | |
379 | u32 dstn_addr_widths; | |
380 | u32 directions; | |
381 | bool cmd_pause; | |
382 | bool cmd_terminate; | |
221a27c7 VK |
383 | }; |
384 | ||
41d5e59c DW |
385 | static inline const char *dma_chan_name(struct dma_chan *chan) |
386 | { | |
387 | return dev_name(&chan->dev->device); | |
388 | } | |
d379b01e | 389 | |
c13c8260 CL |
390 | void dma_chan_cleanup(struct kref *kref); |
391 | ||
59b5ec21 DW |
392 | /** |
393 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
394 | * @chan: channel to be reviewed | |
395 | * @filter_param: opaque parameter passed through dma_request_channel | |
396 | * | |
397 | * When this optional parameter is specified in a call to dma_request_channel a | |
398 | * suitable channel is passed to this routine for further dispositioning before | |
399 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
400 | * satisfies the given capability mask. It returns 'true' to indicate that the |
401 | * channel is suitable. | |
59b5ec21 | 402 | */ |
7dd60251 | 403 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 404 | |
7405f74b | 405 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
d38a8c62 DW |
406 | |
407 | struct dmaengine_unmap_data { | |
408 | u8 to_cnt; | |
409 | u8 from_cnt; | |
410 | u8 bidi_cnt; | |
411 | struct device *dev; | |
412 | struct kref kref; | |
413 | size_t len; | |
414 | dma_addr_t addr[0]; | |
415 | }; | |
416 | ||
7405f74b DW |
417 | /** |
418 | * struct dma_async_tx_descriptor - async transaction descriptor | |
419 | * ---dma generic offload fields--- | |
420 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
421 | * this tx is sitting on a dependency list | |
636bdeaa DW |
422 | * @flags: flags to augment operation preparation, control completion, and |
423 | * communicate status | |
7405f74b | 424 | * @phys: physical address of the descriptor |
7405f74b DW |
425 | * @chan: target channel for this operation |
426 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
427 | * @callback: routine to call after this operation is complete |
428 | * @callback_param: general parameter to pass to the callback routine | |
429 | * ---async_tx api specific fields--- | |
19242d72 | 430 | * @next: at completion submit this descriptor |
7405f74b | 431 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 432 | * @lock: protect the parent and next pointers |
7405f74b DW |
433 | */ |
434 | struct dma_async_tx_descriptor { | |
435 | dma_cookie_t cookie; | |
636bdeaa | 436 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 437 | dma_addr_t phys; |
7405f74b DW |
438 | struct dma_chan *chan; |
439 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
440 | dma_async_tx_callback callback; |
441 | void *callback_param; | |
d38a8c62 | 442 | struct dmaengine_unmap_data *unmap; |
5fc6d897 | 443 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 444 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
445 | struct dma_async_tx_descriptor *parent; |
446 | spinlock_t lock; | |
caa20d97 | 447 | #endif |
7405f74b DW |
448 | }; |
449 | ||
89716462 | 450 | #ifdef CONFIG_DMA_ENGINE |
d38a8c62 DW |
451 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, |
452 | struct dmaengine_unmap_data *unmap) | |
453 | { | |
454 | kref_get(&unmap->kref); | |
455 | tx->unmap = unmap; | |
456 | } | |
457 | ||
89716462 DW |
458 | struct dmaengine_unmap_data * |
459 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
45c463ae | 460 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); |
89716462 DW |
461 | #else |
462 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
463 | struct dmaengine_unmap_data *unmap) | |
464 | { | |
465 | } | |
466 | static inline struct dmaengine_unmap_data * | |
467 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
468 | { | |
469 | return NULL; | |
470 | } | |
471 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
472 | { | |
473 | } | |
474 | #endif | |
45c463ae | 475 | |
d38a8c62 DW |
476 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) |
477 | { | |
478 | if (tx->unmap) { | |
45c463ae | 479 | dmaengine_unmap_put(tx->unmap); |
d38a8c62 DW |
480 | tx->unmap = NULL; |
481 | } | |
482 | } | |
483 | ||
5fc6d897 | 484 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
485 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
486 | { | |
487 | } | |
488 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
489 | { | |
490 | } | |
491 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
492 | { | |
493 | BUG(); | |
494 | } | |
495 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
496 | { | |
497 | } | |
498 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
499 | { | |
500 | } | |
501 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
502 | { | |
503 | return NULL; | |
504 | } | |
505 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
506 | { | |
507 | return NULL; | |
508 | } | |
509 | ||
510 | #else | |
511 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
512 | { | |
513 | spin_lock_bh(&txd->lock); | |
514 | } | |
515 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
516 | { | |
517 | spin_unlock_bh(&txd->lock); | |
518 | } | |
519 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
520 | { | |
521 | txd->next = next; | |
522 | next->parent = txd; | |
523 | } | |
524 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
525 | { | |
526 | txd->parent = NULL; | |
527 | } | |
528 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
529 | { | |
530 | txd->next = NULL; | |
531 | } | |
532 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
533 | { | |
534 | return txd->parent; | |
535 | } | |
536 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
537 | { | |
538 | return txd->next; | |
539 | } | |
540 | #endif | |
541 | ||
07934481 LW |
542 | /** |
543 | * struct dma_tx_state - filled in to report the status of | |
544 | * a transfer. | |
545 | * @last: last completed DMA cookie | |
546 | * @used: last issued DMA cookie (i.e. the one in progress) | |
547 | * @residue: the remaining number of bytes left to transmit | |
548 | * on the selected transfer for states DMA_IN_PROGRESS and | |
549 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
550 | */ | |
551 | struct dma_tx_state { | |
552 | dma_cookie_t last; | |
553 | dma_cookie_t used; | |
554 | u32 residue; | |
555 | }; | |
556 | ||
c13c8260 CL |
557 | /** |
558 | * struct dma_device - info on the entity supplying DMA services | |
559 | * @chancnt: how many DMA channels are supported | |
0f571515 | 560 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
561 | * @channels: the list of struct dma_chan |
562 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
563 | * @cap_mask: one or more dma_capability flags |
564 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 565 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
566 | * @copy_align: alignment shift for memcpy operations |
567 | * @xor_align: alignment shift for xor operations | |
568 | * @pq_align: alignment shift for pq operations | |
569 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 570 | * @dev_id: unique device ID |
7405f74b | 571 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
572 | * @device_alloc_chan_resources: allocate resources and return the |
573 | * number of allocated descriptors | |
574 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
575 | * @device_prep_dma_memcpy: prepares a memcpy operation |
576 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 577 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
578 | * @device_prep_dma_pq: prepares a pq operation |
579 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b | 580 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 581 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
582 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
583 | * The function takes a buffer of size buf_len. The callback function will | |
584 | * be called after period_len bytes have been transferred. | |
b14dab79 | 585 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
c3635c78 LW |
586 | * @device_control: manipulate all pending operations on a channel, returns |
587 | * zero or error code | |
07934481 LW |
588 | * @device_tx_status: poll for transaction completion, the optional |
589 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 590 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 591 | * will just return a simple status code |
7405f74b | 592 | * @device_issue_pending: push pending transactions to hardware |
221a27c7 | 593 | * @device_slave_caps: return the slave channel capabilities |
c13c8260 CL |
594 | */ |
595 | struct dma_device { | |
596 | ||
597 | unsigned int chancnt; | |
0f571515 | 598 | unsigned int privatecnt; |
c13c8260 CL |
599 | struct list_head channels; |
600 | struct list_head global_node; | |
7405f74b | 601 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
602 | unsigned short max_xor; |
603 | unsigned short max_pq; | |
83544ae9 DW |
604 | u8 copy_align; |
605 | u8 xor_align; | |
606 | u8 pq_align; | |
607 | u8 fill_align; | |
b2f46fd8 | 608 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 609 | |
c13c8260 | 610 | int dev_id; |
7405f74b | 611 | struct device *dev; |
c13c8260 | 612 | |
aa1e6f1a | 613 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 614 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
615 | |
616 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 617 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 618 | size_t len, unsigned long flags); |
7405f74b | 619 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 620 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 621 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 622 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 623 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 624 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
625 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
626 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
627 | unsigned int src_cnt, const unsigned char *scf, | |
628 | size_t len, unsigned long flags); | |
629 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
630 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
631 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
632 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 633 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 634 | struct dma_chan *chan, unsigned long flags); |
a86ee03c IS |
635 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
636 | struct dma_chan *chan, | |
637 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
638 | struct scatterlist *src_sg, unsigned int src_nents, | |
639 | unsigned long flags); | |
7405f74b | 640 | |
dc0ee643 HS |
641 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
642 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 643 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 644 | unsigned long flags, void *context); |
782bc950 SH |
645 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
646 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 647 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 648 | unsigned long flags, void *context); |
b14dab79 JB |
649 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
650 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
651 | unsigned long flags); | |
05827630 LW |
652 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
653 | unsigned long arg); | |
dc0ee643 | 654 | |
07934481 LW |
655 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
656 | dma_cookie_t cookie, | |
657 | struct dma_tx_state *txstate); | |
7405f74b | 658 | void (*device_issue_pending)(struct dma_chan *chan); |
221a27c7 | 659 | int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); |
c13c8260 CL |
660 | }; |
661 | ||
6e3ecaf0 SH |
662 | static inline int dmaengine_device_control(struct dma_chan *chan, |
663 | enum dma_ctrl_cmd cmd, | |
664 | unsigned long arg) | |
665 | { | |
944ea4dd JM |
666 | if (chan->device->device_control) |
667 | return chan->device->device_control(chan, cmd, arg); | |
978c4172 AS |
668 | |
669 | return -ENOSYS; | |
6e3ecaf0 SH |
670 | } |
671 | ||
672 | static inline int dmaengine_slave_config(struct dma_chan *chan, | |
673 | struct dma_slave_config *config) | |
674 | { | |
675 | return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, | |
676 | (unsigned long)config); | |
677 | } | |
678 | ||
61cc13a5 AS |
679 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
680 | { | |
681 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
682 | } | |
683 | ||
90b44f8f | 684 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 685 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 686 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
687 | { |
688 | struct scatterlist sg; | |
922ee08b KM |
689 | sg_init_table(&sg, 1); |
690 | sg_dma_address(&sg) = buf; | |
691 | sg_dma_len(&sg) = len; | |
90b44f8f | 692 | |
185ecb5f AB |
693 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
694 | dir, flags, NULL); | |
90b44f8f VK |
695 | } |
696 | ||
16052827 AB |
697 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
698 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
699 | enum dma_transfer_direction dir, unsigned long flags) | |
700 | { | |
701 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
185ecb5f | 702 | dir, flags, NULL); |
16052827 AB |
703 | } |
704 | ||
e42d98eb AB |
705 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
706 | struct rio_dma_ext; | |
707 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
708 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
709 | enum dma_transfer_direction dir, unsigned long flags, | |
710 | struct rio_dma_ext *rio_ext) | |
711 | { | |
712 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
713 | dir, flags, rio_ext); | |
714 | } | |
715 | #endif | |
716 | ||
16052827 AB |
717 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
718 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
719 | size_t period_len, enum dma_transfer_direction dir, |
720 | unsigned long flags) | |
16052827 AB |
721 | { |
722 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
ec8b5e48 | 723 | period_len, dir, flags, NULL); |
a14acb4a BS |
724 | } |
725 | ||
726 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
727 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
728 | unsigned long flags) | |
729 | { | |
730 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
90b44f8f VK |
731 | } |
732 | ||
221a27c7 VK |
733 | static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) |
734 | { | |
735 | if (!chan || !caps) | |
736 | return -EINVAL; | |
737 | ||
738 | /* check if the channel supports slave transactions */ | |
739 | if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits)) | |
740 | return -ENXIO; | |
741 | ||
742 | if (chan->device->device_slave_caps) | |
743 | return chan->device->device_slave_caps(chan, caps); | |
744 | ||
745 | return -ENXIO; | |
746 | } | |
747 | ||
6e3ecaf0 SH |
748 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
749 | { | |
750 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); | |
751 | } | |
752 | ||
753 | static inline int dmaengine_pause(struct dma_chan *chan) | |
754 | { | |
755 | return dmaengine_device_control(chan, DMA_PAUSE, 0); | |
756 | } | |
757 | ||
758 | static inline int dmaengine_resume(struct dma_chan *chan) | |
759 | { | |
760 | return dmaengine_device_control(chan, DMA_RESUME, 0); | |
761 | } | |
762 | ||
3052cc2c LPC |
763 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
764 | dma_cookie_t cookie, struct dma_tx_state *state) | |
765 | { | |
766 | return chan->device->device_tx_status(chan, cookie, state); | |
767 | } | |
768 | ||
98d530fe | 769 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
770 | { |
771 | return desc->tx_submit(desc); | |
772 | } | |
773 | ||
83544ae9 DW |
774 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
775 | { | |
776 | size_t mask; | |
777 | ||
778 | if (!align) | |
779 | return true; | |
780 | mask = (1 << align) - 1; | |
781 | if (mask & (off1 | off2 | len)) | |
782 | return false; | |
783 | return true; | |
784 | } | |
785 | ||
786 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
787 | size_t off2, size_t len) | |
788 | { | |
789 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
790 | } | |
791 | ||
792 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
793 | size_t off2, size_t len) | |
794 | { | |
795 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
796 | } | |
797 | ||
798 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
799 | size_t off2, size_t len) | |
800 | { | |
801 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
802 | } | |
803 | ||
804 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
805 | size_t off2, size_t len) | |
806 | { | |
807 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
808 | } | |
809 | ||
b2f46fd8 DW |
810 | static inline void |
811 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
812 | { | |
813 | dma->max_pq = maxpq; | |
814 | if (has_pq_continue) | |
815 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
816 | } | |
817 | ||
818 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
819 | { | |
820 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
821 | } | |
822 | ||
823 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
824 | { | |
825 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
826 | ||
827 | return (flags & mask) == mask; | |
828 | } | |
829 | ||
830 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
831 | { | |
832 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
833 | } | |
834 | ||
d3f3cf85 | 835 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
836 | { |
837 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
838 | } | |
839 | ||
840 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
841 | * @dma - dma device with PQ capability | |
842 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
843 | * | |
844 | * When an engine does not support native continuation we need 3 extra | |
845 | * source slots to reuse P and Q with the following coefficients: | |
846 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
847 | * 2/ {01} * Q : use Q to continue Q' calculation | |
848 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
849 | * | |
850 | * In the case where P is disabled we only need 1 extra source: | |
851 | * 1/ {01} * Q : use Q to continue Q' calculation | |
852 | */ | |
853 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
854 | { | |
855 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
856 | return dma_dev_to_maxpq(dma); | |
857 | else if (dmaf_p_disabled_continue(flags)) | |
858 | return dma_dev_to_maxpq(dma) - 1; | |
859 | else if (dmaf_continue(flags)) | |
860 | return dma_dev_to_maxpq(dma) - 3; | |
861 | BUG(); | |
862 | } | |
863 | ||
c13c8260 CL |
864 | /* --- public DMA engine API --- */ |
865 | ||
649274d9 | 866 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
867 | void dmaengine_get(void); |
868 | void dmaengine_put(void); | |
649274d9 DW |
869 | #else |
870 | static inline void dmaengine_get(void) | |
871 | { | |
872 | } | |
873 | static inline void dmaengine_put(void) | |
874 | { | |
875 | } | |
876 | #endif | |
877 | ||
b4bd07c2 DM |
878 | #ifdef CONFIG_NET_DMA |
879 | #define net_dmaengine_get() dmaengine_get() | |
880 | #define net_dmaengine_put() dmaengine_put() | |
881 | #else | |
882 | static inline void net_dmaengine_get(void) | |
883 | { | |
884 | } | |
885 | static inline void net_dmaengine_put(void) | |
886 | { | |
887 | } | |
888 | #endif | |
889 | ||
729b5d1b DW |
890 | #ifdef CONFIG_ASYNC_TX_DMA |
891 | #define async_dmaengine_get() dmaengine_get() | |
892 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 893 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
894 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
895 | #else | |
729b5d1b | 896 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 897 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
898 | #else |
899 | static inline void async_dmaengine_get(void) | |
900 | { | |
901 | } | |
902 | static inline void async_dmaengine_put(void) | |
903 | { | |
904 | } | |
905 | static inline struct dma_chan * | |
906 | async_dma_find_channel(enum dma_transaction_type type) | |
907 | { | |
908 | return NULL; | |
909 | } | |
138f4c35 | 910 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 911 | |
7405f74b DW |
912 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
913 | void *dest, void *src, size_t len); | |
914 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
915 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
916 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
917 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
918 | unsigned int src_off, size_t len); | |
919 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
920 | struct dma_chan *chan); | |
c13c8260 | 921 | |
0839875e | 922 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 923 | { |
636bdeaa DW |
924 | tx->flags |= DMA_CTRL_ACK; |
925 | } | |
926 | ||
ef560682 GL |
927 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
928 | { | |
929 | tx->flags &= ~DMA_CTRL_ACK; | |
930 | } | |
931 | ||
0839875e | 932 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 933 | { |
0839875e | 934 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
935 | } |
936 | ||
7405f74b DW |
937 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
938 | static inline void | |
939 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 940 | { |
7405f74b DW |
941 | set_bit(tx_type, dstp->bits); |
942 | } | |
c13c8260 | 943 | |
0f571515 AN |
944 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
945 | static inline void | |
946 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
947 | { | |
948 | clear_bit(tx_type, dstp->bits); | |
949 | } | |
950 | ||
33df8ca0 DW |
951 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
952 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
953 | { | |
954 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
955 | } | |
956 | ||
7405f74b DW |
957 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
958 | static inline int | |
959 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
960 | { | |
961 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
962 | } |
963 | ||
7405f74b | 964 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 965 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 966 | |
c13c8260 | 967 | /** |
7405f74b | 968 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 969 | * @chan: target DMA channel |
c13c8260 CL |
970 | * |
971 | * This allows drivers to push copies to HW in batches, | |
972 | * reducing MMIO writes where possible. | |
973 | */ | |
7405f74b | 974 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 975 | { |
ec8670f1 | 976 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
977 | } |
978 | ||
979 | /** | |
7405f74b | 980 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
981 | * @chan: DMA channel |
982 | * @cookie: transaction identifier to check status of | |
983 | * @last: returns last completed cookie, can be NULL | |
984 | * @used: returns last issued cookie, can be NULL | |
985 | * | |
986 | * If @last and @used are passed in, upon return they reflect the driver | |
987 | * internal state and can be used with dma_async_is_complete() to check | |
988 | * the status of multiple cookies without re-checking hardware state. | |
989 | */ | |
7405f74b | 990 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
991 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
992 | { | |
07934481 LW |
993 | struct dma_tx_state state; |
994 | enum dma_status status; | |
995 | ||
996 | status = chan->device->device_tx_status(chan, cookie, &state); | |
997 | if (last) | |
998 | *last = state.last; | |
999 | if (used) | |
1000 | *used = state.used; | |
1001 | return status; | |
c13c8260 CL |
1002 | } |
1003 | ||
1004 | /** | |
1005 | * dma_async_is_complete - test a cookie against chan state | |
1006 | * @cookie: transaction identifier to test status of | |
1007 | * @last_complete: last know completed transaction | |
1008 | * @last_used: last cookie value handed out | |
1009 | * | |
e239345f | 1010 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 1011 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
1012 | */ |
1013 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1014 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1015 | { | |
1016 | if (last_complete <= last_used) { | |
1017 | if ((cookie <= last_complete) || (cookie > last_used)) | |
adfedd9a | 1018 | return DMA_COMPLETE; |
c13c8260 CL |
1019 | } else { |
1020 | if ((cookie <= last_complete) && (cookie > last_used)) | |
adfedd9a | 1021 | return DMA_COMPLETE; |
c13c8260 CL |
1022 | } |
1023 | return DMA_IN_PROGRESS; | |
1024 | } | |
1025 | ||
bca34692 DW |
1026 | static inline void |
1027 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1028 | { | |
1029 | if (st) { | |
1030 | st->last = last; | |
1031 | st->used = used; | |
1032 | st->residue = residue; | |
1033 | } | |
1034 | } | |
1035 | ||
07f2211e | 1036 | #ifdef CONFIG_DMA_ENGINE |
4a43f394 JM |
1037 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
1038 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
07f2211e | 1039 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
c50331e8 | 1040 | void dma_issue_pending_all(void); |
a53e28da LPC |
1041 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
1042 | dma_filter_fn fn, void *fn_param); | |
bef29ec5 | 1043 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
8f33d527 | 1044 | void dma_release_channel(struct dma_chan *chan); |
07f2211e | 1045 | #else |
4a43f394 JM |
1046 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) |
1047 | { | |
1048 | return NULL; | |
1049 | } | |
1050 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1051 | { | |
adfedd9a | 1052 | return DMA_COMPLETE; |
4a43f394 | 1053 | } |
07f2211e DW |
1054 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1055 | { | |
adfedd9a | 1056 | return DMA_COMPLETE; |
07f2211e | 1057 | } |
c50331e8 DW |
1058 | static inline void dma_issue_pending_all(void) |
1059 | { | |
8f33d527 | 1060 | } |
a53e28da | 1061 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
8f33d527 GL |
1062 | dma_filter_fn fn, void *fn_param) |
1063 | { | |
1064 | return NULL; | |
1065 | } | |
9a6cecc8 | 1066 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 1067 | const char *name) |
9a6cecc8 | 1068 | { |
d18d5f59 | 1069 | return NULL; |
9a6cecc8 | 1070 | } |
8f33d527 GL |
1071 | static inline void dma_release_channel(struct dma_chan *chan) |
1072 | { | |
c50331e8 | 1073 | } |
07f2211e | 1074 | #endif |
c13c8260 CL |
1075 | |
1076 | /* --- DMA device --- */ | |
1077 | ||
1078 | int dma_async_device_register(struct dma_device *device); | |
1079 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 1080 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
7bb587f4 | 1081 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
a2bd1140 | 1082 | struct dma_chan *net_dma_find_channel(void); |
59b5ec21 | 1083 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
864ef69b MP |
1084 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
1085 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1086 | ||
1087 | static inline struct dma_chan | |
a53e28da LPC |
1088 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, |
1089 | dma_filter_fn fn, void *fn_param, | |
1090 | struct device *dev, char *name) | |
864ef69b MP |
1091 | { |
1092 | struct dma_chan *chan; | |
1093 | ||
1094 | chan = dma_request_slave_channel(dev, name); | |
1095 | if (chan) | |
1096 | return chan; | |
1097 | ||
1098 | return __dma_request_channel(mask, fn, fn_param); | |
1099 | } | |
c13c8260 | 1100 | |
de5506e1 CL |
1101 | /* --- Helper iov-locking functions --- */ |
1102 | ||
1103 | struct dma_page_list { | |
b2ddb901 | 1104 | char __user *base_address; |
de5506e1 CL |
1105 | int nr_pages; |
1106 | struct page **pages; | |
1107 | }; | |
1108 | ||
1109 | struct dma_pinned_list { | |
1110 | int nr_iovecs; | |
1111 | struct dma_page_list page_list[0]; | |
1112 | }; | |
1113 | ||
1114 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
1115 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
1116 | ||
1117 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1118 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
1119 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1120 | struct dma_pinned_list *pinned_list, struct page *page, | |
1121 | unsigned int offset, size_t len); | |
1122 | ||
c13c8260 | 1123 | #endif /* DMAENGINE_H */ |