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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
7405f74b | 26 | #include <linux/dma-mapping.h> |
c13c8260 | 27 | |
c13c8260 | 28 | /** |
fe4ada2d | 29 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
30 | * |
31 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
32 | */ | |
33 | typedef s32 dma_cookie_t; | |
76bd061f SM |
34 | #define DMA_MIN_COOKIE 1 |
35 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 CL |
36 | |
37 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
38 | ||
39 | /** | |
40 | * enum dma_status - DMA transaction status | |
41 | * @DMA_SUCCESS: transaction completed successfully | |
42 | * @DMA_IN_PROGRESS: transaction not yet processed | |
07934481 | 43 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
44 | * @DMA_ERROR: transaction failed |
45 | */ | |
46 | enum dma_status { | |
47 | DMA_SUCCESS, | |
48 | DMA_IN_PROGRESS, | |
07934481 | 49 | DMA_PAUSED, |
c13c8260 CL |
50 | DMA_ERROR, |
51 | }; | |
52 | ||
7405f74b DW |
53 | /** |
54 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
55 | * |
56 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
57 | * automatically set as dma devices are registered. | |
7405f74b DW |
58 | */ |
59 | enum dma_transaction_type { | |
60 | DMA_MEMCPY, | |
61 | DMA_XOR, | |
b2f46fd8 | 62 | DMA_PQ, |
099f53cb DW |
63 | DMA_XOR_VAL, |
64 | DMA_PQ_VAL, | |
7405f74b | 65 | DMA_MEMSET, |
7405f74b | 66 | DMA_INTERRUPT, |
59b5ec21 | 67 | DMA_PRIVATE, |
138f4c35 | 68 | DMA_ASYNC_TX, |
dc0ee643 | 69 | DMA_SLAVE, |
7405f74b DW |
70 | }; |
71 | ||
72 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
73 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
74 | ||
7405f74b | 75 | |
d4c56f97 | 76 | /** |
636bdeaa | 77 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 78 | * control completion, and communicate status. |
d4c56f97 | 79 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 80 | * this transaction |
a88f6667 | 81 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
82 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
83 | * chains | |
e1d181ef DW |
84 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
85 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
4f005dbe MS |
86 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
87 | * (if not set, do the source dma-unmapping as page) | |
88 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single | |
89 | * (if not set, do the destination dma-unmapping as page) | |
b2f46fd8 DW |
90 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
91 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
92 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
93 | * sources that were the result of a previous operation, in the case of a PQ | |
94 | * operation it continues the calculation with new sources | |
0403e382 DW |
95 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
96 | * on the result of this operation | |
d4c56f97 | 97 | */ |
636bdeaa | 98 | enum dma_ctrl_flags { |
d4c56f97 | 99 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 100 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
101 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
102 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
4f005dbe MS |
103 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
104 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), | |
f9dd2134 DW |
105 | DMA_PREP_PQ_DISABLE_P = (1 << 6), |
106 | DMA_PREP_PQ_DISABLE_Q = (1 << 7), | |
107 | DMA_PREP_CONTINUE = (1 << 8), | |
0403e382 | 108 | DMA_PREP_FENCE = (1 << 9), |
d4c56f97 DW |
109 | }; |
110 | ||
c3635c78 LW |
111 | /** |
112 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised | |
113 | * on a running channel. | |
114 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers | |
115 | * @DMA_PAUSE: pause ongoing transfers | |
116 | * @DMA_RESUME: resume paused transfer | |
117 | */ | |
118 | enum dma_ctrl_cmd { | |
119 | DMA_TERMINATE_ALL, | |
120 | DMA_PAUSE, | |
121 | DMA_RESUME, | |
122 | }; | |
123 | ||
ad283ea4 DW |
124 | /** |
125 | * enum sum_check_bits - bit position of pq_check_flags | |
126 | */ | |
127 | enum sum_check_bits { | |
128 | SUM_CHECK_P = 0, | |
129 | SUM_CHECK_Q = 1, | |
130 | }; | |
131 | ||
132 | /** | |
133 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
134 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
135 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
136 | */ | |
137 | enum sum_check_flags { | |
138 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
139 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
140 | }; | |
141 | ||
142 | ||
7405f74b DW |
143 | /** |
144 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
145 | * See linux/cpumask.h | |
146 | */ | |
147 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
148 | ||
c13c8260 CL |
149 | /** |
150 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
151 | * @memcpy_count: transaction counter |
152 | * @bytes_transferred: byte counter | |
153 | */ | |
154 | ||
155 | struct dma_chan_percpu { | |
c13c8260 CL |
156 | /* stats */ |
157 | unsigned long memcpy_count; | |
158 | unsigned long bytes_transferred; | |
159 | }; | |
160 | ||
161 | /** | |
162 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 163 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 164 | * @cookie: last cookie value returned to client |
fe4ada2d | 165 | * @chan_id: channel ID for sysfs |
41d5e59c | 166 | * @dev: class device for sysfs |
c13c8260 CL |
167 | * @device_node: used to add this to the device chan list |
168 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 169 | * @client-count: how many clients are using this channel |
bec08513 | 170 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 171 | * @private: private data for certain client-channel associations |
c13c8260 CL |
172 | */ |
173 | struct dma_chan { | |
c13c8260 CL |
174 | struct dma_device *device; |
175 | dma_cookie_t cookie; | |
176 | ||
177 | /* sysfs */ | |
178 | int chan_id; | |
41d5e59c | 179 | struct dma_chan_dev *dev; |
c13c8260 | 180 | |
c13c8260 | 181 | struct list_head device_node; |
a29d8b8e | 182 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 183 | int client_count; |
bec08513 | 184 | int table_count; |
287d8592 | 185 | void *private; |
c13c8260 CL |
186 | }; |
187 | ||
41d5e59c DW |
188 | /** |
189 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
190 | * @chan - driver channel device | |
191 | * @device - sysfs device | |
864498aa DW |
192 | * @dev_id - parent dma_device dev_id |
193 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
194 | */ |
195 | struct dma_chan_dev { | |
196 | struct dma_chan *chan; | |
197 | struct device device; | |
864498aa DW |
198 | int dev_id; |
199 | atomic_t *idr_ref; | |
41d5e59c DW |
200 | }; |
201 | ||
202 | static inline const char *dma_chan_name(struct dma_chan *chan) | |
203 | { | |
204 | return dev_name(&chan->dev->device); | |
205 | } | |
d379b01e | 206 | |
c13c8260 CL |
207 | void dma_chan_cleanup(struct kref *kref); |
208 | ||
59b5ec21 DW |
209 | /** |
210 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
211 | * @chan: channel to be reviewed | |
212 | * @filter_param: opaque parameter passed through dma_request_channel | |
213 | * | |
214 | * When this optional parameter is specified in a call to dma_request_channel a | |
215 | * suitable channel is passed to this routine for further dispositioning before | |
216 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
217 | * satisfies the given capability mask. It returns 'true' to indicate that the |
218 | * channel is suitable. | |
59b5ec21 | 219 | */ |
7dd60251 | 220 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 221 | |
7405f74b DW |
222 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
223 | /** | |
224 | * struct dma_async_tx_descriptor - async transaction descriptor | |
225 | * ---dma generic offload fields--- | |
226 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
227 | * this tx is sitting on a dependency list | |
636bdeaa DW |
228 | * @flags: flags to augment operation preparation, control completion, and |
229 | * communicate status | |
7405f74b | 230 | * @phys: physical address of the descriptor |
7405f74b DW |
231 | * @chan: target channel for this operation |
232 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
233 | * @callback: routine to call after this operation is complete |
234 | * @callback_param: general parameter to pass to the callback routine | |
235 | * ---async_tx api specific fields--- | |
19242d72 | 236 | * @next: at completion submit this descriptor |
7405f74b | 237 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 238 | * @lock: protect the parent and next pointers |
7405f74b DW |
239 | */ |
240 | struct dma_async_tx_descriptor { | |
241 | dma_cookie_t cookie; | |
636bdeaa | 242 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 243 | dma_addr_t phys; |
7405f74b DW |
244 | struct dma_chan *chan; |
245 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
246 | dma_async_tx_callback callback; |
247 | void *callback_param; | |
caa20d97 | 248 | #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
19242d72 | 249 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
250 | struct dma_async_tx_descriptor *parent; |
251 | spinlock_t lock; | |
caa20d97 | 252 | #endif |
7405f74b DW |
253 | }; |
254 | ||
caa20d97 DW |
255 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
256 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
257 | { | |
258 | } | |
259 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
260 | { | |
261 | } | |
262 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
263 | { | |
264 | BUG(); | |
265 | } | |
266 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
267 | { | |
268 | } | |
269 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
270 | { | |
271 | } | |
272 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
273 | { | |
274 | return NULL; | |
275 | } | |
276 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
277 | { | |
278 | return NULL; | |
279 | } | |
280 | ||
281 | #else | |
282 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
283 | { | |
284 | spin_lock_bh(&txd->lock); | |
285 | } | |
286 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
287 | { | |
288 | spin_unlock_bh(&txd->lock); | |
289 | } | |
290 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
291 | { | |
292 | txd->next = next; | |
293 | next->parent = txd; | |
294 | } | |
295 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
296 | { | |
297 | txd->parent = NULL; | |
298 | } | |
299 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
300 | { | |
301 | txd->next = NULL; | |
302 | } | |
303 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
304 | { | |
305 | return txd->parent; | |
306 | } | |
307 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
308 | { | |
309 | return txd->next; | |
310 | } | |
311 | #endif | |
312 | ||
07934481 LW |
313 | /** |
314 | * struct dma_tx_state - filled in to report the status of | |
315 | * a transfer. | |
316 | * @last: last completed DMA cookie | |
317 | * @used: last issued DMA cookie (i.e. the one in progress) | |
318 | * @residue: the remaining number of bytes left to transmit | |
319 | * on the selected transfer for states DMA_IN_PROGRESS and | |
320 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
321 | */ | |
322 | struct dma_tx_state { | |
323 | dma_cookie_t last; | |
324 | dma_cookie_t used; | |
325 | u32 residue; | |
326 | }; | |
327 | ||
c13c8260 CL |
328 | /** |
329 | * struct dma_device - info on the entity supplying DMA services | |
330 | * @chancnt: how many DMA channels are supported | |
0f571515 | 331 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
332 | * @channels: the list of struct dma_chan |
333 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
334 | * @cap_mask: one or more dma_capability flags |
335 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 336 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
337 | * @copy_align: alignment shift for memcpy operations |
338 | * @xor_align: alignment shift for xor operations | |
339 | * @pq_align: alignment shift for pq operations | |
340 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 341 | * @dev_id: unique device ID |
7405f74b | 342 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
343 | * @device_alloc_chan_resources: allocate resources and return the |
344 | * number of allocated descriptors | |
345 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
346 | * @device_prep_dma_memcpy: prepares a memcpy operation |
347 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 348 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
349 | * @device_prep_dma_pq: prepares a pq operation |
350 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b DW |
351 | * @device_prep_dma_memset: prepares a memset operation |
352 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 | 353 | * @device_prep_slave_sg: prepares a slave dma operation |
c3635c78 LW |
354 | * @device_control: manipulate all pending operations on a channel, returns |
355 | * zero or error code | |
07934481 LW |
356 | * @device_tx_status: poll for transaction completion, the optional |
357 | * txstate parameter can be supplied with a pointer to get a | |
358 | * struct with auxilary transfer status information, otherwise the call | |
359 | * will just return a simple status code | |
7405f74b | 360 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
361 | */ |
362 | struct dma_device { | |
363 | ||
364 | unsigned int chancnt; | |
0f571515 | 365 | unsigned int privatecnt; |
c13c8260 CL |
366 | struct list_head channels; |
367 | struct list_head global_node; | |
7405f74b | 368 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
369 | unsigned short max_xor; |
370 | unsigned short max_pq; | |
83544ae9 DW |
371 | u8 copy_align; |
372 | u8 xor_align; | |
373 | u8 pq_align; | |
374 | u8 fill_align; | |
b2f46fd8 | 375 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 376 | |
c13c8260 | 377 | int dev_id; |
7405f74b | 378 | struct device *dev; |
c13c8260 | 379 | |
aa1e6f1a | 380 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 381 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
382 | |
383 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 384 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 385 | size_t len, unsigned long flags); |
7405f74b | 386 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 387 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 388 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 389 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 390 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 391 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
392 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
393 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
394 | unsigned int src_cnt, const unsigned char *scf, | |
395 | size_t len, unsigned long flags); | |
396 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
397 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
398 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
399 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 400 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 401 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 402 | unsigned long flags); |
7405f74b | 403 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 404 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 405 | |
dc0ee643 HS |
406 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
407 | struct dma_chan *chan, struct scatterlist *sgl, | |
408 | unsigned int sg_len, enum dma_data_direction direction, | |
409 | unsigned long flags); | |
05827630 LW |
410 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
411 | unsigned long arg); | |
dc0ee643 | 412 | |
07934481 LW |
413 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
414 | dma_cookie_t cookie, | |
415 | struct dma_tx_state *txstate); | |
7405f74b | 416 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
417 | }; |
418 | ||
83544ae9 DW |
419 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
420 | { | |
421 | size_t mask; | |
422 | ||
423 | if (!align) | |
424 | return true; | |
425 | mask = (1 << align) - 1; | |
426 | if (mask & (off1 | off2 | len)) | |
427 | return false; | |
428 | return true; | |
429 | } | |
430 | ||
431 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
432 | size_t off2, size_t len) | |
433 | { | |
434 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
435 | } | |
436 | ||
437 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
438 | size_t off2, size_t len) | |
439 | { | |
440 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
441 | } | |
442 | ||
443 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
444 | size_t off2, size_t len) | |
445 | { | |
446 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
447 | } | |
448 | ||
449 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
450 | size_t off2, size_t len) | |
451 | { | |
452 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
453 | } | |
454 | ||
b2f46fd8 DW |
455 | static inline void |
456 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
457 | { | |
458 | dma->max_pq = maxpq; | |
459 | if (has_pq_continue) | |
460 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
461 | } | |
462 | ||
463 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
464 | { | |
465 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
466 | } | |
467 | ||
468 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
469 | { | |
470 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
471 | ||
472 | return (flags & mask) == mask; | |
473 | } | |
474 | ||
475 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
476 | { | |
477 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
478 | } | |
479 | ||
480 | static unsigned short dma_dev_to_maxpq(struct dma_device *dma) | |
481 | { | |
482 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
483 | } | |
484 | ||
485 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
486 | * @dma - dma device with PQ capability | |
487 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
488 | * | |
489 | * When an engine does not support native continuation we need 3 extra | |
490 | * source slots to reuse P and Q with the following coefficients: | |
491 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
492 | * 2/ {01} * Q : use Q to continue Q' calculation | |
493 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
494 | * | |
495 | * In the case where P is disabled we only need 1 extra source: | |
496 | * 1/ {01} * Q : use Q to continue Q' calculation | |
497 | */ | |
498 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
499 | { | |
500 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
501 | return dma_dev_to_maxpq(dma); | |
502 | else if (dmaf_p_disabled_continue(flags)) | |
503 | return dma_dev_to_maxpq(dma) - 1; | |
504 | else if (dmaf_continue(flags)) | |
505 | return dma_dev_to_maxpq(dma) - 3; | |
506 | BUG(); | |
507 | } | |
508 | ||
c13c8260 CL |
509 | /* --- public DMA engine API --- */ |
510 | ||
649274d9 | 511 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
512 | void dmaengine_get(void); |
513 | void dmaengine_put(void); | |
649274d9 DW |
514 | #else |
515 | static inline void dmaengine_get(void) | |
516 | { | |
517 | } | |
518 | static inline void dmaengine_put(void) | |
519 | { | |
520 | } | |
521 | #endif | |
522 | ||
b4bd07c2 DM |
523 | #ifdef CONFIG_NET_DMA |
524 | #define net_dmaengine_get() dmaengine_get() | |
525 | #define net_dmaengine_put() dmaengine_put() | |
526 | #else | |
527 | static inline void net_dmaengine_get(void) | |
528 | { | |
529 | } | |
530 | static inline void net_dmaengine_put(void) | |
531 | { | |
532 | } | |
533 | #endif | |
534 | ||
729b5d1b DW |
535 | #ifdef CONFIG_ASYNC_TX_DMA |
536 | #define async_dmaengine_get() dmaengine_get() | |
537 | #define async_dmaengine_put() dmaengine_put() | |
138f4c35 DW |
538 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
539 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) | |
540 | #else | |
729b5d1b | 541 | #define async_dma_find_channel(type) dma_find_channel(type) |
138f4c35 | 542 | #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
543 | #else |
544 | static inline void async_dmaengine_get(void) | |
545 | { | |
546 | } | |
547 | static inline void async_dmaengine_put(void) | |
548 | { | |
549 | } | |
550 | static inline struct dma_chan * | |
551 | async_dma_find_channel(enum dma_transaction_type type) | |
552 | { | |
553 | return NULL; | |
554 | } | |
138f4c35 | 555 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 556 | |
7405f74b DW |
557 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
558 | void *dest, void *src, size_t len); | |
559 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
560 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
561 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
562 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
563 | unsigned int src_off, size_t len); | |
564 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
565 | struct dma_chan *chan); | |
c13c8260 | 566 | |
0839875e | 567 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 568 | { |
636bdeaa DW |
569 | tx->flags |= DMA_CTRL_ACK; |
570 | } | |
571 | ||
ef560682 GL |
572 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
573 | { | |
574 | tx->flags &= ~DMA_CTRL_ACK; | |
575 | } | |
576 | ||
0839875e | 577 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 578 | { |
0839875e | 579 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
580 | } |
581 | ||
7405f74b DW |
582 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
583 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 584 | { |
7405f74b DW |
585 | return min_t(int, DMA_TX_TYPE_END, |
586 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
587 | } | |
c13c8260 | 588 | |
7405f74b DW |
589 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
590 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
591 | { | |
592 | return min_t(int, DMA_TX_TYPE_END, | |
593 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
594 | } |
595 | ||
7405f74b DW |
596 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
597 | static inline void | |
598 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 599 | { |
7405f74b DW |
600 | set_bit(tx_type, dstp->bits); |
601 | } | |
c13c8260 | 602 | |
0f571515 AN |
603 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
604 | static inline void | |
605 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
606 | { | |
607 | clear_bit(tx_type, dstp->bits); | |
608 | } | |
609 | ||
33df8ca0 DW |
610 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
611 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
612 | { | |
613 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
614 | } | |
615 | ||
7405f74b DW |
616 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
617 | static inline int | |
618 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
619 | { | |
620 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
621 | } |
622 | ||
7405f74b DW |
623 | #define for_each_dma_cap_mask(cap, mask) \ |
624 | for ((cap) = first_dma_cap(mask); \ | |
625 | (cap) < DMA_TX_TYPE_END; \ | |
626 | (cap) = next_dma_cap((cap), (mask))) | |
627 | ||
c13c8260 | 628 | /** |
7405f74b | 629 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 630 | * @chan: target DMA channel |
c13c8260 CL |
631 | * |
632 | * This allows drivers to push copies to HW in batches, | |
633 | * reducing MMIO writes where possible. | |
634 | */ | |
7405f74b | 635 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 636 | { |
ec8670f1 | 637 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
638 | } |
639 | ||
7405f74b DW |
640 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
641 | ||
c13c8260 | 642 | /** |
7405f74b | 643 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
644 | * @chan: DMA channel |
645 | * @cookie: transaction identifier to check status of | |
646 | * @last: returns last completed cookie, can be NULL | |
647 | * @used: returns last issued cookie, can be NULL | |
648 | * | |
649 | * If @last and @used are passed in, upon return they reflect the driver | |
650 | * internal state and can be used with dma_async_is_complete() to check | |
651 | * the status of multiple cookies without re-checking hardware state. | |
652 | */ | |
7405f74b | 653 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
654 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
655 | { | |
07934481 LW |
656 | struct dma_tx_state state; |
657 | enum dma_status status; | |
658 | ||
659 | status = chan->device->device_tx_status(chan, cookie, &state); | |
660 | if (last) | |
661 | *last = state.last; | |
662 | if (used) | |
663 | *used = state.used; | |
664 | return status; | |
c13c8260 CL |
665 | } |
666 | ||
7405f74b DW |
667 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
668 | dma_async_is_tx_complete(chan, cookie, last, used) | |
669 | ||
c13c8260 CL |
670 | /** |
671 | * dma_async_is_complete - test a cookie against chan state | |
672 | * @cookie: transaction identifier to test status of | |
673 | * @last_complete: last know completed transaction | |
674 | * @last_used: last cookie value handed out | |
675 | * | |
676 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 677 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
678 | */ |
679 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
680 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
681 | { | |
682 | if (last_complete <= last_used) { | |
683 | if ((cookie <= last_complete) || (cookie > last_used)) | |
684 | return DMA_SUCCESS; | |
685 | } else { | |
686 | if ((cookie <= last_complete) && (cookie > last_used)) | |
687 | return DMA_SUCCESS; | |
688 | } | |
689 | return DMA_IN_PROGRESS; | |
690 | } | |
691 | ||
bca34692 DW |
692 | static inline void |
693 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
694 | { | |
695 | if (st) { | |
696 | st->last = last; | |
697 | st->used = used; | |
698 | st->residue = residue; | |
699 | } | |
700 | } | |
701 | ||
7405f74b | 702 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
703 | #ifdef CONFIG_DMA_ENGINE |
704 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 705 | void dma_issue_pending_all(void); |
07f2211e DW |
706 | #else |
707 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
708 | { | |
709 | return DMA_SUCCESS; | |
710 | } | |
c50331e8 DW |
711 | static inline void dma_issue_pending_all(void) |
712 | { | |
713 | do { } while (0); | |
714 | } | |
07f2211e | 715 | #endif |
c13c8260 CL |
716 | |
717 | /* --- DMA device --- */ | |
718 | ||
719 | int dma_async_device_register(struct dma_device *device); | |
720 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 721 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 722 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
59b5ec21 DW |
723 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
724 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
725 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 726 | |
de5506e1 CL |
727 | /* --- Helper iov-locking functions --- */ |
728 | ||
729 | struct dma_page_list { | |
b2ddb901 | 730 | char __user *base_address; |
de5506e1 CL |
731 | int nr_pages; |
732 | struct page **pages; | |
733 | }; | |
734 | ||
735 | struct dma_pinned_list { | |
736 | int nr_iovecs; | |
737 | struct dma_page_list page_list[0]; | |
738 | }; | |
739 | ||
740 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
741 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
742 | ||
743 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
744 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
745 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
746 | struct dma_pinned_list *pinned_list, struct page *page, | |
747 | unsigned int offset, size_t len); | |
748 | ||
c13c8260 | 749 | #endif /* DMAENGINE_H */ |