]>
Commit | Line | Data |
---|---|---|
9ab65aff | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
c13c8260 CL |
2 | /* |
3 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
c13c8260 | 4 | */ |
d2ebfb33 RKAL |
5 | #ifndef LINUX_DMAENGINE_H |
6 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 7 | |
c13c8260 | 8 | #include <linux/device.h> |
0ad7c000 | 9 | #include <linux/err.h> |
c13c8260 | 10 | #include <linux/uio.h> |
187f1882 | 11 | #include <linux/bug.h> |
90b44f8f | 12 | #include <linux/scatterlist.h> |
a8efa9d6 | 13 | #include <linux/bitmap.h> |
dcc043dc | 14 | #include <linux/types.h> |
a8efa9d6 | 15 | #include <asm/page.h> |
b7f080cf | 16 | |
c13c8260 | 17 | /** |
fe4ada2d | 18 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
19 | * |
20 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
21 | */ | |
22 | typedef s32 dma_cookie_t; | |
76bd061f | 23 | #define DMA_MIN_COOKIE 1 |
c13c8260 | 24 | |
71ea1483 DC |
25 | static inline int dma_submit_error(dma_cookie_t cookie) |
26 | { | |
27 | return cookie < 0 ? cookie : 0; | |
28 | } | |
c13c8260 CL |
29 | |
30 | /** | |
31 | * enum dma_status - DMA transaction status | |
adfedd9a | 32 | * @DMA_COMPLETE: transaction completed |
c13c8260 | 33 | * @DMA_IN_PROGRESS: transaction not yet processed |
07934481 | 34 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
35 | * @DMA_ERROR: transaction failed |
36 | */ | |
37 | enum dma_status { | |
7db5f727 | 38 | DMA_COMPLETE, |
c13c8260 | 39 | DMA_IN_PROGRESS, |
07934481 | 40 | DMA_PAUSED, |
c13c8260 CL |
41 | DMA_ERROR, |
42 | }; | |
43 | ||
7405f74b DW |
44 | /** |
45 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
46 | * |
47 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
48 | * automatically set as dma devices are registered. | |
7405f74b DW |
49 | */ |
50 | enum dma_transaction_type { | |
51 | DMA_MEMCPY, | |
52 | DMA_XOR, | |
b2f46fd8 | 53 | DMA_PQ, |
099f53cb DW |
54 | DMA_XOR_VAL, |
55 | DMA_PQ_VAL, | |
4983a501 | 56 | DMA_MEMSET, |
50c7cd2b | 57 | DMA_MEMSET_SG, |
7405f74b | 58 | DMA_INTERRUPT, |
59b5ec21 | 59 | DMA_PRIVATE, |
138f4c35 | 60 | DMA_ASYNC_TX, |
dc0ee643 | 61 | DMA_SLAVE, |
782bc950 | 62 | DMA_CYCLIC, |
b14dab79 | 63 | DMA_INTERLEAVE, |
7405f74b | 64 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
65 | DMA_TX_TYPE_END, |
66 | }; | |
dc0ee643 | 67 | |
49920bc6 VK |
68 | /** |
69 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
70 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
71 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
72 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
73 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
74 | */ | |
75 | enum dma_transfer_direction { | |
76 | DMA_MEM_TO_MEM, | |
77 | DMA_MEM_TO_DEV, | |
78 | DMA_DEV_TO_MEM, | |
79 | DMA_DEV_TO_DEV, | |
62268ce9 | 80 | DMA_TRANS_NONE, |
49920bc6 | 81 | }; |
7405f74b | 82 | |
b14dab79 JB |
83 | /** |
84 | * Interleaved Transfer Request | |
85 | * ---------------------------- | |
86 | * A chunk is collection of contiguous bytes to be transfered. | |
87 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
88 | * ICGs may or maynot change between chunks. | |
89 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
90 | * that when repeated an integral number of times, specifies the transfer. | |
91 | * A transfer template is specification of a Frame, the number of times | |
92 | * it is to be repeated and other per-transfer attributes. | |
93 | * | |
94 | * Practically, a client driver would have ready a template for each | |
95 | * type of transfer it is going to need during its lifetime and | |
96 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
97 | * | |
98 | * | |
99 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
100 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
101 | * | |
102 | * == Chunk size | |
103 | * ... ICG | |
104 | */ | |
105 | ||
106 | /** | |
107 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
108 | * @size: Number of bytes to read from source. | |
109 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
110 | * @icg: Number of bytes to jump after last src/dst address of this | |
111 | * chunk and before first src/dst address for next chunk. | |
112 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
113 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
e1031dc1 MR |
114 | * @dst_icg: Number of bytes to jump after last dst address of this |
115 | * chunk and before the first dst address for next chunk. | |
116 | * Ignored if dst_inc is true and dst_sgl is false. | |
117 | * @src_icg: Number of bytes to jump after last src address of this | |
118 | * chunk and before the first src address for next chunk. | |
119 | * Ignored if src_inc is true and src_sgl is false. | |
b14dab79 JB |
120 | */ |
121 | struct data_chunk { | |
122 | size_t size; | |
123 | size_t icg; | |
e1031dc1 MR |
124 | size_t dst_icg; |
125 | size_t src_icg; | |
b14dab79 JB |
126 | }; |
127 | ||
128 | /** | |
129 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
130 | * and attributes. | |
131 | * @src_start: Bus address of source for the first chunk. | |
132 | * @dst_start: Bus address of destination for the first chunk. | |
133 | * @dir: Specifies the type of Source and Destination. | |
134 | * @src_inc: If the source address increments after reading from it. | |
135 | * @dst_inc: If the destination address increments after writing to it. | |
136 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
137 | * Otherwise, source is read contiguously (icg ignored). | |
138 | * Ignored if src_inc is false. | |
139 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
140 | * Otherwise, destination is filled contiguously (icg ignored). | |
141 | * Ignored if dst_inc is false. | |
142 | * @numf: Number of frames in this template. | |
143 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
144 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
145 | */ | |
146 | struct dma_interleaved_template { | |
147 | dma_addr_t src_start; | |
148 | dma_addr_t dst_start; | |
149 | enum dma_transfer_direction dir; | |
150 | bool src_inc; | |
151 | bool dst_inc; | |
152 | bool src_sgl; | |
153 | bool dst_sgl; | |
154 | size_t numf; | |
155 | size_t frame_size; | |
156 | struct data_chunk sgl[0]; | |
157 | }; | |
158 | ||
d4c56f97 | 159 | /** |
636bdeaa | 160 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 161 | * control completion, and communicate status. |
d4c56f97 | 162 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 163 | * this transaction |
a88f6667 | 164 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
165 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
166 | * chains | |
b2f46fd8 DW |
167 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
168 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
169 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
170 | * sources that were the result of a previous operation, in the case of a PQ | |
171 | * operation it continues the calculation with new sources | |
0403e382 DW |
172 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
173 | * on the result of this operation | |
27242021 VK |
174 | * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till |
175 | * cleared or freed | |
3e00ab4a AS |
176 | * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command |
177 | * data and the descriptor should be in different format from normal | |
178 | * data descriptors. | |
d4c56f97 | 179 | */ |
636bdeaa | 180 | enum dma_ctrl_flags { |
d4c56f97 | 181 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 182 | DMA_CTRL_ACK = (1 << 1), |
0776ae7b BZ |
183 | DMA_PREP_PQ_DISABLE_P = (1 << 2), |
184 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
185 | DMA_PREP_CONTINUE = (1 << 4), | |
186 | DMA_PREP_FENCE = (1 << 5), | |
27242021 | 187 | DMA_CTRL_REUSE = (1 << 6), |
3e00ab4a | 188 | DMA_PREP_CMD = (1 << 7), |
d4c56f97 DW |
189 | }; |
190 | ||
ad283ea4 DW |
191 | /** |
192 | * enum sum_check_bits - bit position of pq_check_flags | |
193 | */ | |
194 | enum sum_check_bits { | |
195 | SUM_CHECK_P = 0, | |
196 | SUM_CHECK_Q = 1, | |
197 | }; | |
198 | ||
199 | /** | |
200 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
201 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
202 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
203 | */ | |
204 | enum sum_check_flags { | |
205 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
206 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
207 | }; | |
208 | ||
209 | ||
7405f74b DW |
210 | /** |
211 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
212 | * See linux/cpumask.h | |
213 | */ | |
214 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
215 | ||
c13c8260 CL |
216 | /** |
217 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
218 | * @memcpy_count: transaction counter |
219 | * @bytes_transferred: byte counter | |
220 | */ | |
221 | ||
4db8fd32 PU |
222 | /** |
223 | * enum dma_desc_metadata_mode - per descriptor metadata mode types supported | |
224 | * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the | |
225 | * client driver and it is attached (via the dmaengine_desc_attach_metadata() | |
226 | * helper) to the descriptor. | |
227 | * | |
228 | * Client drivers interested to use this mode can follow: | |
229 | * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: | |
230 | * 1. prepare the descriptor (dmaengine_prep_*) | |
231 | * construct the metadata in the client's buffer | |
232 | * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the | |
233 | * descriptor | |
234 | * 3. submit the transfer | |
235 | * - DMA_DEV_TO_MEM: | |
236 | * 1. prepare the descriptor (dmaengine_prep_*) | |
237 | * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the | |
238 | * descriptor | |
239 | * 3. submit the transfer | |
240 | * 4. when the transfer is completed, the metadata should be available in the | |
241 | * attached buffer | |
242 | * | |
243 | * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA | |
244 | * driver. The client driver can ask for the pointer, maximum size and the | |
245 | * currently used size of the metadata and can directly update or read it. | |
246 | * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is | |
247 | * provided as helper functions. | |
248 | * | |
249 | * Note: the metadata area for the descriptor is no longer valid after the | |
250 | * transfer has been completed (valid up to the point when the completion | |
251 | * callback returns if used). | |
252 | * | |
253 | * Client drivers interested to use this mode can follow: | |
254 | * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: | |
255 | * 1. prepare the descriptor (dmaengine_prep_*) | |
256 | * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's | |
257 | * metadata area | |
258 | * 3. update the metadata at the pointer | |
259 | * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount | |
260 | * of data the client has placed into the metadata buffer | |
261 | * 5. submit the transfer | |
262 | * - DMA_DEV_TO_MEM: | |
263 | * 1. prepare the descriptor (dmaengine_prep_*) | |
264 | * 2. submit the transfer | |
265 | * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the | |
266 | * pointer to the engine's metadata area | |
267 | * 4. Read out the metadata from the pointer | |
268 | * | |
269 | * Note: the two mode is not compatible and clients must use one mode for a | |
270 | * descriptor. | |
271 | */ | |
272 | enum dma_desc_metadata_mode { | |
273 | DESC_METADATA_NONE = 0, | |
274 | DESC_METADATA_CLIENT = BIT(0), | |
275 | DESC_METADATA_ENGINE = BIT(1), | |
276 | }; | |
277 | ||
c13c8260 | 278 | struct dma_chan_percpu { |
c13c8260 CL |
279 | /* stats */ |
280 | unsigned long memcpy_count; | |
281 | unsigned long bytes_transferred; | |
282 | }; | |
283 | ||
56f13c0d PU |
284 | /** |
285 | * struct dma_router - DMA router structure | |
286 | * @dev: pointer to the DMA router device | |
287 | * @route_free: function to be called when the route can be disconnected | |
288 | */ | |
289 | struct dma_router { | |
290 | struct device *dev; | |
291 | void (*route_free)(struct device *dev, void *route_data); | |
292 | }; | |
293 | ||
c13c8260 CL |
294 | /** |
295 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 296 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
71723a96 | 297 | * @slave: ptr to the device using this channel |
c13c8260 | 298 | * @cookie: last cookie value returned to client |
4d4e58de | 299 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 300 | * @chan_id: channel ID for sysfs |
41d5e59c | 301 | * @dev: class device for sysfs |
71723a96 | 302 | * @name: backlink name for sysfs |
c13c8260 CL |
303 | * @device_node: used to add this to the device chan list |
304 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
868d2ee2 | 305 | * @client_count: how many clients are using this channel |
bec08513 | 306 | * @table_count: number of appearances in the mem-to-mem allocation table |
56f13c0d PU |
307 | * @router: pointer to the DMA router structure |
308 | * @route_data: channel specific data for the router | |
287d8592 | 309 | * @private: private data for certain client-channel associations |
c13c8260 CL |
310 | */ |
311 | struct dma_chan { | |
c13c8260 | 312 | struct dma_device *device; |
71723a96 | 313 | struct device *slave; |
c13c8260 | 314 | dma_cookie_t cookie; |
4d4e58de | 315 | dma_cookie_t completed_cookie; |
c13c8260 CL |
316 | |
317 | /* sysfs */ | |
318 | int chan_id; | |
41d5e59c | 319 | struct dma_chan_dev *dev; |
71723a96 | 320 | const char *name; |
c13c8260 | 321 | |
c13c8260 | 322 | struct list_head device_node; |
a29d8b8e | 323 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 324 | int client_count; |
bec08513 | 325 | int table_count; |
56f13c0d PU |
326 | |
327 | /* DMA router */ | |
328 | struct dma_router *router; | |
329 | void *route_data; | |
330 | ||
287d8592 | 331 | void *private; |
c13c8260 CL |
332 | }; |
333 | ||
41d5e59c DW |
334 | /** |
335 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
868d2ee2 VK |
336 | * @chan: driver channel device |
337 | * @device: sysfs device | |
338 | * @dev_id: parent dma_device dev_id | |
339 | * @idr_ref: reference count to gate release of dma_device dev_id | |
41d5e59c DW |
340 | */ |
341 | struct dma_chan_dev { | |
342 | struct dma_chan *chan; | |
343 | struct device device; | |
864498aa DW |
344 | int dev_id; |
345 | atomic_t *idr_ref; | |
41d5e59c DW |
346 | }; |
347 | ||
c156d0a5 | 348 | /** |
ba730340 | 349 | * enum dma_slave_buswidth - defines bus width of the DMA slave |
c156d0a5 LW |
350 | * device, source or target buses |
351 | */ | |
352 | enum dma_slave_buswidth { | |
353 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
354 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
355 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
93c6ee94 | 356 | DMA_SLAVE_BUSWIDTH_3_BYTES = 3, |
c156d0a5 LW |
357 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, |
358 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
534a7298 LP |
359 | DMA_SLAVE_BUSWIDTH_16_BYTES = 16, |
360 | DMA_SLAVE_BUSWIDTH_32_BYTES = 32, | |
361 | DMA_SLAVE_BUSWIDTH_64_BYTES = 64, | |
c156d0a5 LW |
362 | }; |
363 | ||
364 | /** | |
365 | * struct dma_slave_config - dma slave channel runtime config | |
366 | * @direction: whether the data shall go in or out on this slave | |
397321f4 | 367 | * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are |
d9ff958b LP |
368 | * legal values. DEPRECATED, drivers should use the direction argument |
369 | * to the device_prep_slave_sg and device_prep_dma_cyclic functions or | |
370 | * the dir field in the dma_interleaved_template structure. | |
c156d0a5 LW |
371 | * @src_addr: this is the physical address where DMA slave data |
372 | * should be read (RX), if the source is memory this argument is | |
373 | * ignored. | |
374 | * @dst_addr: this is the physical address where DMA slave data | |
375 | * should be written (TX), if the source is memory this argument | |
376 | * is ignored. | |
377 | * @src_addr_width: this is the width in bytes of the source (RX) | |
378 | * register where DMA data shall be read. If the source | |
379 | * is memory this may be ignored depending on architecture. | |
3f7632e1 | 380 | * Legal values: 1, 2, 3, 4, 8, 16, 32, 64. |
c156d0a5 LW |
381 | * @dst_addr_width: same as src_addr_width but for destination |
382 | * target (TX) mutatis mutandis. | |
383 | * @src_maxburst: the maximum number of words (note: words, as in | |
384 | * units of the src_addr_width member, not bytes) that can be sent | |
385 | * in one burst to the device. Typically something like half the | |
386 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
387 | * may or may not be applicable on memory sources. | |
388 | * @dst_maxburst: same as src_maxburst but for destination target | |
389 | * mutatis mutandis. | |
54cd2558 PU |
390 | * @src_port_window_size: The length of the register area in words the data need |
391 | * to be accessed on the device side. It is only used for devices which is using | |
392 | * an area instead of a single register to receive the data. Typically the DMA | |
393 | * loops in this area in order to transfer the data. | |
394 | * @dst_port_window_size: same as src_port_window_size but for the destination | |
395 | * port. | |
dcc043dc VK |
396 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
397 | * with 'true' if peripheral should be flow controller. Direction will be | |
398 | * selected at Runtime. | |
4fd1e324 LD |
399 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
400 | * slave peripheral will have unique id as dma requester which need to be | |
401 | * pass as slave config. | |
c156d0a5 LW |
402 | * |
403 | * This struct is passed in as configuration data to a DMA engine | |
404 | * in order to set up a certain channel for DMA transport at runtime. | |
405 | * The DMA device/engine has to provide support for an additional | |
2c44ad91 MR |
406 | * callback in the dma_device structure, device_config and this struct |
407 | * will then be passed in as an argument to the function. | |
c156d0a5 | 408 | * |
7cbccb55 LPC |
409 | * The rationale for adding configuration information to this struct is as |
410 | * follows: if it is likely that more than one DMA slave controllers in | |
411 | * the world will support the configuration option, then make it generic. | |
412 | * If not: if it is fixed so that it be sent in static from the platform | |
413 | * data, then prefer to do that. | |
c156d0a5 LW |
414 | */ |
415 | struct dma_slave_config { | |
49920bc6 | 416 | enum dma_transfer_direction direction; |
95756320 VK |
417 | phys_addr_t src_addr; |
418 | phys_addr_t dst_addr; | |
c156d0a5 LW |
419 | enum dma_slave_buswidth src_addr_width; |
420 | enum dma_slave_buswidth dst_addr_width; | |
421 | u32 src_maxburst; | |
422 | u32 dst_maxburst; | |
54cd2558 PU |
423 | u32 src_port_window_size; |
424 | u32 dst_port_window_size; | |
dcc043dc | 425 | bool device_fc; |
4fd1e324 | 426 | unsigned int slave_id; |
c156d0a5 LW |
427 | }; |
428 | ||
50720563 LPC |
429 | /** |
430 | * enum dma_residue_granularity - Granularity of the reported transfer residue | |
431 | * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The | |
432 | * DMA channel is only able to tell whether a descriptor has been completed or | |
433 | * not, which means residue reporting is not supported by this channel. The | |
434 | * residue field of the dma_tx_state field will always be 0. | |
435 | * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully | |
436 | * completed segment of the transfer (For cyclic transfers this is after each | |
437 | * period). This is typically implemented by having the hardware generate an | |
438 | * interrupt after each transferred segment and then the drivers updates the | |
439 | * outstanding residue by the size of the segment. Another possibility is if | |
440 | * the hardware supports scatter-gather and the segment descriptor has a field | |
441 | * which gets set after the segment has been completed. The driver then counts | |
442 | * the number of segments without the flag set to compute the residue. | |
443 | * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred | |
444 | * burst. This is typically only supported if the hardware has a progress | |
445 | * register of some sort (E.g. a register with the current read/write address | |
446 | * or a register with the amount of bursts/beats/bytes that have been | |
447 | * transferred or still need to be transferred). | |
448 | */ | |
449 | enum dma_residue_granularity { | |
450 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
451 | DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
452 | DMA_RESIDUE_GRANULARITY_BURST = 2, | |
453 | }; | |
454 | ||
c2cbd427 SB |
455 | /** |
456 | * struct dma_slave_caps - expose capabilities of a slave channel only | |
457 | * @src_addr_widths: bit mask of src addr widths the channel supports. | |
458 | * Width is specified in bytes, e.g. for a channel supporting | |
459 | * a width of 4 the mask should have BIT(4) set. | |
460 | * @dst_addr_widths: bit mask of dst addr widths the channel supports | |
461 | * @directions: bit mask of slave directions the channel supports. | |
462 | * Since the enum dma_transfer_direction is not defined as bit flag for | |
463 | * each type, the dma controller should set BIT(<TYPE>) and same | |
464 | * should be checked by controller as well | |
6d5bbed3 | 465 | * @max_burst: max burst capability per-transfer |
d8095f94 MS |
466 | * @cmd_pause: true, if pause is supported (i.e. for reading residue or |
467 | * for resume later) | |
468 | * @cmd_resume: true, if resume is supported | |
221a27c7 | 469 | * @cmd_terminate: true, if terminate cmd is supported |
50720563 | 470 | * @residue_granularity: granularity of the reported transfer residue |
27242021 VK |
471 | * @descriptor_reuse: if a descriptor can be reused by client and |
472 | * resubmitted multiple times | |
221a27c7 VK |
473 | */ |
474 | struct dma_slave_caps { | |
475 | u32 src_addr_widths; | |
ceacbdbf | 476 | u32 dst_addr_widths; |
221a27c7 | 477 | u32 directions; |
6d5bbed3 | 478 | u32 max_burst; |
221a27c7 | 479 | bool cmd_pause; |
d8095f94 | 480 | bool cmd_resume; |
221a27c7 | 481 | bool cmd_terminate; |
50720563 | 482 | enum dma_residue_granularity residue_granularity; |
27242021 | 483 | bool descriptor_reuse; |
221a27c7 VK |
484 | }; |
485 | ||
41d5e59c DW |
486 | static inline const char *dma_chan_name(struct dma_chan *chan) |
487 | { | |
488 | return dev_name(&chan->dev->device); | |
489 | } | |
d379b01e | 490 | |
c13c8260 CL |
491 | void dma_chan_cleanup(struct kref *kref); |
492 | ||
59b5ec21 DW |
493 | /** |
494 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
495 | * @chan: channel to be reviewed | |
496 | * @filter_param: opaque parameter passed through dma_request_channel | |
497 | * | |
498 | * When this optional parameter is specified in a call to dma_request_channel a | |
499 | * suitable channel is passed to this routine for further dispositioning before | |
500 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
501 | * satisfies the given capability mask. It returns 'true' to indicate that the |
502 | * channel is suitable. | |
59b5ec21 | 503 | */ |
7dd60251 | 504 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 505 | |
7405f74b | 506 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
d38a8c62 | 507 | |
f067025b DJ |
508 | enum dmaengine_tx_result { |
509 | DMA_TRANS_NOERROR = 0, /* SUCCESS */ | |
510 | DMA_TRANS_READ_FAILED, /* Source DMA read failed */ | |
511 | DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */ | |
512 | DMA_TRANS_ABORTED, /* Op never submitted / aborted */ | |
513 | }; | |
514 | ||
515 | struct dmaengine_result { | |
516 | enum dmaengine_tx_result result; | |
517 | u32 residue; | |
518 | }; | |
519 | ||
520 | typedef void (*dma_async_tx_callback_result)(void *dma_async_param, | |
521 | const struct dmaengine_result *result); | |
522 | ||
d38a8c62 | 523 | struct dmaengine_unmap_data { |
0c0eb4ca ZY |
524 | #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) |
525 | u16 map_cnt; | |
526 | #else | |
c1f43dd9 | 527 | u8 map_cnt; |
0c0eb4ca | 528 | #endif |
d38a8c62 DW |
529 | u8 to_cnt; |
530 | u8 from_cnt; | |
531 | u8 bidi_cnt; | |
532 | struct device *dev; | |
533 | struct kref kref; | |
534 | size_t len; | |
535 | dma_addr_t addr[0]; | |
536 | }; | |
537 | ||
4db8fd32 PU |
538 | struct dma_async_tx_descriptor; |
539 | ||
540 | struct dma_descriptor_metadata_ops { | |
541 | int (*attach)(struct dma_async_tx_descriptor *desc, void *data, | |
542 | size_t len); | |
543 | ||
544 | void *(*get_ptr)(struct dma_async_tx_descriptor *desc, | |
545 | size_t *payload_len, size_t *max_len); | |
546 | int (*set_len)(struct dma_async_tx_descriptor *desc, | |
547 | size_t payload_len); | |
548 | }; | |
549 | ||
7405f74b DW |
550 | /** |
551 | * struct dma_async_tx_descriptor - async transaction descriptor | |
552 | * ---dma generic offload fields--- | |
553 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
554 | * this tx is sitting on a dependency list | |
636bdeaa | 555 | * @flags: flags to augment operation preparation, control completion, and |
dda51089 | 556 | * communicate status |
7405f74b | 557 | * @phys: physical address of the descriptor |
7405f74b | 558 | * @chan: target channel for this operation |
aba96bad VK |
559 | * @tx_submit: accept the descriptor, assign ordered cookie and mark the |
560 | * descriptor pending. To be pushed on .issue_pending() call | |
7405f74b DW |
561 | * @callback: routine to call after this operation is complete |
562 | * @callback_param: general parameter to pass to the callback routine | |
4db8fd32 PU |
563 | * @desc_metadata_mode: core managed metadata mode to protect mixed use of |
564 | * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise | |
565 | * DESC_METADATA_NONE | |
566 | * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the | |
567 | * DMA driver if metadata mode is supported with the descriptor | |
7405f74b | 568 | * ---async_tx api specific fields--- |
19242d72 | 569 | * @next: at completion submit this descriptor |
7405f74b | 570 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 571 | * @lock: protect the parent and next pointers |
7405f74b DW |
572 | */ |
573 | struct dma_async_tx_descriptor { | |
574 | dma_cookie_t cookie; | |
636bdeaa | 575 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 576 | dma_addr_t phys; |
7405f74b DW |
577 | struct dma_chan *chan; |
578 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
27242021 | 579 | int (*desc_free)(struct dma_async_tx_descriptor *tx); |
7405f74b | 580 | dma_async_tx_callback callback; |
f067025b | 581 | dma_async_tx_callback_result callback_result; |
7405f74b | 582 | void *callback_param; |
d38a8c62 | 583 | struct dmaengine_unmap_data *unmap; |
4db8fd32 PU |
584 | enum dma_desc_metadata_mode desc_metadata_mode; |
585 | struct dma_descriptor_metadata_ops *metadata_ops; | |
5fc6d897 | 586 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 587 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
588 | struct dma_async_tx_descriptor *parent; |
589 | spinlock_t lock; | |
caa20d97 | 590 | #endif |
7405f74b DW |
591 | }; |
592 | ||
89716462 | 593 | #ifdef CONFIG_DMA_ENGINE |
d38a8c62 DW |
594 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, |
595 | struct dmaengine_unmap_data *unmap) | |
596 | { | |
597 | kref_get(&unmap->kref); | |
598 | tx->unmap = unmap; | |
599 | } | |
600 | ||
89716462 DW |
601 | struct dmaengine_unmap_data * |
602 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
45c463ae | 603 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); |
89716462 DW |
604 | #else |
605 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
606 | struct dmaengine_unmap_data *unmap) | |
607 | { | |
608 | } | |
609 | static inline struct dmaengine_unmap_data * | |
610 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
611 | { | |
612 | return NULL; | |
613 | } | |
614 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
615 | { | |
616 | } | |
617 | #endif | |
45c463ae | 618 | |
d38a8c62 DW |
619 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) |
620 | { | |
3a92063b AS |
621 | if (!tx->unmap) |
622 | return; | |
623 | ||
624 | dmaengine_unmap_put(tx->unmap); | |
625 | tx->unmap = NULL; | |
d38a8c62 DW |
626 | } |
627 | ||
5fc6d897 | 628 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
629 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
630 | { | |
631 | } | |
632 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
633 | { | |
634 | } | |
635 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
636 | { | |
637 | BUG(); | |
638 | } | |
639 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
640 | { | |
641 | } | |
642 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
643 | { | |
644 | } | |
645 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
646 | { | |
647 | return NULL; | |
648 | } | |
649 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
650 | { | |
651 | return NULL; | |
652 | } | |
653 | ||
654 | #else | |
655 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
656 | { | |
657 | spin_lock_bh(&txd->lock); | |
658 | } | |
659 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
660 | { | |
661 | spin_unlock_bh(&txd->lock); | |
662 | } | |
663 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
664 | { | |
665 | txd->next = next; | |
666 | next->parent = txd; | |
667 | } | |
668 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
669 | { | |
670 | txd->parent = NULL; | |
671 | } | |
672 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
673 | { | |
674 | txd->next = NULL; | |
675 | } | |
676 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
677 | { | |
678 | return txd->parent; | |
679 | } | |
680 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
681 | { | |
682 | return txd->next; | |
683 | } | |
684 | #endif | |
685 | ||
07934481 LW |
686 | /** |
687 | * struct dma_tx_state - filled in to report the status of | |
688 | * a transfer. | |
689 | * @last: last completed DMA cookie | |
690 | * @used: last issued DMA cookie (i.e. the one in progress) | |
691 | * @residue: the remaining number of bytes left to transmit | |
692 | * on the selected transfer for states DMA_IN_PROGRESS and | |
693 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
6755ec06 | 694 | * @in_flight_bytes: amount of data in bytes cached by the DMA. |
07934481 LW |
695 | */ |
696 | struct dma_tx_state { | |
697 | dma_cookie_t last; | |
698 | dma_cookie_t used; | |
699 | u32 residue; | |
6755ec06 | 700 | u32 in_flight_bytes; |
07934481 LW |
701 | }; |
702 | ||
77a68e56 MR |
703 | /** |
704 | * enum dmaengine_alignment - defines alignment of the DMA async tx | |
705 | * buffers | |
706 | */ | |
707 | enum dmaengine_alignment { | |
708 | DMAENGINE_ALIGN_1_BYTE = 0, | |
709 | DMAENGINE_ALIGN_2_BYTES = 1, | |
710 | DMAENGINE_ALIGN_4_BYTES = 2, | |
711 | DMAENGINE_ALIGN_8_BYTES = 3, | |
712 | DMAENGINE_ALIGN_16_BYTES = 4, | |
713 | DMAENGINE_ALIGN_32_BYTES = 5, | |
714 | DMAENGINE_ALIGN_64_BYTES = 6, | |
715 | }; | |
716 | ||
a8135d0d PU |
717 | /** |
718 | * struct dma_slave_map - associates slave device and it's slave channel with | |
719 | * parameter to be used by a filter function | |
720 | * @devname: name of the device | |
721 | * @slave: slave channel name | |
722 | * @param: opaque parameter to pass to struct dma_filter.fn | |
723 | */ | |
724 | struct dma_slave_map { | |
725 | const char *devname; | |
726 | const char *slave; | |
727 | void *param; | |
728 | }; | |
729 | ||
730 | /** | |
731 | * struct dma_filter - information for slave device/channel to filter_fn/param | |
732 | * mapping | |
733 | * @fn: filter function callback | |
734 | * @mapcnt: number of slave device/channel in the map | |
735 | * @map: array of channel to filter mapping data | |
736 | */ | |
737 | struct dma_filter { | |
738 | dma_filter_fn fn; | |
739 | int mapcnt; | |
740 | const struct dma_slave_map *map; | |
741 | }; | |
742 | ||
c13c8260 CL |
743 | /** |
744 | * struct dma_device - info on the entity supplying DMA services | |
745 | * @chancnt: how many DMA channels are supported | |
0f571515 | 746 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
747 | * @channels: the list of struct dma_chan |
748 | * @global_node: list_head for global dma_device_list | |
a8135d0d | 749 | * @filter: information for device/slave to filter function/param mapping |
7405f74b | 750 | * @cap_mask: one or more dma_capability flags |
4db8fd32 | 751 | * @desc_metadata_modes: supported metadata modes by the DMA device |
7405f74b | 752 | * @max_xor: maximum number of xor sources, 0 if no capability |
b2f46fd8 | 753 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
754 | * @copy_align: alignment shift for memcpy operations |
755 | * @xor_align: alignment shift for xor operations | |
756 | * @pq_align: alignment shift for pq operations | |
4983a501 | 757 | * @fill_align: alignment shift for memset operations |
fe4ada2d | 758 | * @dev_id: unique device ID |
7405f74b | 759 | * @dev: struct device reference for dma mapping api |
dae7a589 | 760 | * @owner: owner module (automatically set based on the provided dev) |
cb8cea51 | 761 | * @src_addr_widths: bit mask of src addr widths the device supports |
c2cbd427 SB |
762 | * Width is specified in bytes, e.g. for a device supporting |
763 | * a width of 4 the mask should have BIT(4) set. | |
cb8cea51 | 764 | * @dst_addr_widths: bit mask of dst addr widths the device supports |
c2cbd427 SB |
765 | * @directions: bit mask of slave directions the device supports. |
766 | * Since the enum dma_transfer_direction is not defined as bit flag for | |
767 | * each type, the dma controller should set BIT(<TYPE>) and same | |
768 | * should be checked by controller as well | |
6d5bbed3 | 769 | * @max_burst: max burst capability per-transfer |
cb8cea51 MR |
770 | * @residue_granularity: granularity of the transfer residue reported |
771 | * by tx_status | |
fe4ada2d RD |
772 | * @device_alloc_chan_resources: allocate resources and return the |
773 | * number of allocated descriptors | |
774 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
775 | * @device_prep_dma_memcpy: prepares a memcpy operation |
776 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 777 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
778 | * @device_prep_dma_pq: prepares a pq operation |
779 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
4983a501 | 780 | * @device_prep_dma_memset: prepares a memset operation |
50c7cd2b | 781 | * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list |
7405f74b | 782 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 783 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
784 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
785 | * The function takes a buffer of size buf_len. The callback function will | |
786 | * be called after period_len bytes have been transferred. | |
b14dab79 | 787 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
ff39988a | 788 | * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address |
94a73e30 MR |
789 | * @device_config: Pushes a new configuration to a channel, return 0 or an error |
790 | * code | |
23a3ea2f MR |
791 | * @device_pause: Pauses any transfer happening on a channel. Returns |
792 | * 0 or an error code | |
793 | * @device_resume: Resumes any transfer on a channel previously | |
794 | * paused. Returns 0 or an error code | |
7fa0cf46 MR |
795 | * @device_terminate_all: Aborts all transfers on a channel. Returns 0 |
796 | * or an error code | |
b36f09c3 LPC |
797 | * @device_synchronize: Synchronizes the termination of a transfers to the |
798 | * current context. | |
07934481 LW |
799 | * @device_tx_status: poll for transaction completion, the optional |
800 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 801 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 802 | * will just return a simple status code |
7405f74b | 803 | * @device_issue_pending: push pending transactions to hardware |
9eeacd3a | 804 | * @descriptor_reuse: a submitted transfer can be resubmitted after completion |
8ad342a8 LG |
805 | * @device_release: called sometime atfer dma_async_device_unregister() is |
806 | * called and there are no further references to this structure. This | |
807 | * must be implemented to free resources however many existing drivers | |
808 | * do not and are therefore not safe to unbind while in use. | |
809 | * | |
c13c8260 CL |
810 | */ |
811 | struct dma_device { | |
8ad342a8 | 812 | struct kref ref; |
c13c8260 | 813 | unsigned int chancnt; |
0f571515 | 814 | unsigned int privatecnt; |
c13c8260 CL |
815 | struct list_head channels; |
816 | struct list_head global_node; | |
a8135d0d | 817 | struct dma_filter filter; |
7405f74b | 818 | dma_cap_mask_t cap_mask; |
4db8fd32 | 819 | enum dma_desc_metadata_mode desc_metadata_modes; |
b2f46fd8 DW |
820 | unsigned short max_xor; |
821 | unsigned short max_pq; | |
77a68e56 MR |
822 | enum dmaengine_alignment copy_align; |
823 | enum dmaengine_alignment xor_align; | |
824 | enum dmaengine_alignment pq_align; | |
825 | enum dmaengine_alignment fill_align; | |
b2f46fd8 | 826 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 827 | |
c13c8260 | 828 | int dev_id; |
7405f74b | 829 | struct device *dev; |
dae7a589 | 830 | struct module *owner; |
c13c8260 | 831 | |
cb8cea51 MR |
832 | u32 src_addr_widths; |
833 | u32 dst_addr_widths; | |
834 | u32 directions; | |
6d5bbed3 | 835 | u32 max_burst; |
9eeacd3a | 836 | bool descriptor_reuse; |
cb8cea51 MR |
837 | enum dma_residue_granularity residue_granularity; |
838 | ||
aa1e6f1a | 839 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 840 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
841 | |
842 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
ceacbdbf | 843 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
d4c56f97 | 844 | size_t len, unsigned long flags); |
7405f74b | 845 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
ceacbdbf | 846 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
d4c56f97 | 847 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 848 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 849 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 850 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
851 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
852 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
853 | unsigned int src_cnt, const unsigned char *scf, | |
854 | size_t len, unsigned long flags); | |
855 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
856 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
857 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
858 | enum sum_check_flags *pqres, unsigned long flags); | |
4983a501 MR |
859 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
860 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
861 | unsigned long flags); | |
50c7cd2b MR |
862 | struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( |
863 | struct dma_chan *chan, struct scatterlist *sg, | |
864 | unsigned int nents, int value, unsigned long flags); | |
7405f74b | 865 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 866 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 867 | |
dc0ee643 HS |
868 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
869 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 870 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 871 | unsigned long flags, void *context); |
782bc950 SH |
872 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
873 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 874 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 875 | unsigned long flags); |
b14dab79 JB |
876 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
877 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
878 | unsigned long flags); | |
ff39988a SY |
879 | struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( |
880 | struct dma_chan *chan, dma_addr_t dst, u64 data, | |
881 | unsigned long flags); | |
94a73e30 MR |
882 | |
883 | int (*device_config)(struct dma_chan *chan, | |
884 | struct dma_slave_config *config); | |
23a3ea2f MR |
885 | int (*device_pause)(struct dma_chan *chan); |
886 | int (*device_resume)(struct dma_chan *chan); | |
7fa0cf46 | 887 | int (*device_terminate_all)(struct dma_chan *chan); |
b36f09c3 | 888 | void (*device_synchronize)(struct dma_chan *chan); |
dc0ee643 | 889 | |
07934481 LW |
890 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
891 | dma_cookie_t cookie, | |
892 | struct dma_tx_state *txstate); | |
7405f74b | 893 | void (*device_issue_pending)(struct dma_chan *chan); |
8ad342a8 | 894 | void (*device_release)(struct dma_device *dev); |
c13c8260 CL |
895 | }; |
896 | ||
6e3ecaf0 SH |
897 | static inline int dmaengine_slave_config(struct dma_chan *chan, |
898 | struct dma_slave_config *config) | |
899 | { | |
94a73e30 MR |
900 | if (chan->device->device_config) |
901 | return chan->device->device_config(chan, config); | |
902 | ||
2c44ad91 | 903 | return -ENOSYS; |
6e3ecaf0 SH |
904 | } |
905 | ||
61cc13a5 AS |
906 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
907 | { | |
908 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
909 | } | |
910 | ||
90b44f8f | 911 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 912 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 913 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
914 | { |
915 | struct scatterlist sg; | |
922ee08b KM |
916 | sg_init_table(&sg, 1); |
917 | sg_dma_address(&sg) = buf; | |
918 | sg_dma_len(&sg) = len; | |
90b44f8f | 919 | |
757d12e5 VK |
920 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) |
921 | return NULL; | |
922 | ||
185ecb5f AB |
923 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
924 | dir, flags, NULL); | |
90b44f8f VK |
925 | } |
926 | ||
16052827 AB |
927 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
928 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
929 | enum dma_transfer_direction dir, unsigned long flags) | |
930 | { | |
757d12e5 VK |
931 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) |
932 | return NULL; | |
933 | ||
16052827 | 934 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, |
185ecb5f | 935 | dir, flags, NULL); |
16052827 AB |
936 | } |
937 | ||
e42d98eb AB |
938 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
939 | struct rio_dma_ext; | |
940 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
941 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
942 | enum dma_transfer_direction dir, unsigned long flags, | |
943 | struct rio_dma_ext *rio_ext) | |
944 | { | |
757d12e5 VK |
945 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) |
946 | return NULL; | |
947 | ||
e42d98eb AB |
948 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, |
949 | dir, flags, rio_ext); | |
950 | } | |
951 | #endif | |
952 | ||
16052827 AB |
953 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
954 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
955 | size_t period_len, enum dma_transfer_direction dir, |
956 | unsigned long flags) | |
16052827 | 957 | { |
757d12e5 VK |
958 | if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) |
959 | return NULL; | |
960 | ||
16052827 | 961 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, |
31c1e5a1 | 962 | period_len, dir, flags); |
a14acb4a BS |
963 | } |
964 | ||
965 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
966 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
967 | unsigned long flags) | |
968 | { | |
757d12e5 VK |
969 | if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) |
970 | return NULL; | |
971 | ||
a14acb4a | 972 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); |
90b44f8f VK |
973 | } |
974 | ||
4983a501 MR |
975 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( |
976 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
977 | unsigned long flags) | |
978 | { | |
757d12e5 | 979 | if (!chan || !chan->device || !chan->device->device_prep_dma_memset) |
4983a501 MR |
980 | return NULL; |
981 | ||
982 | return chan->device->device_prep_dma_memset(chan, dest, value, | |
983 | len, flags); | |
984 | } | |
985 | ||
77d65d6f BB |
986 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( |
987 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
988 | size_t len, unsigned long flags) | |
989 | { | |
990 | if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) | |
991 | return NULL; | |
992 | ||
993 | return chan->device->device_prep_dma_memcpy(chan, dest, src, | |
994 | len, flags); | |
995 | } | |
996 | ||
4db8fd32 PU |
997 | static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, |
998 | enum dma_desc_metadata_mode mode) | |
999 | { | |
1000 | if (!chan) | |
1001 | return false; | |
1002 | ||
1003 | return !!(chan->device->desc_metadata_modes & mode); | |
1004 | } | |
1005 | ||
1006 | #ifdef CONFIG_DMA_ENGINE | |
1007 | int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, | |
1008 | void *data, size_t len); | |
1009 | void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, | |
1010 | size_t *payload_len, size_t *max_len); | |
1011 | int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, | |
1012 | size_t payload_len); | |
1013 | #else /* CONFIG_DMA_ENGINE */ | |
1014 | static inline int dmaengine_desc_attach_metadata( | |
1015 | struct dma_async_tx_descriptor *desc, void *data, size_t len) | |
1016 | { | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | static inline void *dmaengine_desc_get_metadata_ptr( | |
1020 | struct dma_async_tx_descriptor *desc, size_t *payload_len, | |
1021 | size_t *max_len) | |
1022 | { | |
1023 | return NULL; | |
1024 | } | |
1025 | static inline int dmaengine_desc_set_metadata_len( | |
1026 | struct dma_async_tx_descriptor *desc, size_t payload_len) | |
1027 | { | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | #endif /* CONFIG_DMA_ENGINE */ | |
1031 | ||
b36f09c3 LPC |
1032 | /** |
1033 | * dmaengine_terminate_all() - Terminate all active DMA transfers | |
1034 | * @chan: The channel for which to terminate the transfers | |
1035 | * | |
1036 | * This function is DEPRECATED use either dmaengine_terminate_sync() or | |
1037 | * dmaengine_terminate_async() instead. | |
1038 | */ | |
6e3ecaf0 SH |
1039 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
1040 | { | |
7fa0cf46 MR |
1041 | if (chan->device->device_terminate_all) |
1042 | return chan->device->device_terminate_all(chan); | |
1043 | ||
2c44ad91 | 1044 | return -ENOSYS; |
6e3ecaf0 SH |
1045 | } |
1046 | ||
b36f09c3 LPC |
1047 | /** |
1048 | * dmaengine_terminate_async() - Terminate all active DMA transfers | |
1049 | * @chan: The channel for which to terminate the transfers | |
1050 | * | |
1051 | * Calling this function will terminate all active and pending descriptors | |
1052 | * that have previously been submitted to the channel. It is not guaranteed | |
1053 | * though that the transfer for the active descriptor has stopped when the | |
1054 | * function returns. Furthermore it is possible the complete callback of a | |
1055 | * submitted transfer is still running when this function returns. | |
1056 | * | |
1057 | * dmaengine_synchronize() needs to be called before it is safe to free | |
1058 | * any memory that is accessed by previously submitted descriptors or before | |
1059 | * freeing any resources accessed from within the completion callback of any | |
1060 | * perviously submitted descriptors. | |
1061 | * | |
1062 | * This function can be called from atomic context as well as from within a | |
1063 | * complete callback of a descriptor submitted on the same channel. | |
1064 | * | |
1065 | * If none of the two conditions above apply consider using | |
1066 | * dmaengine_terminate_sync() instead. | |
1067 | */ | |
1068 | static inline int dmaengine_terminate_async(struct dma_chan *chan) | |
1069 | { | |
1070 | if (chan->device->device_terminate_all) | |
1071 | return chan->device->device_terminate_all(chan); | |
1072 | ||
1073 | return -EINVAL; | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * dmaengine_synchronize() - Synchronize DMA channel termination | |
1078 | * @chan: The channel to synchronize | |
1079 | * | |
1080 | * Synchronizes to the DMA channel termination to the current context. When this | |
1081 | * function returns it is guaranteed that all transfers for previously issued | |
1082 | * descriptors have stopped and and it is safe to free the memory assoicated | |
1083 | * with them. Furthermore it is guaranteed that all complete callback functions | |
1084 | * for a previously submitted descriptor have finished running and it is safe to | |
1085 | * free resources accessed from within the complete callbacks. | |
1086 | * | |
1087 | * The behavior of this function is undefined if dma_async_issue_pending() has | |
1088 | * been called between dmaengine_terminate_async() and this function. | |
1089 | * | |
1090 | * This function must only be called from non-atomic context and must not be | |
1091 | * called from within a complete callback of a descriptor submitted on the same | |
1092 | * channel. | |
1093 | */ | |
1094 | static inline void dmaengine_synchronize(struct dma_chan *chan) | |
1095 | { | |
b1d6ab1a LPC |
1096 | might_sleep(); |
1097 | ||
b36f09c3 LPC |
1098 | if (chan->device->device_synchronize) |
1099 | chan->device->device_synchronize(chan); | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * dmaengine_terminate_sync() - Terminate all active DMA transfers | |
1104 | * @chan: The channel for which to terminate the transfers | |
1105 | * | |
1106 | * Calling this function will terminate all active and pending transfers | |
1107 | * that have previously been submitted to the channel. It is similar to | |
1108 | * dmaengine_terminate_async() but guarantees that the DMA transfer has actually | |
1109 | * stopped and that all complete callbacks have finished running when the | |
1110 | * function returns. | |
1111 | * | |
1112 | * This function must only be called from non-atomic context and must not be | |
1113 | * called from within a complete callback of a descriptor submitted on the same | |
1114 | * channel. | |
1115 | */ | |
1116 | static inline int dmaengine_terminate_sync(struct dma_chan *chan) | |
1117 | { | |
1118 | int ret; | |
1119 | ||
1120 | ret = dmaengine_terminate_async(chan); | |
1121 | if (ret) | |
1122 | return ret; | |
1123 | ||
1124 | dmaengine_synchronize(chan); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
6e3ecaf0 SH |
1129 | static inline int dmaengine_pause(struct dma_chan *chan) |
1130 | { | |
23a3ea2f MR |
1131 | if (chan->device->device_pause) |
1132 | return chan->device->device_pause(chan); | |
1133 | ||
2c44ad91 | 1134 | return -ENOSYS; |
6e3ecaf0 SH |
1135 | } |
1136 | ||
1137 | static inline int dmaengine_resume(struct dma_chan *chan) | |
1138 | { | |
23a3ea2f MR |
1139 | if (chan->device->device_resume) |
1140 | return chan->device->device_resume(chan); | |
1141 | ||
2c44ad91 | 1142 | return -ENOSYS; |
6e3ecaf0 SH |
1143 | } |
1144 | ||
3052cc2c LPC |
1145 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
1146 | dma_cookie_t cookie, struct dma_tx_state *state) | |
1147 | { | |
1148 | return chan->device->device_tx_status(chan, cookie, state); | |
1149 | } | |
1150 | ||
98d530fe | 1151 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
1152 | { |
1153 | return desc->tx_submit(desc); | |
1154 | } | |
1155 | ||
77a68e56 MR |
1156 | static inline bool dmaengine_check_align(enum dmaengine_alignment align, |
1157 | size_t off1, size_t off2, size_t len) | |
83544ae9 | 1158 | { |
88ac039c | 1159 | return !(((1 << align) - 1) & (off1 | off2 | len)); |
83544ae9 DW |
1160 | } |
1161 | ||
1162 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
1163 | size_t off2, size_t len) | |
1164 | { | |
1165 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
1166 | } | |
1167 | ||
1168 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
1169 | size_t off2, size_t len) | |
1170 | { | |
1171 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
1172 | } | |
1173 | ||
1174 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
1175 | size_t off2, size_t len) | |
1176 | { | |
1177 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
1178 | } | |
1179 | ||
4983a501 MR |
1180 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, |
1181 | size_t off2, size_t len) | |
1182 | { | |
1183 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
1184 | } | |
1185 | ||
b2f46fd8 DW |
1186 | static inline void |
1187 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
1188 | { | |
1189 | dma->max_pq = maxpq; | |
1190 | if (has_pq_continue) | |
1191 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
1192 | } | |
1193 | ||
1194 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
1195 | { | |
1196 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
1197 | } | |
1198 | ||
1199 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
1200 | { | |
1201 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
1202 | ||
1203 | return (flags & mask) == mask; | |
1204 | } | |
1205 | ||
1206 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
1207 | { | |
1208 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
1209 | } | |
1210 | ||
d3f3cf85 | 1211 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
1212 | { |
1213 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
1214 | } | |
1215 | ||
1216 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
1217 | * @dma - dma device with PQ capability | |
1218 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
1219 | * | |
1220 | * When an engine does not support native continuation we need 3 extra | |
1221 | * source slots to reuse P and Q with the following coefficients: | |
1222 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
1223 | * 2/ {01} * Q : use Q to continue Q' calculation | |
1224 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
1225 | * | |
1226 | * In the case where P is disabled we only need 1 extra source: | |
1227 | * 1/ {01} * Q : use Q to continue Q' calculation | |
1228 | */ | |
1229 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
1230 | { | |
1231 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
1232 | return dma_dev_to_maxpq(dma); | |
1233 | else if (dmaf_p_disabled_continue(flags)) | |
1234 | return dma_dev_to_maxpq(dma) - 1; | |
1235 | else if (dmaf_continue(flags)) | |
1236 | return dma_dev_to_maxpq(dma) - 3; | |
1237 | BUG(); | |
1238 | } | |
1239 | ||
87d001ef MR |
1240 | static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, |
1241 | size_t dir_icg) | |
1242 | { | |
1243 | if (inc) { | |
1244 | if (dir_icg) | |
1245 | return dir_icg; | |
1246 | else if (sgl) | |
1247 | return icg; | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, | |
1254 | struct data_chunk *chunk) | |
1255 | { | |
1256 | return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, | |
1257 | chunk->icg, chunk->dst_icg); | |
1258 | } | |
1259 | ||
1260 | static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, | |
1261 | struct data_chunk *chunk) | |
1262 | { | |
1263 | return dmaengine_get_icg(xt->src_inc, xt->src_sgl, | |
1264 | chunk->icg, chunk->src_icg); | |
1265 | } | |
1266 | ||
c13c8260 CL |
1267 | /* --- public DMA engine API --- */ |
1268 | ||
649274d9 | 1269 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
1270 | void dmaengine_get(void); |
1271 | void dmaengine_put(void); | |
649274d9 DW |
1272 | #else |
1273 | static inline void dmaengine_get(void) | |
1274 | { | |
1275 | } | |
1276 | static inline void dmaengine_put(void) | |
1277 | { | |
1278 | } | |
1279 | #endif | |
1280 | ||
729b5d1b DW |
1281 | #ifdef CONFIG_ASYNC_TX_DMA |
1282 | #define async_dmaengine_get() dmaengine_get() | |
1283 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 1284 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
1285 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
1286 | #else | |
729b5d1b | 1287 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 1288 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
1289 | #else |
1290 | static inline void async_dmaengine_get(void) | |
1291 | { | |
1292 | } | |
1293 | static inline void async_dmaengine_put(void) | |
1294 | { | |
1295 | } | |
1296 | static inline struct dma_chan * | |
1297 | async_dma_find_channel(enum dma_transaction_type type) | |
1298 | { | |
1299 | return NULL; | |
1300 | } | |
138f4c35 | 1301 | #endif /* CONFIG_ASYNC_TX_DMA */ |
7405f74b | 1302 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
7bced397 | 1303 | struct dma_chan *chan); |
c13c8260 | 1304 | |
0839875e | 1305 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 1306 | { |
636bdeaa DW |
1307 | tx->flags |= DMA_CTRL_ACK; |
1308 | } | |
1309 | ||
ef560682 GL |
1310 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
1311 | { | |
1312 | tx->flags &= ~DMA_CTRL_ACK; | |
1313 | } | |
1314 | ||
0839875e | 1315 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 1316 | { |
0839875e | 1317 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
1318 | } |
1319 | ||
7405f74b DW |
1320 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
1321 | static inline void | |
1322 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 1323 | { |
7405f74b DW |
1324 | set_bit(tx_type, dstp->bits); |
1325 | } | |
c13c8260 | 1326 | |
0f571515 AN |
1327 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
1328 | static inline void | |
1329 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
1330 | { | |
1331 | clear_bit(tx_type, dstp->bits); | |
1332 | } | |
1333 | ||
33df8ca0 DW |
1334 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
1335 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
1336 | { | |
1337 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
1338 | } | |
1339 | ||
7405f74b DW |
1340 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
1341 | static inline int | |
1342 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
1343 | { | |
1344 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
1345 | } |
1346 | ||
7405f74b | 1347 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 1348 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 1349 | |
c13c8260 | 1350 | /** |
7405f74b | 1351 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 1352 | * @chan: target DMA channel |
c13c8260 CL |
1353 | * |
1354 | * This allows drivers to push copies to HW in batches, | |
1355 | * reducing MMIO writes where possible. | |
1356 | */ | |
7405f74b | 1357 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 1358 | { |
ec8670f1 | 1359 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
1360 | } |
1361 | ||
1362 | /** | |
7405f74b | 1363 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
1364 | * @chan: DMA channel |
1365 | * @cookie: transaction identifier to check status of | |
1366 | * @last: returns last completed cookie, can be NULL | |
1367 | * @used: returns last issued cookie, can be NULL | |
1368 | * | |
1369 | * If @last and @used are passed in, upon return they reflect the driver | |
1370 | * internal state and can be used with dma_async_is_complete() to check | |
1371 | * the status of multiple cookies without re-checking hardware state. | |
1372 | */ | |
7405f74b | 1373 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
1374 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
1375 | { | |
07934481 LW |
1376 | struct dma_tx_state state; |
1377 | enum dma_status status; | |
1378 | ||
1379 | status = chan->device->device_tx_status(chan, cookie, &state); | |
1380 | if (last) | |
1381 | *last = state.last; | |
1382 | if (used) | |
1383 | *used = state.used; | |
1384 | return status; | |
c13c8260 CL |
1385 | } |
1386 | ||
1387 | /** | |
1388 | * dma_async_is_complete - test a cookie against chan state | |
1389 | * @cookie: transaction identifier to test status of | |
1390 | * @last_complete: last know completed transaction | |
1391 | * @last_used: last cookie value handed out | |
1392 | * | |
e239345f | 1393 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 1394 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
1395 | */ |
1396 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1397 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1398 | { | |
1399 | if (last_complete <= last_used) { | |
1400 | if ((cookie <= last_complete) || (cookie > last_used)) | |
adfedd9a | 1401 | return DMA_COMPLETE; |
c13c8260 CL |
1402 | } else { |
1403 | if ((cookie <= last_complete) && (cookie > last_used)) | |
adfedd9a | 1404 | return DMA_COMPLETE; |
c13c8260 CL |
1405 | } |
1406 | return DMA_IN_PROGRESS; | |
1407 | } | |
1408 | ||
bca34692 DW |
1409 | static inline void |
1410 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1411 | { | |
3a92063b AS |
1412 | if (!st) |
1413 | return; | |
1414 | ||
1415 | st->last = last; | |
1416 | st->used = used; | |
1417 | st->residue = residue; | |
bca34692 DW |
1418 | } |
1419 | ||
07f2211e | 1420 | #ifdef CONFIG_DMA_ENGINE |
4a43f394 JM |
1421 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
1422 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
07f2211e | 1423 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
c50331e8 | 1424 | void dma_issue_pending_all(void); |
a53e28da | 1425 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
f5151311 BW |
1426 | dma_filter_fn fn, void *fn_param, |
1427 | struct device_node *np); | |
bef29ec5 | 1428 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
a8135d0d PU |
1429 | |
1430 | struct dma_chan *dma_request_chan(struct device *dev, const char *name); | |
1431 | struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); | |
1432 | ||
8f33d527 | 1433 | void dma_release_channel(struct dma_chan *chan); |
fdb8df99 | 1434 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); |
07f2211e | 1435 | #else |
4a43f394 JM |
1436 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) |
1437 | { | |
1438 | return NULL; | |
1439 | } | |
1440 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1441 | { | |
adfedd9a | 1442 | return DMA_COMPLETE; |
4a43f394 | 1443 | } |
07f2211e DW |
1444 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1445 | { | |
adfedd9a | 1446 | return DMA_COMPLETE; |
07f2211e | 1447 | } |
c50331e8 DW |
1448 | static inline void dma_issue_pending_all(void) |
1449 | { | |
8f33d527 | 1450 | } |
a53e28da | 1451 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
f5151311 BW |
1452 | dma_filter_fn fn, |
1453 | void *fn_param, | |
1454 | struct device_node *np) | |
8f33d527 GL |
1455 | { |
1456 | return NULL; | |
1457 | } | |
9a6cecc8 | 1458 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 1459 | const char *name) |
9a6cecc8 | 1460 | { |
d18d5f59 | 1461 | return NULL; |
9a6cecc8 | 1462 | } |
a8135d0d PU |
1463 | static inline struct dma_chan *dma_request_chan(struct device *dev, |
1464 | const char *name) | |
1465 | { | |
1466 | return ERR_PTR(-ENODEV); | |
1467 | } | |
1468 | static inline struct dma_chan *dma_request_chan_by_mask( | |
1469 | const dma_cap_mask_t *mask) | |
1470 | { | |
1471 | return ERR_PTR(-ENODEV); | |
1472 | } | |
8f33d527 GL |
1473 | static inline void dma_release_channel(struct dma_chan *chan) |
1474 | { | |
c50331e8 | 1475 | } |
fdb8df99 LP |
1476 | static inline int dma_get_slave_caps(struct dma_chan *chan, |
1477 | struct dma_slave_caps *caps) | |
1478 | { | |
1479 | return -ENXIO; | |
1480 | } | |
07f2211e | 1481 | #endif |
c13c8260 | 1482 | |
a8135d0d PU |
1483 | #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name) |
1484 | ||
27242021 VK |
1485 | static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) |
1486 | { | |
1487 | struct dma_slave_caps caps; | |
53a256a9 | 1488 | int ret; |
27242021 | 1489 | |
53a256a9 LW |
1490 | ret = dma_get_slave_caps(tx->chan, &caps); |
1491 | if (ret) | |
1492 | return ret; | |
27242021 | 1493 | |
3a92063b | 1494 | if (!caps.descriptor_reuse) |
27242021 | 1495 | return -EPERM; |
3a92063b AS |
1496 | |
1497 | tx->flags |= DMA_CTRL_REUSE; | |
1498 | return 0; | |
27242021 VK |
1499 | } |
1500 | ||
1501 | static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) | |
1502 | { | |
1503 | tx->flags &= ~DMA_CTRL_REUSE; | |
1504 | } | |
1505 | ||
1506 | static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) | |
1507 | { | |
1508 | return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; | |
1509 | } | |
1510 | ||
1511 | static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) | |
1512 | { | |
1513 | /* this is supported for reusable desc, so check that */ | |
3a92063b | 1514 | if (!dmaengine_desc_test_reuse(desc)) |
27242021 | 1515 | return -EPERM; |
3a92063b AS |
1516 | |
1517 | return desc->desc_free(desc); | |
27242021 VK |
1518 | } |
1519 | ||
c13c8260 CL |
1520 | /* --- DMA device --- */ |
1521 | ||
1522 | int dma_async_device_register(struct dma_device *device); | |
f39b948d | 1523 | int dmaenginem_async_device_register(struct dma_device *device); |
c13c8260 | 1524 | void dma_async_device_unregister(struct dma_device *device); |
e81274cd DJ |
1525 | int dma_async_device_channel_register(struct dma_device *device, |
1526 | struct dma_chan *chan); | |
1527 | void dma_async_device_channel_unregister(struct dma_device *device, | |
1528 | struct dma_chan *chan); | |
07f2211e | 1529 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
f5151311 BW |
1530 | #define dma_request_channel(mask, x, y) \ |
1531 | __dma_request_channel(&(mask), x, y, NULL) | |
864ef69b MP |
1532 | |
1533 | static inline struct dma_chan | |
71ca5b78 | 1534 | *dma_request_slave_channel_compat(const dma_cap_mask_t mask, |
a53e28da | 1535 | dma_filter_fn fn, void *fn_param, |
1dc04288 | 1536 | struct device *dev, const char *name) |
864ef69b MP |
1537 | { |
1538 | struct dma_chan *chan; | |
1539 | ||
1540 | chan = dma_request_slave_channel(dev, name); | |
1541 | if (chan) | |
1542 | return chan; | |
1543 | ||
7dfffb95 GU |
1544 | if (!fn || !fn_param) |
1545 | return NULL; | |
1546 | ||
71ca5b78 | 1547 | return __dma_request_channel(&mask, fn, fn_param, NULL); |
864ef69b | 1548 | } |
816ebf48 PU |
1549 | |
1550 | static inline char * | |
1551 | dmaengine_get_direction_text(enum dma_transfer_direction dir) | |
1552 | { | |
1553 | switch (dir) { | |
1554 | case DMA_DEV_TO_MEM: | |
1555 | return "DEV_TO_MEM"; | |
1556 | case DMA_MEM_TO_DEV: | |
1557 | return "MEM_TO_DEV"; | |
1558 | case DMA_MEM_TO_MEM: | |
1559 | return "MEM_TO_MEM"; | |
1560 | case DMA_DEV_TO_DEV: | |
1561 | return "DEV_TO_DEV"; | |
1562 | default: | |
1563 | break; | |
1564 | } | |
1565 | ||
1566 | return "invalid"; | |
864ef69b | 1567 | } |
c13c8260 | 1568 | #endif /* DMAENGINE_H */ |