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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
26 | #include <linux/kref.h> | |
27 | #include <linux/completion.h> | |
28 | #include <linux/rcupdate.h> | |
7405f74b | 29 | #include <linux/dma-mapping.h> |
c13c8260 CL |
30 | |
31 | /** | |
fd3f8984 | 32 | * enum dma_state - resource PNP/power management state |
c13c8260 CL |
33 | * @DMA_RESOURCE_SUSPEND: DMA device going into low power state |
34 | * @DMA_RESOURCE_RESUME: DMA device returning to full power | |
d379b01e | 35 | * @DMA_RESOURCE_AVAILABLE: DMA device available to the system |
c13c8260 CL |
36 | * @DMA_RESOURCE_REMOVED: DMA device removed from the system |
37 | */ | |
d379b01e | 38 | enum dma_state { |
c13c8260 CL |
39 | DMA_RESOURCE_SUSPEND, |
40 | DMA_RESOURCE_RESUME, | |
d379b01e | 41 | DMA_RESOURCE_AVAILABLE, |
c13c8260 CL |
42 | DMA_RESOURCE_REMOVED, |
43 | }; | |
44 | ||
d379b01e DW |
45 | /** |
46 | * enum dma_state_client - state of the channel in the client | |
47 | * @DMA_ACK: client would like to use, or was using this channel | |
48 | * @DMA_DUP: client has already seen this channel, or is not using this channel | |
49 | * @DMA_NAK: client does not want to see any more channels | |
50 | */ | |
51 | enum dma_state_client { | |
52 | DMA_ACK, | |
53 | DMA_DUP, | |
54 | DMA_NAK, | |
55 | }; | |
56 | ||
c13c8260 | 57 | /** |
fe4ada2d | 58 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
59 | * |
60 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
61 | */ | |
62 | typedef s32 dma_cookie_t; | |
63 | ||
64 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
65 | ||
66 | /** | |
67 | * enum dma_status - DMA transaction status | |
68 | * @DMA_SUCCESS: transaction completed successfully | |
69 | * @DMA_IN_PROGRESS: transaction not yet processed | |
70 | * @DMA_ERROR: transaction failed | |
71 | */ | |
72 | enum dma_status { | |
73 | DMA_SUCCESS, | |
74 | DMA_IN_PROGRESS, | |
75 | DMA_ERROR, | |
76 | }; | |
77 | ||
7405f74b DW |
78 | /** |
79 | * enum dma_transaction_type - DMA transaction types/indexes | |
80 | */ | |
81 | enum dma_transaction_type { | |
82 | DMA_MEMCPY, | |
83 | DMA_XOR, | |
84 | DMA_PQ_XOR, | |
85 | DMA_DUAL_XOR, | |
86 | DMA_PQ_UPDATE, | |
87 | DMA_ZERO_SUM, | |
88 | DMA_PQ_ZERO_SUM, | |
89 | DMA_MEMSET, | |
90 | DMA_MEMCPY_CRC32C, | |
91 | DMA_INTERRUPT, | |
59b5ec21 | 92 | DMA_PRIVATE, |
dc0ee643 | 93 | DMA_SLAVE, |
7405f74b DW |
94 | }; |
95 | ||
96 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
97 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
98 | ||
99 | /** | |
100 | * enum dma_slave_width - DMA slave register access width. | |
101 | * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses | |
102 | * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses | |
103 | * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses | |
104 | */ | |
105 | enum dma_slave_width { | |
106 | DMA_SLAVE_WIDTH_8BIT, | |
107 | DMA_SLAVE_WIDTH_16BIT, | |
108 | DMA_SLAVE_WIDTH_32BIT, | |
109 | }; | |
7405f74b | 110 | |
d4c56f97 | 111 | /** |
636bdeaa DW |
112 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
113 | * control completion, and communicate status. | |
d4c56f97 DW |
114 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
115 | * this transaction | |
636bdeaa DW |
116 | * @DMA_CTRL_ACK - the descriptor cannot be reused until the client |
117 | * acknowledges receipt, i.e. has has a chance to establish any | |
118 | * dependency chains | |
e1d181ef DW |
119 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
120 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
d4c56f97 | 121 | */ |
636bdeaa | 122 | enum dma_ctrl_flags { |
d4c56f97 | 123 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 124 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
125 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
126 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
d4c56f97 DW |
127 | }; |
128 | ||
7405f74b DW |
129 | /** |
130 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
131 | * See linux/cpumask.h | |
132 | */ | |
133 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
134 | ||
dc0ee643 HS |
135 | /** |
136 | * struct dma_slave - Information about a DMA slave | |
137 | * @dev: device acting as DMA slave | |
138 | * @dma_dev: required DMA master device. If non-NULL, the client can not be | |
139 | * bound to other masters than this. | |
140 | * @tx_reg: physical address of data register used for | |
141 | * memory-to-peripheral transfers | |
142 | * @rx_reg: physical address of data register used for | |
143 | * peripheral-to-memory transfers | |
144 | * @reg_width: peripheral register width | |
145 | * | |
146 | * If dma_dev is non-NULL, the client can not be bound to other DMA | |
147 | * masters than the one corresponding to this device. The DMA master | |
148 | * driver may use this to determine if there is controller-specific | |
149 | * data wrapped around this struct. Drivers of platform code that sets | |
150 | * the dma_dev field must therefore make sure to use an appropriate | |
151 | * controller-specific dma slave structure wrapping this struct. | |
152 | */ | |
153 | struct dma_slave { | |
154 | struct device *dev; | |
155 | struct device *dma_dev; | |
156 | dma_addr_t tx_reg; | |
157 | dma_addr_t rx_reg; | |
158 | enum dma_slave_width reg_width; | |
159 | }; | |
160 | ||
c13c8260 CL |
161 | /** |
162 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
163 | * @refcount: local_t used for open-coded "bigref" counting | |
164 | * @memcpy_count: transaction counter | |
165 | * @bytes_transferred: byte counter | |
166 | */ | |
167 | ||
168 | struct dma_chan_percpu { | |
c13c8260 CL |
169 | /* stats */ |
170 | unsigned long memcpy_count; | |
171 | unsigned long bytes_transferred; | |
172 | }; | |
173 | ||
174 | /** | |
175 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 176 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 177 | * @cookie: last cookie value returned to client |
fe4ada2d RD |
178 | * @chan_id: channel ID for sysfs |
179 | * @class_dev: class device for sysfs | |
c13c8260 | 180 | * @refcount: kref, used in "bigref" slow-mode |
fe4ada2d RD |
181 | * @slow_ref: indicates that the DMA channel is free |
182 | * @rcu: the DMA channel's RCU head | |
c13c8260 CL |
183 | * @device_node: used to add this to the device chan list |
184 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 185 | * @client-count: how many clients are using this channel |
bec08513 | 186 | * @table_count: number of appearances in the mem-to-mem allocation table |
c13c8260 CL |
187 | */ |
188 | struct dma_chan { | |
c13c8260 CL |
189 | struct dma_device *device; |
190 | dma_cookie_t cookie; | |
191 | ||
192 | /* sysfs */ | |
193 | int chan_id; | |
891f78ea | 194 | struct device dev; |
c13c8260 CL |
195 | |
196 | struct kref refcount; | |
197 | int slow_ref; | |
198 | struct rcu_head rcu; | |
199 | ||
c13c8260 CL |
200 | struct list_head device_node; |
201 | struct dma_chan_percpu *local; | |
7cc5bf9a | 202 | int client_count; |
bec08513 | 203 | int table_count; |
c13c8260 CL |
204 | }; |
205 | ||
891f78ea | 206 | #define to_dma_chan(p) container_of(p, struct dma_chan, dev) |
d379b01e | 207 | |
c13c8260 CL |
208 | void dma_chan_cleanup(struct kref *kref); |
209 | ||
c13c8260 CL |
210 | /* |
211 | * typedef dma_event_callback - function pointer to a DMA event callback | |
d379b01e DW |
212 | * For each channel added to the system this routine is called for each client. |
213 | * If the client would like to use the channel it returns '1' to signal (ack) | |
214 | * the dmaengine core to take out a reference on the channel and its | |
215 | * corresponding device. A client must not 'ack' an available channel more | |
216 | * than once. When a channel is removed all clients are notified. If a client | |
217 | * is using the channel it must 'ack' the removal. A client must not 'ack' a | |
218 | * removed channel more than once. | |
219 | * @client - 'this' pointer for the client context | |
220 | * @chan - channel to be acted upon | |
221 | * @state - available or removed | |
c13c8260 | 222 | */ |
d379b01e DW |
223 | struct dma_client; |
224 | typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client, | |
225 | struct dma_chan *chan, enum dma_state state); | |
c13c8260 | 226 | |
59b5ec21 DW |
227 | /** |
228 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
229 | * @chan: channel to be reviewed | |
230 | * @filter_param: opaque parameter passed through dma_request_channel | |
231 | * | |
232 | * When this optional parameter is specified in a call to dma_request_channel a | |
233 | * suitable channel is passed to this routine for further dispositioning before | |
234 | * being returned. Where 'suitable' indicates a non-busy channel that | |
235 | * satisfies the given capability mask. | |
236 | */ | |
237 | typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); | |
238 | ||
c13c8260 CL |
239 | /** |
240 | * struct dma_client - info on the entity making use of DMA services | |
241 | * @event_callback: func ptr to call when something happens | |
d379b01e DW |
242 | * @cap_mask: only return channels that satisfy the requested capabilities |
243 | * a value of zero corresponds to any capability | |
dc0ee643 HS |
244 | * @slave: data for preparing slave transfer. Must be non-NULL iff the |
245 | * DMA_SLAVE capability is requested. | |
c13c8260 CL |
246 | * @global_node: list_head for global dma_client_list |
247 | */ | |
248 | struct dma_client { | |
249 | dma_event_callback event_callback; | |
d379b01e | 250 | dma_cap_mask_t cap_mask; |
dc0ee643 | 251 | struct dma_slave *slave; |
c13c8260 CL |
252 | struct list_head global_node; |
253 | }; | |
254 | ||
7405f74b DW |
255 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
256 | /** | |
257 | * struct dma_async_tx_descriptor - async transaction descriptor | |
258 | * ---dma generic offload fields--- | |
259 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
260 | * this tx is sitting on a dependency list | |
636bdeaa DW |
261 | * @flags: flags to augment operation preparation, control completion, and |
262 | * communicate status | |
7405f74b DW |
263 | * @phys: physical address of the descriptor |
264 | * @tx_list: driver common field for operations that require multiple | |
265 | * descriptors | |
266 | * @chan: target channel for this operation | |
267 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
268 | * @callback: routine to call after this operation is complete |
269 | * @callback_param: general parameter to pass to the callback routine | |
270 | * ---async_tx api specific fields--- | |
19242d72 | 271 | * @next: at completion submit this descriptor |
7405f74b | 272 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 273 | * @lock: protect the parent and next pointers |
7405f74b DW |
274 | */ |
275 | struct dma_async_tx_descriptor { | |
276 | dma_cookie_t cookie; | |
636bdeaa | 277 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b DW |
278 | dma_addr_t phys; |
279 | struct list_head tx_list; | |
280 | struct dma_chan *chan; | |
281 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
282 | dma_async_tx_callback callback; |
283 | void *callback_param; | |
19242d72 | 284 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
285 | struct dma_async_tx_descriptor *parent; |
286 | spinlock_t lock; | |
287 | }; | |
288 | ||
c13c8260 CL |
289 | /** |
290 | * struct dma_device - info on the entity supplying DMA services | |
291 | * @chancnt: how many DMA channels are supported | |
292 | * @channels: the list of struct dma_chan | |
293 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
294 | * @cap_mask: one or more dma_capability flags |
295 | * @max_xor: maximum number of xor sources, 0 if no capability | |
fe4ada2d RD |
296 | * @refcount: reference count |
297 | * @done: IO completion struct | |
298 | * @dev_id: unique device ID | |
7405f74b | 299 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
300 | * @device_alloc_chan_resources: allocate resources and return the |
301 | * number of allocated descriptors | |
302 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
303 | * @device_prep_dma_memcpy: prepares a memcpy operation |
304 | * @device_prep_dma_xor: prepares a xor operation | |
305 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | |
306 | * @device_prep_dma_memset: prepares a memset operation | |
307 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
308 | * @device_prep_slave_sg: prepares a slave dma operation |
309 | * @device_terminate_all: terminate all pending operations | |
7405f74b | 310 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
311 | */ |
312 | struct dma_device { | |
313 | ||
314 | unsigned int chancnt; | |
315 | struct list_head channels; | |
316 | struct list_head global_node; | |
7405f74b DW |
317 | dma_cap_mask_t cap_mask; |
318 | int max_xor; | |
c13c8260 CL |
319 | |
320 | struct kref refcount; | |
321 | struct completion done; | |
322 | ||
323 | int dev_id; | |
7405f74b | 324 | struct device *dev; |
c13c8260 | 325 | |
848c536a HS |
326 | int (*device_alloc_chan_resources)(struct dma_chan *chan, |
327 | struct dma_client *client); | |
c13c8260 | 328 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
329 | |
330 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 331 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 332 | size_t len, unsigned long flags); |
7405f74b | 333 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 334 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 335 | unsigned int src_cnt, size_t len, unsigned long flags); |
7405f74b | 336 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
0036731c | 337 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
d4c56f97 | 338 | size_t len, u32 *result, unsigned long flags); |
7405f74b | 339 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 340 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 341 | unsigned long flags); |
7405f74b | 342 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 343 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 344 | |
dc0ee643 HS |
345 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
346 | struct dma_chan *chan, struct scatterlist *sgl, | |
347 | unsigned int sg_len, enum dma_data_direction direction, | |
348 | unsigned long flags); | |
349 | void (*device_terminate_all)(struct dma_chan *chan); | |
350 | ||
7405f74b | 351 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
352 | dma_cookie_t cookie, dma_cookie_t *last, |
353 | dma_cookie_t *used); | |
7405f74b | 354 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
355 | }; |
356 | ||
357 | /* --- public DMA engine API --- */ | |
358 | ||
d379b01e | 359 | void dma_async_client_register(struct dma_client *client); |
c13c8260 | 360 | void dma_async_client_unregister(struct dma_client *client); |
d379b01e | 361 | void dma_async_client_chan_request(struct dma_client *client); |
7405f74b DW |
362 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
363 | void *dest, void *src, size_t len); | |
364 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
365 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
366 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
367 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
368 | unsigned int src_off, size_t len); | |
369 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
370 | struct dma_chan *chan); | |
c13c8260 | 371 | |
0839875e | 372 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 373 | { |
636bdeaa DW |
374 | tx->flags |= DMA_CTRL_ACK; |
375 | } | |
376 | ||
0839875e | 377 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 378 | { |
0839875e | 379 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
380 | } |
381 | ||
7405f74b DW |
382 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
383 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 384 | { |
7405f74b DW |
385 | return min_t(int, DMA_TX_TYPE_END, |
386 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
387 | } | |
c13c8260 | 388 | |
7405f74b DW |
389 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
390 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
391 | { | |
392 | return min_t(int, DMA_TX_TYPE_END, | |
393 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
394 | } |
395 | ||
7405f74b DW |
396 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
397 | static inline void | |
398 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 399 | { |
7405f74b DW |
400 | set_bit(tx_type, dstp->bits); |
401 | } | |
c13c8260 | 402 | |
7405f74b DW |
403 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
404 | static inline int | |
405 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
406 | { | |
407 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
408 | } |
409 | ||
7405f74b DW |
410 | #define for_each_dma_cap_mask(cap, mask) \ |
411 | for ((cap) = first_dma_cap(mask); \ | |
412 | (cap) < DMA_TX_TYPE_END; \ | |
413 | (cap) = next_dma_cap((cap), (mask))) | |
414 | ||
c13c8260 | 415 | /** |
7405f74b | 416 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 417 | * @chan: target DMA channel |
c13c8260 CL |
418 | * |
419 | * This allows drivers to push copies to HW in batches, | |
420 | * reducing MMIO writes where possible. | |
421 | */ | |
7405f74b | 422 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 423 | { |
ec8670f1 | 424 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
425 | } |
426 | ||
7405f74b DW |
427 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
428 | ||
c13c8260 | 429 | /** |
7405f74b | 430 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
431 | * @chan: DMA channel |
432 | * @cookie: transaction identifier to check status of | |
433 | * @last: returns last completed cookie, can be NULL | |
434 | * @used: returns last issued cookie, can be NULL | |
435 | * | |
436 | * If @last and @used are passed in, upon return they reflect the driver | |
437 | * internal state and can be used with dma_async_is_complete() to check | |
438 | * the status of multiple cookies without re-checking hardware state. | |
439 | */ | |
7405f74b | 440 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
441 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
442 | { | |
7405f74b | 443 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
444 | } |
445 | ||
7405f74b DW |
446 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
447 | dma_async_is_tx_complete(chan, cookie, last, used) | |
448 | ||
c13c8260 CL |
449 | /** |
450 | * dma_async_is_complete - test a cookie against chan state | |
451 | * @cookie: transaction identifier to test status of | |
452 | * @last_complete: last know completed transaction | |
453 | * @last_used: last cookie value handed out | |
454 | * | |
455 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 456 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
457 | */ |
458 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
459 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
460 | { | |
461 | if (last_complete <= last_used) { | |
462 | if ((cookie <= last_complete) || (cookie > last_used)) | |
463 | return DMA_SUCCESS; | |
464 | } else { | |
465 | if ((cookie <= last_complete) && (cookie > last_used)) | |
466 | return DMA_SUCCESS; | |
467 | } | |
468 | return DMA_IN_PROGRESS; | |
469 | } | |
470 | ||
7405f74b | 471 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
472 | #ifdef CONFIG_DMA_ENGINE |
473 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
474 | #else | |
475 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
476 | { | |
477 | return DMA_SUCCESS; | |
478 | } | |
479 | #endif | |
c13c8260 CL |
480 | |
481 | /* --- DMA device --- */ | |
482 | ||
483 | int dma_async_device_register(struct dma_device *device); | |
484 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 485 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 486 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
2ba05622 | 487 | void dma_issue_pending_all(void); |
59b5ec21 DW |
488 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
489 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
490 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 491 | |
de5506e1 CL |
492 | /* --- Helper iov-locking functions --- */ |
493 | ||
494 | struct dma_page_list { | |
b2ddb901 | 495 | char __user *base_address; |
de5506e1 CL |
496 | int nr_pages; |
497 | struct page **pages; | |
498 | }; | |
499 | ||
500 | struct dma_pinned_list { | |
501 | int nr_iovecs; | |
502 | struct dma_page_list page_list[0]; | |
503 | }; | |
504 | ||
505 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
506 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
507 | ||
508 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
509 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
510 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
511 | struct dma_pinned_list *pinned_list, struct page *page, | |
512 | unsigned int offset, size_t len); | |
513 | ||
c13c8260 | 514 | #endif /* DMAENGINE_H */ |