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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
7405f74b | 26 | #include <linux/dma-mapping.h> |
c13c8260 | 27 | |
c13c8260 | 28 | /** |
fe4ada2d | 29 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
30 | * |
31 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
32 | */ | |
33 | typedef s32 dma_cookie_t; | |
76bd061f SM |
34 | #define DMA_MIN_COOKIE 1 |
35 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 CL |
36 | |
37 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
38 | ||
39 | /** | |
40 | * enum dma_status - DMA transaction status | |
41 | * @DMA_SUCCESS: transaction completed successfully | |
42 | * @DMA_IN_PROGRESS: transaction not yet processed | |
07934481 | 43 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
44 | * @DMA_ERROR: transaction failed |
45 | */ | |
46 | enum dma_status { | |
47 | DMA_SUCCESS, | |
48 | DMA_IN_PROGRESS, | |
07934481 | 49 | DMA_PAUSED, |
c13c8260 CL |
50 | DMA_ERROR, |
51 | }; | |
52 | ||
7405f74b DW |
53 | /** |
54 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
55 | * |
56 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
57 | * automatically set as dma devices are registered. | |
7405f74b DW |
58 | */ |
59 | enum dma_transaction_type { | |
60 | DMA_MEMCPY, | |
61 | DMA_XOR, | |
b2f46fd8 | 62 | DMA_PQ, |
099f53cb DW |
63 | DMA_XOR_VAL, |
64 | DMA_PQ_VAL, | |
7405f74b | 65 | DMA_MEMSET, |
7405f74b | 66 | DMA_INTERRUPT, |
59b5ec21 | 67 | DMA_PRIVATE, |
138f4c35 | 68 | DMA_ASYNC_TX, |
dc0ee643 | 69 | DMA_SLAVE, |
782bc950 | 70 | DMA_CYCLIC, |
7405f74b DW |
71 | }; |
72 | ||
73 | /* last transaction type for creation of the capabilities mask */ | |
782bc950 | 74 | #define DMA_TX_TYPE_END (DMA_CYCLIC + 1) |
dc0ee643 | 75 | |
7405f74b | 76 | |
d4c56f97 | 77 | /** |
636bdeaa | 78 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 79 | * control completion, and communicate status. |
d4c56f97 | 80 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 81 | * this transaction |
a88f6667 | 82 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
83 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
84 | * chains | |
e1d181ef DW |
85 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
86 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
4f005dbe MS |
87 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
88 | * (if not set, do the source dma-unmapping as page) | |
89 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single | |
90 | * (if not set, do the destination dma-unmapping as page) | |
b2f46fd8 DW |
91 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
92 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
93 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
94 | * sources that were the result of a previous operation, in the case of a PQ | |
95 | * operation it continues the calculation with new sources | |
0403e382 DW |
96 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
97 | * on the result of this operation | |
d4c56f97 | 98 | */ |
636bdeaa | 99 | enum dma_ctrl_flags { |
d4c56f97 | 100 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 101 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
102 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
103 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
4f005dbe MS |
104 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
105 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), | |
f9dd2134 DW |
106 | DMA_PREP_PQ_DISABLE_P = (1 << 6), |
107 | DMA_PREP_PQ_DISABLE_Q = (1 << 7), | |
108 | DMA_PREP_CONTINUE = (1 << 8), | |
0403e382 | 109 | DMA_PREP_FENCE = (1 << 9), |
d4c56f97 DW |
110 | }; |
111 | ||
c3635c78 LW |
112 | /** |
113 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised | |
114 | * on a running channel. | |
115 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers | |
116 | * @DMA_PAUSE: pause ongoing transfers | |
117 | * @DMA_RESUME: resume paused transfer | |
c156d0a5 LW |
118 | * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers |
119 | * that need to runtime reconfigure the slave channels (as opposed to passing | |
120 | * configuration data in statically from the platform). An additional | |
121 | * argument of struct dma_slave_config must be passed in with this | |
122 | * command. | |
c3635c78 LW |
123 | */ |
124 | enum dma_ctrl_cmd { | |
125 | DMA_TERMINATE_ALL, | |
126 | DMA_PAUSE, | |
127 | DMA_RESUME, | |
c156d0a5 | 128 | DMA_SLAVE_CONFIG, |
c3635c78 LW |
129 | }; |
130 | ||
ad283ea4 DW |
131 | /** |
132 | * enum sum_check_bits - bit position of pq_check_flags | |
133 | */ | |
134 | enum sum_check_bits { | |
135 | SUM_CHECK_P = 0, | |
136 | SUM_CHECK_Q = 1, | |
137 | }; | |
138 | ||
139 | /** | |
140 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
141 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
142 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
143 | */ | |
144 | enum sum_check_flags { | |
145 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
146 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
147 | }; | |
148 | ||
149 | ||
7405f74b DW |
150 | /** |
151 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
152 | * See linux/cpumask.h | |
153 | */ | |
154 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
155 | ||
c13c8260 CL |
156 | /** |
157 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
158 | * @memcpy_count: transaction counter |
159 | * @bytes_transferred: byte counter | |
160 | */ | |
161 | ||
162 | struct dma_chan_percpu { | |
c13c8260 CL |
163 | /* stats */ |
164 | unsigned long memcpy_count; | |
165 | unsigned long bytes_transferred; | |
166 | }; | |
167 | ||
168 | /** | |
169 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 170 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 171 | * @cookie: last cookie value returned to client |
fe4ada2d | 172 | * @chan_id: channel ID for sysfs |
41d5e59c | 173 | * @dev: class device for sysfs |
c13c8260 CL |
174 | * @device_node: used to add this to the device chan list |
175 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 176 | * @client-count: how many clients are using this channel |
bec08513 | 177 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 178 | * @private: private data for certain client-channel associations |
c13c8260 CL |
179 | */ |
180 | struct dma_chan { | |
c13c8260 CL |
181 | struct dma_device *device; |
182 | dma_cookie_t cookie; | |
183 | ||
184 | /* sysfs */ | |
185 | int chan_id; | |
41d5e59c | 186 | struct dma_chan_dev *dev; |
c13c8260 | 187 | |
c13c8260 | 188 | struct list_head device_node; |
a29d8b8e | 189 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 190 | int client_count; |
bec08513 | 191 | int table_count; |
287d8592 | 192 | void *private; |
c13c8260 CL |
193 | }; |
194 | ||
41d5e59c DW |
195 | /** |
196 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
197 | * @chan - driver channel device | |
198 | * @device - sysfs device | |
864498aa DW |
199 | * @dev_id - parent dma_device dev_id |
200 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
201 | */ |
202 | struct dma_chan_dev { | |
203 | struct dma_chan *chan; | |
204 | struct device device; | |
864498aa DW |
205 | int dev_id; |
206 | atomic_t *idr_ref; | |
41d5e59c DW |
207 | }; |
208 | ||
c156d0a5 LW |
209 | /** |
210 | * enum dma_slave_buswidth - defines bus with of the DMA slave | |
211 | * device, source or target buses | |
212 | */ | |
213 | enum dma_slave_buswidth { | |
214 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
215 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
216 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
217 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, | |
218 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
219 | }; | |
220 | ||
221 | /** | |
222 | * struct dma_slave_config - dma slave channel runtime config | |
223 | * @direction: whether the data shall go in or out on this slave | |
224 | * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are | |
225 | * legal values, DMA_BIDIRECTIONAL is not acceptable since we | |
226 | * need to differentiate source and target addresses. | |
227 | * @src_addr: this is the physical address where DMA slave data | |
228 | * should be read (RX), if the source is memory this argument is | |
229 | * ignored. | |
230 | * @dst_addr: this is the physical address where DMA slave data | |
231 | * should be written (TX), if the source is memory this argument | |
232 | * is ignored. | |
233 | * @src_addr_width: this is the width in bytes of the source (RX) | |
234 | * register where DMA data shall be read. If the source | |
235 | * is memory this may be ignored depending on architecture. | |
236 | * Legal values: 1, 2, 4, 8. | |
237 | * @dst_addr_width: same as src_addr_width but for destination | |
238 | * target (TX) mutatis mutandis. | |
239 | * @src_maxburst: the maximum number of words (note: words, as in | |
240 | * units of the src_addr_width member, not bytes) that can be sent | |
241 | * in one burst to the device. Typically something like half the | |
242 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
243 | * may or may not be applicable on memory sources. | |
244 | * @dst_maxburst: same as src_maxburst but for destination target | |
245 | * mutatis mutandis. | |
246 | * | |
247 | * This struct is passed in as configuration data to a DMA engine | |
248 | * in order to set up a certain channel for DMA transport at runtime. | |
249 | * The DMA device/engine has to provide support for an additional | |
250 | * command in the channel config interface, DMA_SLAVE_CONFIG | |
251 | * and this struct will then be passed in as an argument to the | |
252 | * DMA engine device_control() function. | |
253 | * | |
254 | * The rationale for adding configuration information to this struct | |
255 | * is as follows: if it is likely that most DMA slave controllers in | |
256 | * the world will support the configuration option, then make it | |
257 | * generic. If not: if it is fixed so that it be sent in static from | |
258 | * the platform data, then prefer to do that. Else, if it is neither | |
259 | * fixed at runtime, nor generic enough (such as bus mastership on | |
260 | * some CPU family and whatnot) then create a custom slave config | |
261 | * struct and pass that, then make this config a member of that | |
262 | * struct, if applicable. | |
263 | */ | |
264 | struct dma_slave_config { | |
265 | enum dma_data_direction direction; | |
266 | dma_addr_t src_addr; | |
267 | dma_addr_t dst_addr; | |
268 | enum dma_slave_buswidth src_addr_width; | |
269 | enum dma_slave_buswidth dst_addr_width; | |
270 | u32 src_maxburst; | |
271 | u32 dst_maxburst; | |
272 | }; | |
273 | ||
41d5e59c DW |
274 | static inline const char *dma_chan_name(struct dma_chan *chan) |
275 | { | |
276 | return dev_name(&chan->dev->device); | |
277 | } | |
d379b01e | 278 | |
c13c8260 CL |
279 | void dma_chan_cleanup(struct kref *kref); |
280 | ||
59b5ec21 DW |
281 | /** |
282 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
283 | * @chan: channel to be reviewed | |
284 | * @filter_param: opaque parameter passed through dma_request_channel | |
285 | * | |
286 | * When this optional parameter is specified in a call to dma_request_channel a | |
287 | * suitable channel is passed to this routine for further dispositioning before | |
288 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
289 | * satisfies the given capability mask. It returns 'true' to indicate that the |
290 | * channel is suitable. | |
59b5ec21 | 291 | */ |
7dd60251 | 292 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 293 | |
7405f74b DW |
294 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
295 | /** | |
296 | * struct dma_async_tx_descriptor - async transaction descriptor | |
297 | * ---dma generic offload fields--- | |
298 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
299 | * this tx is sitting on a dependency list | |
636bdeaa DW |
300 | * @flags: flags to augment operation preparation, control completion, and |
301 | * communicate status | |
7405f74b | 302 | * @phys: physical address of the descriptor |
7405f74b DW |
303 | * @chan: target channel for this operation |
304 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
305 | * @callback: routine to call after this operation is complete |
306 | * @callback_param: general parameter to pass to the callback routine | |
307 | * ---async_tx api specific fields--- | |
19242d72 | 308 | * @next: at completion submit this descriptor |
7405f74b | 309 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 310 | * @lock: protect the parent and next pointers |
7405f74b DW |
311 | */ |
312 | struct dma_async_tx_descriptor { | |
313 | dma_cookie_t cookie; | |
636bdeaa | 314 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 315 | dma_addr_t phys; |
7405f74b DW |
316 | struct dma_chan *chan; |
317 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
318 | dma_async_tx_callback callback; |
319 | void *callback_param; | |
caa20d97 | 320 | #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
19242d72 | 321 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
322 | struct dma_async_tx_descriptor *parent; |
323 | spinlock_t lock; | |
caa20d97 | 324 | #endif |
7405f74b DW |
325 | }; |
326 | ||
caa20d97 DW |
327 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
328 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
329 | { | |
330 | } | |
331 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
332 | { | |
333 | } | |
334 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
335 | { | |
336 | BUG(); | |
337 | } | |
338 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
339 | { | |
340 | } | |
341 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
342 | { | |
343 | } | |
344 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
345 | { | |
346 | return NULL; | |
347 | } | |
348 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
349 | { | |
350 | return NULL; | |
351 | } | |
352 | ||
353 | #else | |
354 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
355 | { | |
356 | spin_lock_bh(&txd->lock); | |
357 | } | |
358 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
359 | { | |
360 | spin_unlock_bh(&txd->lock); | |
361 | } | |
362 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
363 | { | |
364 | txd->next = next; | |
365 | next->parent = txd; | |
366 | } | |
367 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
368 | { | |
369 | txd->parent = NULL; | |
370 | } | |
371 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
372 | { | |
373 | txd->next = NULL; | |
374 | } | |
375 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
376 | { | |
377 | return txd->parent; | |
378 | } | |
379 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
380 | { | |
381 | return txd->next; | |
382 | } | |
383 | #endif | |
384 | ||
07934481 LW |
385 | /** |
386 | * struct dma_tx_state - filled in to report the status of | |
387 | * a transfer. | |
388 | * @last: last completed DMA cookie | |
389 | * @used: last issued DMA cookie (i.e. the one in progress) | |
390 | * @residue: the remaining number of bytes left to transmit | |
391 | * on the selected transfer for states DMA_IN_PROGRESS and | |
392 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
393 | */ | |
394 | struct dma_tx_state { | |
395 | dma_cookie_t last; | |
396 | dma_cookie_t used; | |
397 | u32 residue; | |
398 | }; | |
399 | ||
c13c8260 CL |
400 | /** |
401 | * struct dma_device - info on the entity supplying DMA services | |
402 | * @chancnt: how many DMA channels are supported | |
0f571515 | 403 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
404 | * @channels: the list of struct dma_chan |
405 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
406 | * @cap_mask: one or more dma_capability flags |
407 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 408 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
409 | * @copy_align: alignment shift for memcpy operations |
410 | * @xor_align: alignment shift for xor operations | |
411 | * @pq_align: alignment shift for pq operations | |
412 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 413 | * @dev_id: unique device ID |
7405f74b | 414 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
415 | * @device_alloc_chan_resources: allocate resources and return the |
416 | * number of allocated descriptors | |
417 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
418 | * @device_prep_dma_memcpy: prepares a memcpy operation |
419 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 420 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
421 | * @device_prep_dma_pq: prepares a pq operation |
422 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b DW |
423 | * @device_prep_dma_memset: prepares a memset operation |
424 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 | 425 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
426 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
427 | * The function takes a buffer of size buf_len. The callback function will | |
428 | * be called after period_len bytes have been transferred. | |
c3635c78 LW |
429 | * @device_control: manipulate all pending operations on a channel, returns |
430 | * zero or error code | |
07934481 LW |
431 | * @device_tx_status: poll for transaction completion, the optional |
432 | * txstate parameter can be supplied with a pointer to get a | |
433 | * struct with auxilary transfer status information, otherwise the call | |
434 | * will just return a simple status code | |
7405f74b | 435 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
436 | */ |
437 | struct dma_device { | |
438 | ||
439 | unsigned int chancnt; | |
0f571515 | 440 | unsigned int privatecnt; |
c13c8260 CL |
441 | struct list_head channels; |
442 | struct list_head global_node; | |
7405f74b | 443 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
444 | unsigned short max_xor; |
445 | unsigned short max_pq; | |
83544ae9 DW |
446 | u8 copy_align; |
447 | u8 xor_align; | |
448 | u8 pq_align; | |
449 | u8 fill_align; | |
b2f46fd8 | 450 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 451 | |
c13c8260 | 452 | int dev_id; |
7405f74b | 453 | struct device *dev; |
c13c8260 | 454 | |
aa1e6f1a | 455 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 456 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
457 | |
458 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 459 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 460 | size_t len, unsigned long flags); |
7405f74b | 461 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 462 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 463 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 464 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 465 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 466 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
467 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
468 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
469 | unsigned int src_cnt, const unsigned char *scf, | |
470 | size_t len, unsigned long flags); | |
471 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
472 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
473 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
474 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 475 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 476 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 477 | unsigned long flags); |
7405f74b | 478 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 479 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 480 | |
dc0ee643 HS |
481 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
482 | struct dma_chan *chan, struct scatterlist *sgl, | |
483 | unsigned int sg_len, enum dma_data_direction direction, | |
484 | unsigned long flags); | |
782bc950 SH |
485 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
486 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
487 | size_t period_len, enum dma_data_direction direction); | |
05827630 LW |
488 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
489 | unsigned long arg); | |
dc0ee643 | 490 | |
07934481 LW |
491 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
492 | dma_cookie_t cookie, | |
493 | struct dma_tx_state *txstate); | |
7405f74b | 494 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
495 | }; |
496 | ||
83544ae9 DW |
497 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
498 | { | |
499 | size_t mask; | |
500 | ||
501 | if (!align) | |
502 | return true; | |
503 | mask = (1 << align) - 1; | |
504 | if (mask & (off1 | off2 | len)) | |
505 | return false; | |
506 | return true; | |
507 | } | |
508 | ||
509 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
510 | size_t off2, size_t len) | |
511 | { | |
512 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
513 | } | |
514 | ||
515 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
516 | size_t off2, size_t len) | |
517 | { | |
518 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
519 | } | |
520 | ||
521 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
522 | size_t off2, size_t len) | |
523 | { | |
524 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
525 | } | |
526 | ||
527 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
528 | size_t off2, size_t len) | |
529 | { | |
530 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
531 | } | |
532 | ||
b2f46fd8 DW |
533 | static inline void |
534 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
535 | { | |
536 | dma->max_pq = maxpq; | |
537 | if (has_pq_continue) | |
538 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
539 | } | |
540 | ||
541 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
542 | { | |
543 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
544 | } | |
545 | ||
546 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
547 | { | |
548 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
549 | ||
550 | return (flags & mask) == mask; | |
551 | } | |
552 | ||
553 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
554 | { | |
555 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
556 | } | |
557 | ||
558 | static unsigned short dma_dev_to_maxpq(struct dma_device *dma) | |
559 | { | |
560 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
561 | } | |
562 | ||
563 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
564 | * @dma - dma device with PQ capability | |
565 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
566 | * | |
567 | * When an engine does not support native continuation we need 3 extra | |
568 | * source slots to reuse P and Q with the following coefficients: | |
569 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
570 | * 2/ {01} * Q : use Q to continue Q' calculation | |
571 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
572 | * | |
573 | * In the case where P is disabled we only need 1 extra source: | |
574 | * 1/ {01} * Q : use Q to continue Q' calculation | |
575 | */ | |
576 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
577 | { | |
578 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
579 | return dma_dev_to_maxpq(dma); | |
580 | else if (dmaf_p_disabled_continue(flags)) | |
581 | return dma_dev_to_maxpq(dma) - 1; | |
582 | else if (dmaf_continue(flags)) | |
583 | return dma_dev_to_maxpq(dma) - 3; | |
584 | BUG(); | |
585 | } | |
586 | ||
c13c8260 CL |
587 | /* --- public DMA engine API --- */ |
588 | ||
649274d9 | 589 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
590 | void dmaengine_get(void); |
591 | void dmaengine_put(void); | |
649274d9 DW |
592 | #else |
593 | static inline void dmaengine_get(void) | |
594 | { | |
595 | } | |
596 | static inline void dmaengine_put(void) | |
597 | { | |
598 | } | |
599 | #endif | |
600 | ||
b4bd07c2 DM |
601 | #ifdef CONFIG_NET_DMA |
602 | #define net_dmaengine_get() dmaengine_get() | |
603 | #define net_dmaengine_put() dmaengine_put() | |
604 | #else | |
605 | static inline void net_dmaengine_get(void) | |
606 | { | |
607 | } | |
608 | static inline void net_dmaengine_put(void) | |
609 | { | |
610 | } | |
611 | #endif | |
612 | ||
729b5d1b DW |
613 | #ifdef CONFIG_ASYNC_TX_DMA |
614 | #define async_dmaengine_get() dmaengine_get() | |
615 | #define async_dmaengine_put() dmaengine_put() | |
138f4c35 DW |
616 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
617 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) | |
618 | #else | |
729b5d1b | 619 | #define async_dma_find_channel(type) dma_find_channel(type) |
138f4c35 | 620 | #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
621 | #else |
622 | static inline void async_dmaengine_get(void) | |
623 | { | |
624 | } | |
625 | static inline void async_dmaengine_put(void) | |
626 | { | |
627 | } | |
628 | static inline struct dma_chan * | |
629 | async_dma_find_channel(enum dma_transaction_type type) | |
630 | { | |
631 | return NULL; | |
632 | } | |
138f4c35 | 633 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 634 | |
7405f74b DW |
635 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
636 | void *dest, void *src, size_t len); | |
637 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
638 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
639 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
640 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
641 | unsigned int src_off, size_t len); | |
642 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
643 | struct dma_chan *chan); | |
c13c8260 | 644 | |
0839875e | 645 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 646 | { |
636bdeaa DW |
647 | tx->flags |= DMA_CTRL_ACK; |
648 | } | |
649 | ||
ef560682 GL |
650 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
651 | { | |
652 | tx->flags &= ~DMA_CTRL_ACK; | |
653 | } | |
654 | ||
0839875e | 655 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 656 | { |
0839875e | 657 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
658 | } |
659 | ||
7405f74b DW |
660 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
661 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 662 | { |
7405f74b DW |
663 | return min_t(int, DMA_TX_TYPE_END, |
664 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
665 | } | |
c13c8260 | 666 | |
7405f74b DW |
667 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
668 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
669 | { | |
670 | return min_t(int, DMA_TX_TYPE_END, | |
671 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
672 | } |
673 | ||
7405f74b DW |
674 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
675 | static inline void | |
676 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 677 | { |
7405f74b DW |
678 | set_bit(tx_type, dstp->bits); |
679 | } | |
c13c8260 | 680 | |
0f571515 AN |
681 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
682 | static inline void | |
683 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
684 | { | |
685 | clear_bit(tx_type, dstp->bits); | |
686 | } | |
687 | ||
33df8ca0 DW |
688 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
689 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
690 | { | |
691 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
692 | } | |
693 | ||
7405f74b DW |
694 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
695 | static inline int | |
696 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
697 | { | |
698 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
699 | } |
700 | ||
7405f74b DW |
701 | #define for_each_dma_cap_mask(cap, mask) \ |
702 | for ((cap) = first_dma_cap(mask); \ | |
703 | (cap) < DMA_TX_TYPE_END; \ | |
704 | (cap) = next_dma_cap((cap), (mask))) | |
705 | ||
c13c8260 | 706 | /** |
7405f74b | 707 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 708 | * @chan: target DMA channel |
c13c8260 CL |
709 | * |
710 | * This allows drivers to push copies to HW in batches, | |
711 | * reducing MMIO writes where possible. | |
712 | */ | |
7405f74b | 713 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 714 | { |
ec8670f1 | 715 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
716 | } |
717 | ||
7405f74b DW |
718 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
719 | ||
c13c8260 | 720 | /** |
7405f74b | 721 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
722 | * @chan: DMA channel |
723 | * @cookie: transaction identifier to check status of | |
724 | * @last: returns last completed cookie, can be NULL | |
725 | * @used: returns last issued cookie, can be NULL | |
726 | * | |
727 | * If @last and @used are passed in, upon return they reflect the driver | |
728 | * internal state and can be used with dma_async_is_complete() to check | |
729 | * the status of multiple cookies without re-checking hardware state. | |
730 | */ | |
7405f74b | 731 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
732 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
733 | { | |
07934481 LW |
734 | struct dma_tx_state state; |
735 | enum dma_status status; | |
736 | ||
737 | status = chan->device->device_tx_status(chan, cookie, &state); | |
738 | if (last) | |
739 | *last = state.last; | |
740 | if (used) | |
741 | *used = state.used; | |
742 | return status; | |
c13c8260 CL |
743 | } |
744 | ||
7405f74b DW |
745 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
746 | dma_async_is_tx_complete(chan, cookie, last, used) | |
747 | ||
c13c8260 CL |
748 | /** |
749 | * dma_async_is_complete - test a cookie against chan state | |
750 | * @cookie: transaction identifier to test status of | |
751 | * @last_complete: last know completed transaction | |
752 | * @last_used: last cookie value handed out | |
753 | * | |
754 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 755 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
756 | */ |
757 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
758 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
759 | { | |
760 | if (last_complete <= last_used) { | |
761 | if ((cookie <= last_complete) || (cookie > last_used)) | |
762 | return DMA_SUCCESS; | |
763 | } else { | |
764 | if ((cookie <= last_complete) && (cookie > last_used)) | |
765 | return DMA_SUCCESS; | |
766 | } | |
767 | return DMA_IN_PROGRESS; | |
768 | } | |
769 | ||
bca34692 DW |
770 | static inline void |
771 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
772 | { | |
773 | if (st) { | |
774 | st->last = last; | |
775 | st->used = used; | |
776 | st->residue = residue; | |
777 | } | |
778 | } | |
779 | ||
7405f74b | 780 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
781 | #ifdef CONFIG_DMA_ENGINE |
782 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 783 | void dma_issue_pending_all(void); |
07f2211e DW |
784 | #else |
785 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
786 | { | |
787 | return DMA_SUCCESS; | |
788 | } | |
c50331e8 DW |
789 | static inline void dma_issue_pending_all(void) |
790 | { | |
791 | do { } while (0); | |
792 | } | |
07f2211e | 793 | #endif |
c13c8260 CL |
794 | |
795 | /* --- DMA device --- */ | |
796 | ||
797 | int dma_async_device_register(struct dma_device *device); | |
798 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 799 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 800 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
59b5ec21 DW |
801 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
802 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
803 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 804 | |
de5506e1 CL |
805 | /* --- Helper iov-locking functions --- */ |
806 | ||
807 | struct dma_page_list { | |
b2ddb901 | 808 | char __user *base_address; |
de5506e1 CL |
809 | int nr_pages; |
810 | struct page **pages; | |
811 | }; | |
812 | ||
813 | struct dma_pinned_list { | |
814 | int nr_iovecs; | |
815 | struct dma_page_list page_list[0]; | |
816 | }; | |
817 | ||
818 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
819 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
820 | ||
821 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
822 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
823 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
824 | struct dma_pinned_list *pinned_list, struct page *page, | |
825 | unsigned int offset, size_t len); | |
826 | ||
c13c8260 | 827 | #endif /* DMAENGINE_H */ |