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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
c13c8260 CL |
14 | * The full GNU General Public License is included in this distribution in the |
15 | * file called COPYING. | |
16 | */ | |
d2ebfb33 RKAL |
17 | #ifndef LINUX_DMAENGINE_H |
18 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 19 | |
c13c8260 | 20 | #include <linux/device.h> |
0ad7c000 | 21 | #include <linux/err.h> |
c13c8260 | 22 | #include <linux/uio.h> |
187f1882 | 23 | #include <linux/bug.h> |
90b44f8f | 24 | #include <linux/scatterlist.h> |
a8efa9d6 | 25 | #include <linux/bitmap.h> |
dcc043dc | 26 | #include <linux/types.h> |
a8efa9d6 | 27 | #include <asm/page.h> |
b7f080cf | 28 | |
c13c8260 | 29 | /** |
fe4ada2d | 30 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
31 | * |
32 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
33 | */ | |
34 | typedef s32 dma_cookie_t; | |
76bd061f | 35 | #define DMA_MIN_COOKIE 1 |
c13c8260 | 36 | |
71ea1483 DC |
37 | static inline int dma_submit_error(dma_cookie_t cookie) |
38 | { | |
39 | return cookie < 0 ? cookie : 0; | |
40 | } | |
c13c8260 CL |
41 | |
42 | /** | |
43 | * enum dma_status - DMA transaction status | |
adfedd9a | 44 | * @DMA_COMPLETE: transaction completed |
c13c8260 | 45 | * @DMA_IN_PROGRESS: transaction not yet processed |
07934481 | 46 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
47 | * @DMA_ERROR: transaction failed |
48 | */ | |
49 | enum dma_status { | |
7db5f727 | 50 | DMA_COMPLETE, |
c13c8260 | 51 | DMA_IN_PROGRESS, |
07934481 | 52 | DMA_PAUSED, |
c13c8260 CL |
53 | DMA_ERROR, |
54 | }; | |
55 | ||
7405f74b DW |
56 | /** |
57 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
58 | * |
59 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
60 | * automatically set as dma devices are registered. | |
7405f74b DW |
61 | */ |
62 | enum dma_transaction_type { | |
63 | DMA_MEMCPY, | |
64 | DMA_XOR, | |
b2f46fd8 | 65 | DMA_PQ, |
099f53cb DW |
66 | DMA_XOR_VAL, |
67 | DMA_PQ_VAL, | |
4983a501 | 68 | DMA_MEMSET, |
50c7cd2b | 69 | DMA_MEMSET_SG, |
7405f74b | 70 | DMA_INTERRUPT, |
a86ee03c | 71 | DMA_SG, |
59b5ec21 | 72 | DMA_PRIVATE, |
138f4c35 | 73 | DMA_ASYNC_TX, |
dc0ee643 | 74 | DMA_SLAVE, |
782bc950 | 75 | DMA_CYCLIC, |
b14dab79 | 76 | DMA_INTERLEAVE, |
7405f74b | 77 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
78 | DMA_TX_TYPE_END, |
79 | }; | |
dc0ee643 | 80 | |
49920bc6 VK |
81 | /** |
82 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
83 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
84 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
85 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
86 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
87 | */ | |
88 | enum dma_transfer_direction { | |
89 | DMA_MEM_TO_MEM, | |
90 | DMA_MEM_TO_DEV, | |
91 | DMA_DEV_TO_MEM, | |
92 | DMA_DEV_TO_DEV, | |
62268ce9 | 93 | DMA_TRANS_NONE, |
49920bc6 | 94 | }; |
7405f74b | 95 | |
b14dab79 JB |
96 | /** |
97 | * Interleaved Transfer Request | |
98 | * ---------------------------- | |
99 | * A chunk is collection of contiguous bytes to be transfered. | |
100 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
101 | * ICGs may or maynot change between chunks. | |
102 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
103 | * that when repeated an integral number of times, specifies the transfer. | |
104 | * A transfer template is specification of a Frame, the number of times | |
105 | * it is to be repeated and other per-transfer attributes. | |
106 | * | |
107 | * Practically, a client driver would have ready a template for each | |
108 | * type of transfer it is going to need during its lifetime and | |
109 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
110 | * | |
111 | * | |
112 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
113 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
114 | * | |
115 | * == Chunk size | |
116 | * ... ICG | |
117 | */ | |
118 | ||
119 | /** | |
120 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
121 | * @size: Number of bytes to read from source. | |
122 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
123 | * @icg: Number of bytes to jump after last src/dst address of this | |
124 | * chunk and before first src/dst address for next chunk. | |
125 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
126 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
e1031dc1 MR |
127 | * @dst_icg: Number of bytes to jump after last dst address of this |
128 | * chunk and before the first dst address for next chunk. | |
129 | * Ignored if dst_inc is true and dst_sgl is false. | |
130 | * @src_icg: Number of bytes to jump after last src address of this | |
131 | * chunk and before the first src address for next chunk. | |
132 | * Ignored if src_inc is true and src_sgl is false. | |
b14dab79 JB |
133 | */ |
134 | struct data_chunk { | |
135 | size_t size; | |
136 | size_t icg; | |
e1031dc1 MR |
137 | size_t dst_icg; |
138 | size_t src_icg; | |
b14dab79 JB |
139 | }; |
140 | ||
141 | /** | |
142 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
143 | * and attributes. | |
144 | * @src_start: Bus address of source for the first chunk. | |
145 | * @dst_start: Bus address of destination for the first chunk. | |
146 | * @dir: Specifies the type of Source and Destination. | |
147 | * @src_inc: If the source address increments after reading from it. | |
148 | * @dst_inc: If the destination address increments after writing to it. | |
149 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
150 | * Otherwise, source is read contiguously (icg ignored). | |
151 | * Ignored if src_inc is false. | |
152 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
153 | * Otherwise, destination is filled contiguously (icg ignored). | |
154 | * Ignored if dst_inc is false. | |
155 | * @numf: Number of frames in this template. | |
156 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
157 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
158 | */ | |
159 | struct dma_interleaved_template { | |
160 | dma_addr_t src_start; | |
161 | dma_addr_t dst_start; | |
162 | enum dma_transfer_direction dir; | |
163 | bool src_inc; | |
164 | bool dst_inc; | |
165 | bool src_sgl; | |
166 | bool dst_sgl; | |
167 | size_t numf; | |
168 | size_t frame_size; | |
169 | struct data_chunk sgl[0]; | |
170 | }; | |
171 | ||
d4c56f97 | 172 | /** |
636bdeaa | 173 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 174 | * control completion, and communicate status. |
d4c56f97 | 175 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 176 | * this transaction |
a88f6667 | 177 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
178 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
179 | * chains | |
b2f46fd8 DW |
180 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
181 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
182 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
183 | * sources that were the result of a previous operation, in the case of a PQ | |
184 | * operation it continues the calculation with new sources | |
0403e382 DW |
185 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
186 | * on the result of this operation | |
27242021 VK |
187 | * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till |
188 | * cleared or freed | |
d4c56f97 | 189 | */ |
636bdeaa | 190 | enum dma_ctrl_flags { |
d4c56f97 | 191 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 192 | DMA_CTRL_ACK = (1 << 1), |
0776ae7b BZ |
193 | DMA_PREP_PQ_DISABLE_P = (1 << 2), |
194 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
195 | DMA_PREP_CONTINUE = (1 << 4), | |
196 | DMA_PREP_FENCE = (1 << 5), | |
27242021 | 197 | DMA_CTRL_REUSE = (1 << 6), |
d4c56f97 DW |
198 | }; |
199 | ||
ad283ea4 DW |
200 | /** |
201 | * enum sum_check_bits - bit position of pq_check_flags | |
202 | */ | |
203 | enum sum_check_bits { | |
204 | SUM_CHECK_P = 0, | |
205 | SUM_CHECK_Q = 1, | |
206 | }; | |
207 | ||
208 | /** | |
209 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
210 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
211 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
212 | */ | |
213 | enum sum_check_flags { | |
214 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
215 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
216 | }; | |
217 | ||
218 | ||
7405f74b DW |
219 | /** |
220 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
221 | * See linux/cpumask.h | |
222 | */ | |
223 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
224 | ||
c13c8260 CL |
225 | /** |
226 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
227 | * @memcpy_count: transaction counter |
228 | * @bytes_transferred: byte counter | |
229 | */ | |
230 | ||
231 | struct dma_chan_percpu { | |
c13c8260 CL |
232 | /* stats */ |
233 | unsigned long memcpy_count; | |
234 | unsigned long bytes_transferred; | |
235 | }; | |
236 | ||
56f13c0d PU |
237 | /** |
238 | * struct dma_router - DMA router structure | |
239 | * @dev: pointer to the DMA router device | |
240 | * @route_free: function to be called when the route can be disconnected | |
241 | */ | |
242 | struct dma_router { | |
243 | struct device *dev; | |
244 | void (*route_free)(struct device *dev, void *route_data); | |
245 | }; | |
246 | ||
c13c8260 CL |
247 | /** |
248 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 249 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 250 | * @cookie: last cookie value returned to client |
4d4e58de | 251 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 252 | * @chan_id: channel ID for sysfs |
41d5e59c | 253 | * @dev: class device for sysfs |
c13c8260 CL |
254 | * @device_node: used to add this to the device chan list |
255 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
868d2ee2 | 256 | * @client_count: how many clients are using this channel |
bec08513 | 257 | * @table_count: number of appearances in the mem-to-mem allocation table |
56f13c0d PU |
258 | * @router: pointer to the DMA router structure |
259 | * @route_data: channel specific data for the router | |
287d8592 | 260 | * @private: private data for certain client-channel associations |
c13c8260 CL |
261 | */ |
262 | struct dma_chan { | |
c13c8260 CL |
263 | struct dma_device *device; |
264 | dma_cookie_t cookie; | |
4d4e58de | 265 | dma_cookie_t completed_cookie; |
c13c8260 CL |
266 | |
267 | /* sysfs */ | |
268 | int chan_id; | |
41d5e59c | 269 | struct dma_chan_dev *dev; |
c13c8260 | 270 | |
c13c8260 | 271 | struct list_head device_node; |
a29d8b8e | 272 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 273 | int client_count; |
bec08513 | 274 | int table_count; |
56f13c0d PU |
275 | |
276 | /* DMA router */ | |
277 | struct dma_router *router; | |
278 | void *route_data; | |
279 | ||
287d8592 | 280 | void *private; |
c13c8260 CL |
281 | }; |
282 | ||
41d5e59c DW |
283 | /** |
284 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
868d2ee2 VK |
285 | * @chan: driver channel device |
286 | * @device: sysfs device | |
287 | * @dev_id: parent dma_device dev_id | |
288 | * @idr_ref: reference count to gate release of dma_device dev_id | |
41d5e59c DW |
289 | */ |
290 | struct dma_chan_dev { | |
291 | struct dma_chan *chan; | |
292 | struct device device; | |
864498aa DW |
293 | int dev_id; |
294 | atomic_t *idr_ref; | |
41d5e59c DW |
295 | }; |
296 | ||
c156d0a5 | 297 | /** |
ba730340 | 298 | * enum dma_slave_buswidth - defines bus width of the DMA slave |
c156d0a5 LW |
299 | * device, source or target buses |
300 | */ | |
301 | enum dma_slave_buswidth { | |
302 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
303 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
304 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
93c6ee94 | 305 | DMA_SLAVE_BUSWIDTH_3_BYTES = 3, |
c156d0a5 LW |
306 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, |
307 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
534a7298 LP |
308 | DMA_SLAVE_BUSWIDTH_16_BYTES = 16, |
309 | DMA_SLAVE_BUSWIDTH_32_BYTES = 32, | |
310 | DMA_SLAVE_BUSWIDTH_64_BYTES = 64, | |
c156d0a5 LW |
311 | }; |
312 | ||
313 | /** | |
314 | * struct dma_slave_config - dma slave channel runtime config | |
315 | * @direction: whether the data shall go in or out on this slave | |
397321f4 | 316 | * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are |
d9ff958b LP |
317 | * legal values. DEPRECATED, drivers should use the direction argument |
318 | * to the device_prep_slave_sg and device_prep_dma_cyclic functions or | |
319 | * the dir field in the dma_interleaved_template structure. | |
c156d0a5 LW |
320 | * @src_addr: this is the physical address where DMA slave data |
321 | * should be read (RX), if the source is memory this argument is | |
322 | * ignored. | |
323 | * @dst_addr: this is the physical address where DMA slave data | |
324 | * should be written (TX), if the source is memory this argument | |
325 | * is ignored. | |
326 | * @src_addr_width: this is the width in bytes of the source (RX) | |
327 | * register where DMA data shall be read. If the source | |
328 | * is memory this may be ignored depending on architecture. | |
329 | * Legal values: 1, 2, 4, 8. | |
330 | * @dst_addr_width: same as src_addr_width but for destination | |
331 | * target (TX) mutatis mutandis. | |
332 | * @src_maxburst: the maximum number of words (note: words, as in | |
333 | * units of the src_addr_width member, not bytes) that can be sent | |
334 | * in one burst to the device. Typically something like half the | |
335 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
336 | * may or may not be applicable on memory sources. | |
337 | * @dst_maxburst: same as src_maxburst but for destination target | |
338 | * mutatis mutandis. | |
dcc043dc VK |
339 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
340 | * with 'true' if peripheral should be flow controller. Direction will be | |
341 | * selected at Runtime. | |
4fd1e324 LD |
342 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
343 | * slave peripheral will have unique id as dma requester which need to be | |
344 | * pass as slave config. | |
c156d0a5 LW |
345 | * |
346 | * This struct is passed in as configuration data to a DMA engine | |
347 | * in order to set up a certain channel for DMA transport at runtime. | |
348 | * The DMA device/engine has to provide support for an additional | |
2c44ad91 MR |
349 | * callback in the dma_device structure, device_config and this struct |
350 | * will then be passed in as an argument to the function. | |
c156d0a5 | 351 | * |
7cbccb55 LPC |
352 | * The rationale for adding configuration information to this struct is as |
353 | * follows: if it is likely that more than one DMA slave controllers in | |
354 | * the world will support the configuration option, then make it generic. | |
355 | * If not: if it is fixed so that it be sent in static from the platform | |
356 | * data, then prefer to do that. | |
c156d0a5 LW |
357 | */ |
358 | struct dma_slave_config { | |
49920bc6 | 359 | enum dma_transfer_direction direction; |
c156d0a5 LW |
360 | dma_addr_t src_addr; |
361 | dma_addr_t dst_addr; | |
362 | enum dma_slave_buswidth src_addr_width; | |
363 | enum dma_slave_buswidth dst_addr_width; | |
364 | u32 src_maxburst; | |
365 | u32 dst_maxburst; | |
dcc043dc | 366 | bool device_fc; |
4fd1e324 | 367 | unsigned int slave_id; |
c156d0a5 LW |
368 | }; |
369 | ||
50720563 LPC |
370 | /** |
371 | * enum dma_residue_granularity - Granularity of the reported transfer residue | |
372 | * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The | |
373 | * DMA channel is only able to tell whether a descriptor has been completed or | |
374 | * not, which means residue reporting is not supported by this channel. The | |
375 | * residue field of the dma_tx_state field will always be 0. | |
376 | * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully | |
377 | * completed segment of the transfer (For cyclic transfers this is after each | |
378 | * period). This is typically implemented by having the hardware generate an | |
379 | * interrupt after each transferred segment and then the drivers updates the | |
380 | * outstanding residue by the size of the segment. Another possibility is if | |
381 | * the hardware supports scatter-gather and the segment descriptor has a field | |
382 | * which gets set after the segment has been completed. The driver then counts | |
383 | * the number of segments without the flag set to compute the residue. | |
384 | * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred | |
385 | * burst. This is typically only supported if the hardware has a progress | |
386 | * register of some sort (E.g. a register with the current read/write address | |
387 | * or a register with the amount of bursts/beats/bytes that have been | |
388 | * transferred or still need to be transferred). | |
389 | */ | |
390 | enum dma_residue_granularity { | |
391 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
392 | DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
393 | DMA_RESIDUE_GRANULARITY_BURST = 2, | |
394 | }; | |
395 | ||
221a27c7 VK |
396 | /* struct dma_slave_caps - expose capabilities of a slave channel only |
397 | * | |
398 | * @src_addr_widths: bit mask of src addr widths the channel supports | |
ceacbdbf | 399 | * @dst_addr_widths: bit mask of dstn addr widths the channel supports |
221a27c7 VK |
400 | * @directions: bit mask of slave direction the channel supported |
401 | * since the enum dma_transfer_direction is not defined as bits for each | |
402 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | |
403 | * should be checked by controller as well | |
404 | * @cmd_pause: true, if pause and thereby resume is supported | |
405 | * @cmd_terminate: true, if terminate cmd is supported | |
50720563 | 406 | * @residue_granularity: granularity of the reported transfer residue |
27242021 VK |
407 | * @descriptor_reuse: if a descriptor can be reused by client and |
408 | * resubmitted multiple times | |
221a27c7 VK |
409 | */ |
410 | struct dma_slave_caps { | |
411 | u32 src_addr_widths; | |
ceacbdbf | 412 | u32 dst_addr_widths; |
221a27c7 VK |
413 | u32 directions; |
414 | bool cmd_pause; | |
415 | bool cmd_terminate; | |
50720563 | 416 | enum dma_residue_granularity residue_granularity; |
27242021 | 417 | bool descriptor_reuse; |
221a27c7 VK |
418 | }; |
419 | ||
41d5e59c DW |
420 | static inline const char *dma_chan_name(struct dma_chan *chan) |
421 | { | |
422 | return dev_name(&chan->dev->device); | |
423 | } | |
d379b01e | 424 | |
c13c8260 CL |
425 | void dma_chan_cleanup(struct kref *kref); |
426 | ||
59b5ec21 DW |
427 | /** |
428 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
429 | * @chan: channel to be reviewed | |
430 | * @filter_param: opaque parameter passed through dma_request_channel | |
431 | * | |
432 | * When this optional parameter is specified in a call to dma_request_channel a | |
433 | * suitable channel is passed to this routine for further dispositioning before | |
434 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
435 | * satisfies the given capability mask. It returns 'true' to indicate that the |
436 | * channel is suitable. | |
59b5ec21 | 437 | */ |
7dd60251 | 438 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 439 | |
7405f74b | 440 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
d38a8c62 DW |
441 | |
442 | struct dmaengine_unmap_data { | |
c1f43dd9 | 443 | u8 map_cnt; |
d38a8c62 DW |
444 | u8 to_cnt; |
445 | u8 from_cnt; | |
446 | u8 bidi_cnt; | |
447 | struct device *dev; | |
448 | struct kref kref; | |
449 | size_t len; | |
450 | dma_addr_t addr[0]; | |
451 | }; | |
452 | ||
7405f74b DW |
453 | /** |
454 | * struct dma_async_tx_descriptor - async transaction descriptor | |
455 | * ---dma generic offload fields--- | |
456 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
457 | * this tx is sitting on a dependency list | |
636bdeaa DW |
458 | * @flags: flags to augment operation preparation, control completion, and |
459 | * communicate status | |
7405f74b | 460 | * @phys: physical address of the descriptor |
7405f74b | 461 | * @chan: target channel for this operation |
aba96bad VK |
462 | * @tx_submit: accept the descriptor, assign ordered cookie and mark the |
463 | * descriptor pending. To be pushed on .issue_pending() call | |
7405f74b DW |
464 | * @callback: routine to call after this operation is complete |
465 | * @callback_param: general parameter to pass to the callback routine | |
466 | * ---async_tx api specific fields--- | |
19242d72 | 467 | * @next: at completion submit this descriptor |
7405f74b | 468 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 469 | * @lock: protect the parent and next pointers |
7405f74b DW |
470 | */ |
471 | struct dma_async_tx_descriptor { | |
472 | dma_cookie_t cookie; | |
636bdeaa | 473 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 474 | dma_addr_t phys; |
7405f74b DW |
475 | struct dma_chan *chan; |
476 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
27242021 | 477 | int (*desc_free)(struct dma_async_tx_descriptor *tx); |
7405f74b DW |
478 | dma_async_tx_callback callback; |
479 | void *callback_param; | |
d38a8c62 | 480 | struct dmaengine_unmap_data *unmap; |
5fc6d897 | 481 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 482 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
483 | struct dma_async_tx_descriptor *parent; |
484 | spinlock_t lock; | |
caa20d97 | 485 | #endif |
7405f74b DW |
486 | }; |
487 | ||
89716462 | 488 | #ifdef CONFIG_DMA_ENGINE |
d38a8c62 DW |
489 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, |
490 | struct dmaengine_unmap_data *unmap) | |
491 | { | |
492 | kref_get(&unmap->kref); | |
493 | tx->unmap = unmap; | |
494 | } | |
495 | ||
89716462 DW |
496 | struct dmaengine_unmap_data * |
497 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
45c463ae | 498 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); |
89716462 DW |
499 | #else |
500 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
501 | struct dmaengine_unmap_data *unmap) | |
502 | { | |
503 | } | |
504 | static inline struct dmaengine_unmap_data * | |
505 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
506 | { | |
507 | return NULL; | |
508 | } | |
509 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
510 | { | |
511 | } | |
512 | #endif | |
45c463ae | 513 | |
d38a8c62 DW |
514 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) |
515 | { | |
516 | if (tx->unmap) { | |
45c463ae | 517 | dmaengine_unmap_put(tx->unmap); |
d38a8c62 DW |
518 | tx->unmap = NULL; |
519 | } | |
520 | } | |
521 | ||
5fc6d897 | 522 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
523 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
524 | { | |
525 | } | |
526 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
527 | { | |
528 | } | |
529 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
530 | { | |
531 | BUG(); | |
532 | } | |
533 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
534 | { | |
535 | } | |
536 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
537 | { | |
538 | } | |
539 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
540 | { | |
541 | return NULL; | |
542 | } | |
543 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
544 | { | |
545 | return NULL; | |
546 | } | |
547 | ||
548 | #else | |
549 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
550 | { | |
551 | spin_lock_bh(&txd->lock); | |
552 | } | |
553 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
554 | { | |
555 | spin_unlock_bh(&txd->lock); | |
556 | } | |
557 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
558 | { | |
559 | txd->next = next; | |
560 | next->parent = txd; | |
561 | } | |
562 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
563 | { | |
564 | txd->parent = NULL; | |
565 | } | |
566 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
567 | { | |
568 | txd->next = NULL; | |
569 | } | |
570 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
571 | { | |
572 | return txd->parent; | |
573 | } | |
574 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
575 | { | |
576 | return txd->next; | |
577 | } | |
578 | #endif | |
579 | ||
07934481 LW |
580 | /** |
581 | * struct dma_tx_state - filled in to report the status of | |
582 | * a transfer. | |
583 | * @last: last completed DMA cookie | |
584 | * @used: last issued DMA cookie (i.e. the one in progress) | |
585 | * @residue: the remaining number of bytes left to transmit | |
586 | * on the selected transfer for states DMA_IN_PROGRESS and | |
587 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
588 | */ | |
589 | struct dma_tx_state { | |
590 | dma_cookie_t last; | |
591 | dma_cookie_t used; | |
592 | u32 residue; | |
593 | }; | |
594 | ||
77a68e56 MR |
595 | /** |
596 | * enum dmaengine_alignment - defines alignment of the DMA async tx | |
597 | * buffers | |
598 | */ | |
599 | enum dmaengine_alignment { | |
600 | DMAENGINE_ALIGN_1_BYTE = 0, | |
601 | DMAENGINE_ALIGN_2_BYTES = 1, | |
602 | DMAENGINE_ALIGN_4_BYTES = 2, | |
603 | DMAENGINE_ALIGN_8_BYTES = 3, | |
604 | DMAENGINE_ALIGN_16_BYTES = 4, | |
605 | DMAENGINE_ALIGN_32_BYTES = 5, | |
606 | DMAENGINE_ALIGN_64_BYTES = 6, | |
607 | }; | |
608 | ||
c13c8260 CL |
609 | /** |
610 | * struct dma_device - info on the entity supplying DMA services | |
611 | * @chancnt: how many DMA channels are supported | |
0f571515 | 612 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
613 | * @channels: the list of struct dma_chan |
614 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
615 | * @cap_mask: one or more dma_capability flags |
616 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 617 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
618 | * @copy_align: alignment shift for memcpy operations |
619 | * @xor_align: alignment shift for xor operations | |
620 | * @pq_align: alignment shift for pq operations | |
4983a501 | 621 | * @fill_align: alignment shift for memset operations |
fe4ada2d | 622 | * @dev_id: unique device ID |
7405f74b | 623 | * @dev: struct device reference for dma mapping api |
cb8cea51 MR |
624 | * @src_addr_widths: bit mask of src addr widths the device supports |
625 | * @dst_addr_widths: bit mask of dst addr widths the device supports | |
626 | * @directions: bit mask of slave direction the device supports since | |
627 | * the enum dma_transfer_direction is not defined as bits for | |
628 | * each type of direction, the dma controller should fill (1 << | |
629 | * <TYPE>) and same should be checked by controller as well | |
630 | * @residue_granularity: granularity of the transfer residue reported | |
631 | * by tx_status | |
fe4ada2d RD |
632 | * @device_alloc_chan_resources: allocate resources and return the |
633 | * number of allocated descriptors | |
634 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
635 | * @device_prep_dma_memcpy: prepares a memcpy operation |
636 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 637 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
638 | * @device_prep_dma_pq: prepares a pq operation |
639 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
4983a501 | 640 | * @device_prep_dma_memset: prepares a memset operation |
50c7cd2b | 641 | * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list |
7405f74b | 642 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 643 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
644 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
645 | * The function takes a buffer of size buf_len. The callback function will | |
646 | * be called after period_len bytes have been transferred. | |
b14dab79 | 647 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
94a73e30 MR |
648 | * @device_config: Pushes a new configuration to a channel, return 0 or an error |
649 | * code | |
23a3ea2f MR |
650 | * @device_pause: Pauses any transfer happening on a channel. Returns |
651 | * 0 or an error code | |
652 | * @device_resume: Resumes any transfer on a channel previously | |
653 | * paused. Returns 0 or an error code | |
7fa0cf46 MR |
654 | * @device_terminate_all: Aborts all transfers on a channel. Returns 0 |
655 | * or an error code | |
07934481 LW |
656 | * @device_tx_status: poll for transaction completion, the optional |
657 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 658 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 659 | * will just return a simple status code |
7405f74b | 660 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
661 | */ |
662 | struct dma_device { | |
663 | ||
664 | unsigned int chancnt; | |
0f571515 | 665 | unsigned int privatecnt; |
c13c8260 CL |
666 | struct list_head channels; |
667 | struct list_head global_node; | |
7405f74b | 668 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
669 | unsigned short max_xor; |
670 | unsigned short max_pq; | |
77a68e56 MR |
671 | enum dmaengine_alignment copy_align; |
672 | enum dmaengine_alignment xor_align; | |
673 | enum dmaengine_alignment pq_align; | |
674 | enum dmaengine_alignment fill_align; | |
b2f46fd8 | 675 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 676 | |
c13c8260 | 677 | int dev_id; |
7405f74b | 678 | struct device *dev; |
c13c8260 | 679 | |
cb8cea51 MR |
680 | u32 src_addr_widths; |
681 | u32 dst_addr_widths; | |
682 | u32 directions; | |
683 | enum dma_residue_granularity residue_granularity; | |
684 | ||
aa1e6f1a | 685 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 686 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
687 | |
688 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
ceacbdbf | 689 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
d4c56f97 | 690 | size_t len, unsigned long flags); |
7405f74b | 691 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
ceacbdbf | 692 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
d4c56f97 | 693 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 694 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 695 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 696 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
697 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
698 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
699 | unsigned int src_cnt, const unsigned char *scf, | |
700 | size_t len, unsigned long flags); | |
701 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
702 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
703 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
704 | enum sum_check_flags *pqres, unsigned long flags); | |
4983a501 MR |
705 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
706 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
707 | unsigned long flags); | |
50c7cd2b MR |
708 | struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( |
709 | struct dma_chan *chan, struct scatterlist *sg, | |
710 | unsigned int nents, int value, unsigned long flags); | |
7405f74b | 711 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 712 | struct dma_chan *chan, unsigned long flags); |
a86ee03c IS |
713 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
714 | struct dma_chan *chan, | |
715 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
716 | struct scatterlist *src_sg, unsigned int src_nents, | |
717 | unsigned long flags); | |
7405f74b | 718 | |
dc0ee643 HS |
719 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
720 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 721 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 722 | unsigned long flags, void *context); |
782bc950 SH |
723 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
724 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 725 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 726 | unsigned long flags); |
b14dab79 JB |
727 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
728 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
729 | unsigned long flags); | |
94a73e30 MR |
730 | |
731 | int (*device_config)(struct dma_chan *chan, | |
732 | struct dma_slave_config *config); | |
23a3ea2f MR |
733 | int (*device_pause)(struct dma_chan *chan); |
734 | int (*device_resume)(struct dma_chan *chan); | |
7fa0cf46 | 735 | int (*device_terminate_all)(struct dma_chan *chan); |
dc0ee643 | 736 | |
07934481 LW |
737 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
738 | dma_cookie_t cookie, | |
739 | struct dma_tx_state *txstate); | |
7405f74b | 740 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
741 | }; |
742 | ||
6e3ecaf0 SH |
743 | static inline int dmaengine_slave_config(struct dma_chan *chan, |
744 | struct dma_slave_config *config) | |
745 | { | |
94a73e30 MR |
746 | if (chan->device->device_config) |
747 | return chan->device->device_config(chan, config); | |
748 | ||
2c44ad91 | 749 | return -ENOSYS; |
6e3ecaf0 SH |
750 | } |
751 | ||
61cc13a5 AS |
752 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
753 | { | |
754 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
755 | } | |
756 | ||
90b44f8f | 757 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 758 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 759 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
760 | { |
761 | struct scatterlist sg; | |
922ee08b KM |
762 | sg_init_table(&sg, 1); |
763 | sg_dma_address(&sg) = buf; | |
764 | sg_dma_len(&sg) = len; | |
90b44f8f | 765 | |
185ecb5f AB |
766 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
767 | dir, flags, NULL); | |
90b44f8f VK |
768 | } |
769 | ||
16052827 AB |
770 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
771 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
772 | enum dma_transfer_direction dir, unsigned long flags) | |
773 | { | |
774 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
185ecb5f | 775 | dir, flags, NULL); |
16052827 AB |
776 | } |
777 | ||
e42d98eb AB |
778 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
779 | struct rio_dma_ext; | |
780 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
781 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
782 | enum dma_transfer_direction dir, unsigned long flags, | |
783 | struct rio_dma_ext *rio_ext) | |
784 | { | |
785 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
786 | dir, flags, rio_ext); | |
787 | } | |
788 | #endif | |
789 | ||
16052827 AB |
790 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
791 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
792 | size_t period_len, enum dma_transfer_direction dir, |
793 | unsigned long flags) | |
16052827 AB |
794 | { |
795 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
31c1e5a1 | 796 | period_len, dir, flags); |
a14acb4a BS |
797 | } |
798 | ||
799 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
800 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
801 | unsigned long flags) | |
802 | { | |
803 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
90b44f8f VK |
804 | } |
805 | ||
4983a501 MR |
806 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( |
807 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
808 | unsigned long flags) | |
809 | { | |
810 | if (!chan || !chan->device) | |
811 | return NULL; | |
812 | ||
813 | return chan->device->device_prep_dma_memset(chan, dest, value, | |
814 | len, flags); | |
815 | } | |
816 | ||
b65612a8 VK |
817 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( |
818 | struct dma_chan *chan, | |
819 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
820 | struct scatterlist *src_sg, unsigned int src_nents, | |
821 | unsigned long flags) | |
822 | { | |
823 | return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, | |
824 | src_sg, src_nents, flags); | |
825 | } | |
826 | ||
6e3ecaf0 SH |
827 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
828 | { | |
7fa0cf46 MR |
829 | if (chan->device->device_terminate_all) |
830 | return chan->device->device_terminate_all(chan); | |
831 | ||
2c44ad91 | 832 | return -ENOSYS; |
6e3ecaf0 SH |
833 | } |
834 | ||
835 | static inline int dmaengine_pause(struct dma_chan *chan) | |
836 | { | |
23a3ea2f MR |
837 | if (chan->device->device_pause) |
838 | return chan->device->device_pause(chan); | |
839 | ||
2c44ad91 | 840 | return -ENOSYS; |
6e3ecaf0 SH |
841 | } |
842 | ||
843 | static inline int dmaengine_resume(struct dma_chan *chan) | |
844 | { | |
23a3ea2f MR |
845 | if (chan->device->device_resume) |
846 | return chan->device->device_resume(chan); | |
847 | ||
2c44ad91 | 848 | return -ENOSYS; |
6e3ecaf0 SH |
849 | } |
850 | ||
3052cc2c LPC |
851 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
852 | dma_cookie_t cookie, struct dma_tx_state *state) | |
853 | { | |
854 | return chan->device->device_tx_status(chan, cookie, state); | |
855 | } | |
856 | ||
98d530fe | 857 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
858 | { |
859 | return desc->tx_submit(desc); | |
860 | } | |
861 | ||
77a68e56 MR |
862 | static inline bool dmaengine_check_align(enum dmaengine_alignment align, |
863 | size_t off1, size_t off2, size_t len) | |
83544ae9 DW |
864 | { |
865 | size_t mask; | |
866 | ||
867 | if (!align) | |
868 | return true; | |
869 | mask = (1 << align) - 1; | |
870 | if (mask & (off1 | off2 | len)) | |
871 | return false; | |
872 | return true; | |
873 | } | |
874 | ||
875 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
876 | size_t off2, size_t len) | |
877 | { | |
878 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
879 | } | |
880 | ||
881 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
882 | size_t off2, size_t len) | |
883 | { | |
884 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
885 | } | |
886 | ||
887 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
888 | size_t off2, size_t len) | |
889 | { | |
890 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
891 | } | |
892 | ||
4983a501 MR |
893 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, |
894 | size_t off2, size_t len) | |
895 | { | |
896 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
897 | } | |
898 | ||
b2f46fd8 DW |
899 | static inline void |
900 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
901 | { | |
902 | dma->max_pq = maxpq; | |
903 | if (has_pq_continue) | |
904 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
905 | } | |
906 | ||
907 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
908 | { | |
909 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
910 | } | |
911 | ||
912 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
913 | { | |
914 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
915 | ||
916 | return (flags & mask) == mask; | |
917 | } | |
918 | ||
919 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
920 | { | |
921 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
922 | } | |
923 | ||
d3f3cf85 | 924 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
925 | { |
926 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
927 | } | |
928 | ||
929 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
930 | * @dma - dma device with PQ capability | |
931 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
932 | * | |
933 | * When an engine does not support native continuation we need 3 extra | |
934 | * source slots to reuse P and Q with the following coefficients: | |
935 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
936 | * 2/ {01} * Q : use Q to continue Q' calculation | |
937 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
938 | * | |
939 | * In the case where P is disabled we only need 1 extra source: | |
940 | * 1/ {01} * Q : use Q to continue Q' calculation | |
941 | */ | |
942 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
943 | { | |
944 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
945 | return dma_dev_to_maxpq(dma); | |
946 | else if (dmaf_p_disabled_continue(flags)) | |
947 | return dma_dev_to_maxpq(dma) - 1; | |
948 | else if (dmaf_continue(flags)) | |
949 | return dma_dev_to_maxpq(dma) - 3; | |
950 | BUG(); | |
951 | } | |
952 | ||
87d001ef MR |
953 | static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, |
954 | size_t dir_icg) | |
955 | { | |
956 | if (inc) { | |
957 | if (dir_icg) | |
958 | return dir_icg; | |
959 | else if (sgl) | |
960 | return icg; | |
961 | } | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, | |
967 | struct data_chunk *chunk) | |
968 | { | |
969 | return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, | |
970 | chunk->icg, chunk->dst_icg); | |
971 | } | |
972 | ||
973 | static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, | |
974 | struct data_chunk *chunk) | |
975 | { | |
976 | return dmaengine_get_icg(xt->src_inc, xt->src_sgl, | |
977 | chunk->icg, chunk->src_icg); | |
978 | } | |
979 | ||
c13c8260 CL |
980 | /* --- public DMA engine API --- */ |
981 | ||
649274d9 | 982 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
983 | void dmaengine_get(void); |
984 | void dmaengine_put(void); | |
649274d9 DW |
985 | #else |
986 | static inline void dmaengine_get(void) | |
987 | { | |
988 | } | |
989 | static inline void dmaengine_put(void) | |
990 | { | |
991 | } | |
992 | #endif | |
993 | ||
729b5d1b DW |
994 | #ifdef CONFIG_ASYNC_TX_DMA |
995 | #define async_dmaengine_get() dmaengine_get() | |
996 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 997 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
998 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
999 | #else | |
729b5d1b | 1000 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 1001 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
1002 | #else |
1003 | static inline void async_dmaengine_get(void) | |
1004 | { | |
1005 | } | |
1006 | static inline void async_dmaengine_put(void) | |
1007 | { | |
1008 | } | |
1009 | static inline struct dma_chan * | |
1010 | async_dma_find_channel(enum dma_transaction_type type) | |
1011 | { | |
1012 | return NULL; | |
1013 | } | |
138f4c35 | 1014 | #endif /* CONFIG_ASYNC_TX_DMA */ |
7405f74b | 1015 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
7bced397 | 1016 | struct dma_chan *chan); |
c13c8260 | 1017 | |
0839875e | 1018 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 1019 | { |
636bdeaa DW |
1020 | tx->flags |= DMA_CTRL_ACK; |
1021 | } | |
1022 | ||
ef560682 GL |
1023 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
1024 | { | |
1025 | tx->flags &= ~DMA_CTRL_ACK; | |
1026 | } | |
1027 | ||
0839875e | 1028 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 1029 | { |
0839875e | 1030 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
1031 | } |
1032 | ||
7405f74b DW |
1033 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
1034 | static inline void | |
1035 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 1036 | { |
7405f74b DW |
1037 | set_bit(tx_type, dstp->bits); |
1038 | } | |
c13c8260 | 1039 | |
0f571515 AN |
1040 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
1041 | static inline void | |
1042 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
1043 | { | |
1044 | clear_bit(tx_type, dstp->bits); | |
1045 | } | |
1046 | ||
33df8ca0 DW |
1047 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
1048 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
1049 | { | |
1050 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
1051 | } | |
1052 | ||
7405f74b DW |
1053 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
1054 | static inline int | |
1055 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
1056 | { | |
1057 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
1058 | } |
1059 | ||
7405f74b | 1060 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 1061 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 1062 | |
c13c8260 | 1063 | /** |
7405f74b | 1064 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 1065 | * @chan: target DMA channel |
c13c8260 CL |
1066 | * |
1067 | * This allows drivers to push copies to HW in batches, | |
1068 | * reducing MMIO writes where possible. | |
1069 | */ | |
7405f74b | 1070 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 1071 | { |
ec8670f1 | 1072 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
1073 | } |
1074 | ||
1075 | /** | |
7405f74b | 1076 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
1077 | * @chan: DMA channel |
1078 | * @cookie: transaction identifier to check status of | |
1079 | * @last: returns last completed cookie, can be NULL | |
1080 | * @used: returns last issued cookie, can be NULL | |
1081 | * | |
1082 | * If @last and @used are passed in, upon return they reflect the driver | |
1083 | * internal state and can be used with dma_async_is_complete() to check | |
1084 | * the status of multiple cookies without re-checking hardware state. | |
1085 | */ | |
7405f74b | 1086 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
1087 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
1088 | { | |
07934481 LW |
1089 | struct dma_tx_state state; |
1090 | enum dma_status status; | |
1091 | ||
1092 | status = chan->device->device_tx_status(chan, cookie, &state); | |
1093 | if (last) | |
1094 | *last = state.last; | |
1095 | if (used) | |
1096 | *used = state.used; | |
1097 | return status; | |
c13c8260 CL |
1098 | } |
1099 | ||
1100 | /** | |
1101 | * dma_async_is_complete - test a cookie against chan state | |
1102 | * @cookie: transaction identifier to test status of | |
1103 | * @last_complete: last know completed transaction | |
1104 | * @last_used: last cookie value handed out | |
1105 | * | |
e239345f | 1106 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 1107 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
1108 | */ |
1109 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1110 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1111 | { | |
1112 | if (last_complete <= last_used) { | |
1113 | if ((cookie <= last_complete) || (cookie > last_used)) | |
adfedd9a | 1114 | return DMA_COMPLETE; |
c13c8260 CL |
1115 | } else { |
1116 | if ((cookie <= last_complete) && (cookie > last_used)) | |
adfedd9a | 1117 | return DMA_COMPLETE; |
c13c8260 CL |
1118 | } |
1119 | return DMA_IN_PROGRESS; | |
1120 | } | |
1121 | ||
bca34692 DW |
1122 | static inline void |
1123 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1124 | { | |
1125 | if (st) { | |
1126 | st->last = last; | |
1127 | st->used = used; | |
1128 | st->residue = residue; | |
1129 | } | |
1130 | } | |
1131 | ||
07f2211e | 1132 | #ifdef CONFIG_DMA_ENGINE |
4a43f394 JM |
1133 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
1134 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
07f2211e | 1135 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
c50331e8 | 1136 | void dma_issue_pending_all(void); |
a53e28da LPC |
1137 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
1138 | dma_filter_fn fn, void *fn_param); | |
0ad7c000 SW |
1139 | struct dma_chan *dma_request_slave_channel_reason(struct device *dev, |
1140 | const char *name); | |
bef29ec5 | 1141 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
8f33d527 | 1142 | void dma_release_channel(struct dma_chan *chan); |
fdb8df99 | 1143 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); |
07f2211e | 1144 | #else |
4a43f394 JM |
1145 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) |
1146 | { | |
1147 | return NULL; | |
1148 | } | |
1149 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1150 | { | |
adfedd9a | 1151 | return DMA_COMPLETE; |
4a43f394 | 1152 | } |
07f2211e DW |
1153 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1154 | { | |
adfedd9a | 1155 | return DMA_COMPLETE; |
07f2211e | 1156 | } |
c50331e8 DW |
1157 | static inline void dma_issue_pending_all(void) |
1158 | { | |
8f33d527 | 1159 | } |
a53e28da | 1160 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
8f33d527 GL |
1161 | dma_filter_fn fn, void *fn_param) |
1162 | { | |
1163 | return NULL; | |
1164 | } | |
0ad7c000 SW |
1165 | static inline struct dma_chan *dma_request_slave_channel_reason( |
1166 | struct device *dev, const char *name) | |
1167 | { | |
1168 | return ERR_PTR(-ENODEV); | |
1169 | } | |
9a6cecc8 | 1170 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 1171 | const char *name) |
9a6cecc8 | 1172 | { |
d18d5f59 | 1173 | return NULL; |
9a6cecc8 | 1174 | } |
8f33d527 GL |
1175 | static inline void dma_release_channel(struct dma_chan *chan) |
1176 | { | |
c50331e8 | 1177 | } |
fdb8df99 LP |
1178 | static inline int dma_get_slave_caps(struct dma_chan *chan, |
1179 | struct dma_slave_caps *caps) | |
1180 | { | |
1181 | return -ENXIO; | |
1182 | } | |
07f2211e | 1183 | #endif |
c13c8260 | 1184 | |
27242021 VK |
1185 | static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) |
1186 | { | |
1187 | struct dma_slave_caps caps; | |
1188 | ||
1189 | dma_get_slave_caps(tx->chan, &caps); | |
1190 | ||
1191 | if (caps.descriptor_reuse) { | |
1192 | tx->flags |= DMA_CTRL_REUSE; | |
1193 | return 0; | |
1194 | } else { | |
1195 | return -EPERM; | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) | |
1200 | { | |
1201 | tx->flags &= ~DMA_CTRL_REUSE; | |
1202 | } | |
1203 | ||
1204 | static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) | |
1205 | { | |
1206 | return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; | |
1207 | } | |
1208 | ||
1209 | static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) | |
1210 | { | |
1211 | /* this is supported for reusable desc, so check that */ | |
1212 | if (dmaengine_desc_test_reuse(desc)) | |
1213 | return desc->desc_free(desc); | |
1214 | else | |
1215 | return -EPERM; | |
1216 | } | |
1217 | ||
c13c8260 CL |
1218 | /* --- DMA device --- */ |
1219 | ||
1220 | int dma_async_device_register(struct dma_device *device); | |
1221 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 1222 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
7bb587f4 | 1223 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
8010dad5 | 1224 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); |
59b5ec21 | 1225 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
864ef69b MP |
1226 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
1227 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1228 | ||
1229 | static inline struct dma_chan | |
a53e28da LPC |
1230 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, |
1231 | dma_filter_fn fn, void *fn_param, | |
1dc04288 | 1232 | struct device *dev, const char *name) |
864ef69b MP |
1233 | { |
1234 | struct dma_chan *chan; | |
1235 | ||
1236 | chan = dma_request_slave_channel(dev, name); | |
1237 | if (chan) | |
1238 | return chan; | |
1239 | ||
1240 | return __dma_request_channel(mask, fn, fn_param); | |
1241 | } | |
c13c8260 | 1242 | #endif /* DMAENGINE_H */ |