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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
7405f74b | 26 | #include <linux/dma-mapping.h> |
c13c8260 | 27 | |
c13c8260 | 28 | /** |
fe4ada2d | 29 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
30 | * |
31 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
32 | */ | |
33 | typedef s32 dma_cookie_t; | |
34 | ||
35 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
36 | ||
37 | /** | |
38 | * enum dma_status - DMA transaction status | |
39 | * @DMA_SUCCESS: transaction completed successfully | |
40 | * @DMA_IN_PROGRESS: transaction not yet processed | |
41 | * @DMA_ERROR: transaction failed | |
42 | */ | |
43 | enum dma_status { | |
44 | DMA_SUCCESS, | |
45 | DMA_IN_PROGRESS, | |
46 | DMA_ERROR, | |
47 | }; | |
48 | ||
7405f74b DW |
49 | /** |
50 | * enum dma_transaction_type - DMA transaction types/indexes | |
51 | */ | |
52 | enum dma_transaction_type { | |
53 | DMA_MEMCPY, | |
54 | DMA_XOR, | |
55 | DMA_PQ_XOR, | |
56 | DMA_DUAL_XOR, | |
57 | DMA_PQ_UPDATE, | |
58 | DMA_ZERO_SUM, | |
59 | DMA_PQ_ZERO_SUM, | |
60 | DMA_MEMSET, | |
61 | DMA_MEMCPY_CRC32C, | |
62 | DMA_INTERRUPT, | |
59b5ec21 | 63 | DMA_PRIVATE, |
dc0ee643 | 64 | DMA_SLAVE, |
7405f74b DW |
65 | }; |
66 | ||
67 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
68 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
69 | ||
7405f74b | 70 | |
d4c56f97 | 71 | /** |
636bdeaa DW |
72 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
73 | * control completion, and communicate status. | |
d4c56f97 DW |
74 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
75 | * this transaction | |
636bdeaa DW |
76 | * @DMA_CTRL_ACK - the descriptor cannot be reused until the client |
77 | * acknowledges receipt, i.e. has has a chance to establish any | |
78 | * dependency chains | |
e1d181ef DW |
79 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
80 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
d4c56f97 | 81 | */ |
636bdeaa | 82 | enum dma_ctrl_flags { |
d4c56f97 | 83 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 84 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
85 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
86 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
d4c56f97 DW |
87 | }; |
88 | ||
7405f74b DW |
89 | /** |
90 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
91 | * See linux/cpumask.h | |
92 | */ | |
93 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
94 | ||
c13c8260 CL |
95 | /** |
96 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
97 | * @memcpy_count: transaction counter |
98 | * @bytes_transferred: byte counter | |
99 | */ | |
100 | ||
101 | struct dma_chan_percpu { | |
c13c8260 CL |
102 | /* stats */ |
103 | unsigned long memcpy_count; | |
104 | unsigned long bytes_transferred; | |
105 | }; | |
106 | ||
107 | /** | |
108 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 109 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 110 | * @cookie: last cookie value returned to client |
fe4ada2d | 111 | * @chan_id: channel ID for sysfs |
41d5e59c | 112 | * @dev: class device for sysfs |
c13c8260 CL |
113 | * @device_node: used to add this to the device chan list |
114 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 115 | * @client-count: how many clients are using this channel |
bec08513 | 116 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 117 | * @private: private data for certain client-channel associations |
c13c8260 CL |
118 | */ |
119 | struct dma_chan { | |
c13c8260 CL |
120 | struct dma_device *device; |
121 | dma_cookie_t cookie; | |
122 | ||
123 | /* sysfs */ | |
124 | int chan_id; | |
41d5e59c | 125 | struct dma_chan_dev *dev; |
c13c8260 | 126 | |
c13c8260 CL |
127 | struct list_head device_node; |
128 | struct dma_chan_percpu *local; | |
7cc5bf9a | 129 | int client_count; |
bec08513 | 130 | int table_count; |
287d8592 | 131 | void *private; |
c13c8260 CL |
132 | }; |
133 | ||
41d5e59c DW |
134 | /** |
135 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
136 | * @chan - driver channel device | |
137 | * @device - sysfs device | |
864498aa DW |
138 | * @dev_id - parent dma_device dev_id |
139 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
140 | */ |
141 | struct dma_chan_dev { | |
142 | struct dma_chan *chan; | |
143 | struct device device; | |
864498aa DW |
144 | int dev_id; |
145 | atomic_t *idr_ref; | |
41d5e59c DW |
146 | }; |
147 | ||
148 | static inline const char *dma_chan_name(struct dma_chan *chan) | |
149 | { | |
150 | return dev_name(&chan->dev->device); | |
151 | } | |
d379b01e | 152 | |
c13c8260 CL |
153 | void dma_chan_cleanup(struct kref *kref); |
154 | ||
59b5ec21 DW |
155 | /** |
156 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
157 | * @chan: channel to be reviewed | |
158 | * @filter_param: opaque parameter passed through dma_request_channel | |
159 | * | |
160 | * When this optional parameter is specified in a call to dma_request_channel a | |
161 | * suitable channel is passed to this routine for further dispositioning before | |
162 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
163 | * satisfies the given capability mask. It returns 'true' to indicate that the |
164 | * channel is suitable. | |
59b5ec21 | 165 | */ |
7dd60251 | 166 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 167 | |
7405f74b DW |
168 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
169 | /** | |
170 | * struct dma_async_tx_descriptor - async transaction descriptor | |
171 | * ---dma generic offload fields--- | |
172 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
173 | * this tx is sitting on a dependency list | |
636bdeaa DW |
174 | * @flags: flags to augment operation preparation, control completion, and |
175 | * communicate status | |
7405f74b DW |
176 | * @phys: physical address of the descriptor |
177 | * @tx_list: driver common field for operations that require multiple | |
178 | * descriptors | |
179 | * @chan: target channel for this operation | |
180 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
181 | * @callback: routine to call after this operation is complete |
182 | * @callback_param: general parameter to pass to the callback routine | |
183 | * ---async_tx api specific fields--- | |
19242d72 | 184 | * @next: at completion submit this descriptor |
7405f74b | 185 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 186 | * @lock: protect the parent and next pointers |
7405f74b DW |
187 | */ |
188 | struct dma_async_tx_descriptor { | |
189 | dma_cookie_t cookie; | |
636bdeaa | 190 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b DW |
191 | dma_addr_t phys; |
192 | struct list_head tx_list; | |
193 | struct dma_chan *chan; | |
194 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
195 | dma_async_tx_callback callback; |
196 | void *callback_param; | |
19242d72 | 197 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
198 | struct dma_async_tx_descriptor *parent; |
199 | spinlock_t lock; | |
200 | }; | |
201 | ||
c13c8260 CL |
202 | /** |
203 | * struct dma_device - info on the entity supplying DMA services | |
204 | * @chancnt: how many DMA channels are supported | |
205 | * @channels: the list of struct dma_chan | |
206 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
207 | * @cap_mask: one or more dma_capability flags |
208 | * @max_xor: maximum number of xor sources, 0 if no capability | |
fe4ada2d | 209 | * @dev_id: unique device ID |
7405f74b | 210 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
211 | * @device_alloc_chan_resources: allocate resources and return the |
212 | * number of allocated descriptors | |
213 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
214 | * @device_prep_dma_memcpy: prepares a memcpy operation |
215 | * @device_prep_dma_xor: prepares a xor operation | |
216 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | |
217 | * @device_prep_dma_memset: prepares a memset operation | |
218 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
219 | * @device_prep_slave_sg: prepares a slave dma operation |
220 | * @device_terminate_all: terminate all pending operations | |
1d93e52e | 221 | * @device_is_tx_complete: poll for transaction completion |
7405f74b | 222 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
223 | */ |
224 | struct dma_device { | |
225 | ||
226 | unsigned int chancnt; | |
227 | struct list_head channels; | |
228 | struct list_head global_node; | |
7405f74b DW |
229 | dma_cap_mask_t cap_mask; |
230 | int max_xor; | |
c13c8260 | 231 | |
c13c8260 | 232 | int dev_id; |
7405f74b | 233 | struct device *dev; |
c13c8260 | 234 | |
aa1e6f1a | 235 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 236 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
237 | |
238 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 239 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 240 | size_t len, unsigned long flags); |
7405f74b | 241 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 242 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 243 | unsigned int src_cnt, size_t len, unsigned long flags); |
7405f74b | 244 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
0036731c | 245 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
d4c56f97 | 246 | size_t len, u32 *result, unsigned long flags); |
7405f74b | 247 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 248 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 249 | unsigned long flags); |
7405f74b | 250 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 251 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 252 | |
dc0ee643 HS |
253 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
254 | struct dma_chan *chan, struct scatterlist *sgl, | |
255 | unsigned int sg_len, enum dma_data_direction direction, | |
256 | unsigned long flags); | |
257 | void (*device_terminate_all)(struct dma_chan *chan); | |
258 | ||
7405f74b | 259 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
260 | dma_cookie_t cookie, dma_cookie_t *last, |
261 | dma_cookie_t *used); | |
7405f74b | 262 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
263 | }; |
264 | ||
265 | /* --- public DMA engine API --- */ | |
266 | ||
649274d9 | 267 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
268 | void dmaengine_get(void); |
269 | void dmaengine_put(void); | |
649274d9 DW |
270 | #else |
271 | static inline void dmaengine_get(void) | |
272 | { | |
273 | } | |
274 | static inline void dmaengine_put(void) | |
275 | { | |
276 | } | |
277 | #endif | |
278 | ||
b4bd07c2 DM |
279 | #ifdef CONFIG_NET_DMA |
280 | #define net_dmaengine_get() dmaengine_get() | |
281 | #define net_dmaengine_put() dmaengine_put() | |
282 | #else | |
283 | static inline void net_dmaengine_get(void) | |
284 | { | |
285 | } | |
286 | static inline void net_dmaengine_put(void) | |
287 | { | |
288 | } | |
289 | #endif | |
290 | ||
729b5d1b DW |
291 | #ifdef CONFIG_ASYNC_TX_DMA |
292 | #define async_dmaengine_get() dmaengine_get() | |
293 | #define async_dmaengine_put() dmaengine_put() | |
294 | #define async_dma_find_channel(type) dma_find_channel(type) | |
295 | #else | |
296 | static inline void async_dmaengine_get(void) | |
297 | { | |
298 | } | |
299 | static inline void async_dmaengine_put(void) | |
300 | { | |
301 | } | |
302 | static inline struct dma_chan * | |
303 | async_dma_find_channel(enum dma_transaction_type type) | |
304 | { | |
305 | return NULL; | |
306 | } | |
307 | #endif | |
308 | ||
7405f74b DW |
309 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
310 | void *dest, void *src, size_t len); | |
311 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
312 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
313 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
314 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
315 | unsigned int src_off, size_t len); | |
316 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
317 | struct dma_chan *chan); | |
c13c8260 | 318 | |
0839875e | 319 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 320 | { |
636bdeaa DW |
321 | tx->flags |= DMA_CTRL_ACK; |
322 | } | |
323 | ||
ef560682 GL |
324 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
325 | { | |
326 | tx->flags &= ~DMA_CTRL_ACK; | |
327 | } | |
328 | ||
0839875e | 329 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 330 | { |
0839875e | 331 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
332 | } |
333 | ||
7405f74b DW |
334 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
335 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 336 | { |
7405f74b DW |
337 | return min_t(int, DMA_TX_TYPE_END, |
338 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
339 | } | |
c13c8260 | 340 | |
7405f74b DW |
341 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
342 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
343 | { | |
344 | return min_t(int, DMA_TX_TYPE_END, | |
345 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
346 | } |
347 | ||
7405f74b DW |
348 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
349 | static inline void | |
350 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 351 | { |
7405f74b DW |
352 | set_bit(tx_type, dstp->bits); |
353 | } | |
c13c8260 | 354 | |
33df8ca0 DW |
355 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
356 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
357 | { | |
358 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
359 | } | |
360 | ||
7405f74b DW |
361 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
362 | static inline int | |
363 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
364 | { | |
365 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
366 | } |
367 | ||
7405f74b DW |
368 | #define for_each_dma_cap_mask(cap, mask) \ |
369 | for ((cap) = first_dma_cap(mask); \ | |
370 | (cap) < DMA_TX_TYPE_END; \ | |
371 | (cap) = next_dma_cap((cap), (mask))) | |
372 | ||
c13c8260 | 373 | /** |
7405f74b | 374 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 375 | * @chan: target DMA channel |
c13c8260 CL |
376 | * |
377 | * This allows drivers to push copies to HW in batches, | |
378 | * reducing MMIO writes where possible. | |
379 | */ | |
7405f74b | 380 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 381 | { |
ec8670f1 | 382 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
383 | } |
384 | ||
7405f74b DW |
385 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
386 | ||
c13c8260 | 387 | /** |
7405f74b | 388 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
389 | * @chan: DMA channel |
390 | * @cookie: transaction identifier to check status of | |
391 | * @last: returns last completed cookie, can be NULL | |
392 | * @used: returns last issued cookie, can be NULL | |
393 | * | |
394 | * If @last and @used are passed in, upon return they reflect the driver | |
395 | * internal state and can be used with dma_async_is_complete() to check | |
396 | * the status of multiple cookies without re-checking hardware state. | |
397 | */ | |
7405f74b | 398 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
399 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
400 | { | |
7405f74b | 401 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
402 | } |
403 | ||
7405f74b DW |
404 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
405 | dma_async_is_tx_complete(chan, cookie, last, used) | |
406 | ||
c13c8260 CL |
407 | /** |
408 | * dma_async_is_complete - test a cookie against chan state | |
409 | * @cookie: transaction identifier to test status of | |
410 | * @last_complete: last know completed transaction | |
411 | * @last_used: last cookie value handed out | |
412 | * | |
413 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 414 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
415 | */ |
416 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
417 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
418 | { | |
419 | if (last_complete <= last_used) { | |
420 | if ((cookie <= last_complete) || (cookie > last_used)) | |
421 | return DMA_SUCCESS; | |
422 | } else { | |
423 | if ((cookie <= last_complete) && (cookie > last_used)) | |
424 | return DMA_SUCCESS; | |
425 | } | |
426 | return DMA_IN_PROGRESS; | |
427 | } | |
428 | ||
7405f74b | 429 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
430 | #ifdef CONFIG_DMA_ENGINE |
431 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 432 | void dma_issue_pending_all(void); |
07f2211e DW |
433 | #else |
434 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
435 | { | |
436 | return DMA_SUCCESS; | |
437 | } | |
c50331e8 DW |
438 | static inline void dma_issue_pending_all(void) |
439 | { | |
440 | do { } while (0); | |
441 | } | |
07f2211e | 442 | #endif |
c13c8260 CL |
443 | |
444 | /* --- DMA device --- */ | |
445 | ||
446 | int dma_async_device_register(struct dma_device *device); | |
447 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 448 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 449 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
59b5ec21 DW |
450 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
451 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
452 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 453 | |
de5506e1 CL |
454 | /* --- Helper iov-locking functions --- */ |
455 | ||
456 | struct dma_page_list { | |
b2ddb901 | 457 | char __user *base_address; |
de5506e1 CL |
458 | int nr_pages; |
459 | struct page **pages; | |
460 | }; | |
461 | ||
462 | struct dma_pinned_list { | |
463 | int nr_iovecs; | |
464 | struct dma_page_list page_list[0]; | |
465 | }; | |
466 | ||
467 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
468 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
469 | ||
470 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
471 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
472 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
473 | struct dma_pinned_list *pinned_list, struct page *page, | |
474 | unsigned int offset, size_t len); | |
475 | ||
c13c8260 | 476 | #endif /* DMAENGINE_H */ |