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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
26 | #include <linux/kref.h> | |
27 | #include <linux/completion.h> | |
28 | #include <linux/rcupdate.h> | |
7405f74b | 29 | #include <linux/dma-mapping.h> |
c13c8260 CL |
30 | |
31 | /** | |
fd3f8984 | 32 | * enum dma_state - resource PNP/power management state |
c13c8260 CL |
33 | * @DMA_RESOURCE_SUSPEND: DMA device going into low power state |
34 | * @DMA_RESOURCE_RESUME: DMA device returning to full power | |
d379b01e | 35 | * @DMA_RESOURCE_AVAILABLE: DMA device available to the system |
c13c8260 CL |
36 | * @DMA_RESOURCE_REMOVED: DMA device removed from the system |
37 | */ | |
d379b01e | 38 | enum dma_state { |
c13c8260 CL |
39 | DMA_RESOURCE_SUSPEND, |
40 | DMA_RESOURCE_RESUME, | |
d379b01e | 41 | DMA_RESOURCE_AVAILABLE, |
c13c8260 CL |
42 | DMA_RESOURCE_REMOVED, |
43 | }; | |
44 | ||
d379b01e DW |
45 | /** |
46 | * enum dma_state_client - state of the channel in the client | |
47 | * @DMA_ACK: client would like to use, or was using this channel | |
48 | * @DMA_DUP: client has already seen this channel, or is not using this channel | |
49 | * @DMA_NAK: client does not want to see any more channels | |
50 | */ | |
51 | enum dma_state_client { | |
52 | DMA_ACK, | |
53 | DMA_DUP, | |
54 | DMA_NAK, | |
55 | }; | |
56 | ||
c13c8260 | 57 | /** |
fe4ada2d | 58 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
59 | * |
60 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
61 | */ | |
62 | typedef s32 dma_cookie_t; | |
63 | ||
64 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
65 | ||
66 | /** | |
67 | * enum dma_status - DMA transaction status | |
68 | * @DMA_SUCCESS: transaction completed successfully | |
69 | * @DMA_IN_PROGRESS: transaction not yet processed | |
70 | * @DMA_ERROR: transaction failed | |
71 | */ | |
72 | enum dma_status { | |
73 | DMA_SUCCESS, | |
74 | DMA_IN_PROGRESS, | |
75 | DMA_ERROR, | |
76 | }; | |
77 | ||
7405f74b DW |
78 | /** |
79 | * enum dma_transaction_type - DMA transaction types/indexes | |
80 | */ | |
81 | enum dma_transaction_type { | |
82 | DMA_MEMCPY, | |
83 | DMA_XOR, | |
84 | DMA_PQ_XOR, | |
85 | DMA_DUAL_XOR, | |
86 | DMA_PQ_UPDATE, | |
87 | DMA_ZERO_SUM, | |
88 | DMA_PQ_ZERO_SUM, | |
89 | DMA_MEMSET, | |
90 | DMA_MEMCPY_CRC32C, | |
91 | DMA_INTERRUPT, | |
dc0ee643 | 92 | DMA_SLAVE, |
7405f74b DW |
93 | }; |
94 | ||
95 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
96 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
97 | ||
98 | /** | |
99 | * enum dma_slave_width - DMA slave register access width. | |
100 | * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses | |
101 | * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses | |
102 | * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses | |
103 | */ | |
104 | enum dma_slave_width { | |
105 | DMA_SLAVE_WIDTH_8BIT, | |
106 | DMA_SLAVE_WIDTH_16BIT, | |
107 | DMA_SLAVE_WIDTH_32BIT, | |
108 | }; | |
7405f74b | 109 | |
d4c56f97 | 110 | /** |
636bdeaa DW |
111 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
112 | * control completion, and communicate status. | |
d4c56f97 DW |
113 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
114 | * this transaction | |
636bdeaa DW |
115 | * @DMA_CTRL_ACK - the descriptor cannot be reused until the client |
116 | * acknowledges receipt, i.e. has has a chance to establish any | |
117 | * dependency chains | |
e1d181ef DW |
118 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
119 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
d4c56f97 | 120 | */ |
636bdeaa | 121 | enum dma_ctrl_flags { |
d4c56f97 | 122 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 123 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
124 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
125 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
d4c56f97 DW |
126 | }; |
127 | ||
7405f74b DW |
128 | /** |
129 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
130 | * See linux/cpumask.h | |
131 | */ | |
132 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
133 | ||
dc0ee643 HS |
134 | /** |
135 | * struct dma_slave - Information about a DMA slave | |
136 | * @dev: device acting as DMA slave | |
137 | * @dma_dev: required DMA master device. If non-NULL, the client can not be | |
138 | * bound to other masters than this. | |
139 | * @tx_reg: physical address of data register used for | |
140 | * memory-to-peripheral transfers | |
141 | * @rx_reg: physical address of data register used for | |
142 | * peripheral-to-memory transfers | |
143 | * @reg_width: peripheral register width | |
144 | * | |
145 | * If dma_dev is non-NULL, the client can not be bound to other DMA | |
146 | * masters than the one corresponding to this device. The DMA master | |
147 | * driver may use this to determine if there is controller-specific | |
148 | * data wrapped around this struct. Drivers of platform code that sets | |
149 | * the dma_dev field must therefore make sure to use an appropriate | |
150 | * controller-specific dma slave structure wrapping this struct. | |
151 | */ | |
152 | struct dma_slave { | |
153 | struct device *dev; | |
154 | struct device *dma_dev; | |
155 | dma_addr_t tx_reg; | |
156 | dma_addr_t rx_reg; | |
157 | enum dma_slave_width reg_width; | |
158 | }; | |
159 | ||
c13c8260 CL |
160 | /** |
161 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
162 | * @refcount: local_t used for open-coded "bigref" counting | |
163 | * @memcpy_count: transaction counter | |
164 | * @bytes_transferred: byte counter | |
165 | */ | |
166 | ||
167 | struct dma_chan_percpu { | |
c13c8260 CL |
168 | /* stats */ |
169 | unsigned long memcpy_count; | |
170 | unsigned long bytes_transferred; | |
171 | }; | |
172 | ||
173 | /** | |
174 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 175 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 176 | * @cookie: last cookie value returned to client |
fe4ada2d RD |
177 | * @chan_id: channel ID for sysfs |
178 | * @class_dev: class device for sysfs | |
c13c8260 | 179 | * @refcount: kref, used in "bigref" slow-mode |
fe4ada2d RD |
180 | * @slow_ref: indicates that the DMA channel is free |
181 | * @rcu: the DMA channel's RCU head | |
c13c8260 CL |
182 | * @device_node: used to add this to the device chan list |
183 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 184 | * @client-count: how many clients are using this channel |
bec08513 | 185 | * @table_count: number of appearances in the mem-to-mem allocation table |
c13c8260 CL |
186 | */ |
187 | struct dma_chan { | |
c13c8260 CL |
188 | struct dma_device *device; |
189 | dma_cookie_t cookie; | |
190 | ||
191 | /* sysfs */ | |
192 | int chan_id; | |
891f78ea | 193 | struct device dev; |
c13c8260 CL |
194 | |
195 | struct kref refcount; | |
196 | int slow_ref; | |
197 | struct rcu_head rcu; | |
198 | ||
c13c8260 CL |
199 | struct list_head device_node; |
200 | struct dma_chan_percpu *local; | |
7cc5bf9a | 201 | int client_count; |
bec08513 | 202 | int table_count; |
c13c8260 CL |
203 | }; |
204 | ||
891f78ea | 205 | #define to_dma_chan(p) container_of(p, struct dma_chan, dev) |
d379b01e | 206 | |
c13c8260 CL |
207 | void dma_chan_cleanup(struct kref *kref); |
208 | ||
c13c8260 CL |
209 | /* |
210 | * typedef dma_event_callback - function pointer to a DMA event callback | |
d379b01e DW |
211 | * For each channel added to the system this routine is called for each client. |
212 | * If the client would like to use the channel it returns '1' to signal (ack) | |
213 | * the dmaengine core to take out a reference on the channel and its | |
214 | * corresponding device. A client must not 'ack' an available channel more | |
215 | * than once. When a channel is removed all clients are notified. If a client | |
216 | * is using the channel it must 'ack' the removal. A client must not 'ack' a | |
217 | * removed channel more than once. | |
218 | * @client - 'this' pointer for the client context | |
219 | * @chan - channel to be acted upon | |
220 | * @state - available or removed | |
c13c8260 | 221 | */ |
d379b01e DW |
222 | struct dma_client; |
223 | typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client, | |
224 | struct dma_chan *chan, enum dma_state state); | |
c13c8260 CL |
225 | |
226 | /** | |
227 | * struct dma_client - info on the entity making use of DMA services | |
228 | * @event_callback: func ptr to call when something happens | |
d379b01e DW |
229 | * @cap_mask: only return channels that satisfy the requested capabilities |
230 | * a value of zero corresponds to any capability | |
dc0ee643 HS |
231 | * @slave: data for preparing slave transfer. Must be non-NULL iff the |
232 | * DMA_SLAVE capability is requested. | |
c13c8260 CL |
233 | * @global_node: list_head for global dma_client_list |
234 | */ | |
235 | struct dma_client { | |
236 | dma_event_callback event_callback; | |
d379b01e | 237 | dma_cap_mask_t cap_mask; |
dc0ee643 | 238 | struct dma_slave *slave; |
c13c8260 CL |
239 | struct list_head global_node; |
240 | }; | |
241 | ||
7405f74b DW |
242 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
243 | /** | |
244 | * struct dma_async_tx_descriptor - async transaction descriptor | |
245 | * ---dma generic offload fields--- | |
246 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
247 | * this tx is sitting on a dependency list | |
636bdeaa DW |
248 | * @flags: flags to augment operation preparation, control completion, and |
249 | * communicate status | |
7405f74b DW |
250 | * @phys: physical address of the descriptor |
251 | * @tx_list: driver common field for operations that require multiple | |
252 | * descriptors | |
253 | * @chan: target channel for this operation | |
254 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
255 | * @callback: routine to call after this operation is complete |
256 | * @callback_param: general parameter to pass to the callback routine | |
257 | * ---async_tx api specific fields--- | |
19242d72 | 258 | * @next: at completion submit this descriptor |
7405f74b | 259 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 260 | * @lock: protect the parent and next pointers |
7405f74b DW |
261 | */ |
262 | struct dma_async_tx_descriptor { | |
263 | dma_cookie_t cookie; | |
636bdeaa | 264 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b DW |
265 | dma_addr_t phys; |
266 | struct list_head tx_list; | |
267 | struct dma_chan *chan; | |
268 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
269 | dma_async_tx_callback callback; |
270 | void *callback_param; | |
19242d72 | 271 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
272 | struct dma_async_tx_descriptor *parent; |
273 | spinlock_t lock; | |
274 | }; | |
275 | ||
c13c8260 CL |
276 | /** |
277 | * struct dma_device - info on the entity supplying DMA services | |
278 | * @chancnt: how many DMA channels are supported | |
279 | * @channels: the list of struct dma_chan | |
280 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
281 | * @cap_mask: one or more dma_capability flags |
282 | * @max_xor: maximum number of xor sources, 0 if no capability | |
fe4ada2d RD |
283 | * @refcount: reference count |
284 | * @done: IO completion struct | |
285 | * @dev_id: unique device ID | |
7405f74b | 286 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
287 | * @device_alloc_chan_resources: allocate resources and return the |
288 | * number of allocated descriptors | |
289 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
290 | * @device_prep_dma_memcpy: prepares a memcpy operation |
291 | * @device_prep_dma_xor: prepares a xor operation | |
292 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | |
293 | * @device_prep_dma_memset: prepares a memset operation | |
294 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
295 | * @device_prep_slave_sg: prepares a slave dma operation |
296 | * @device_terminate_all: terminate all pending operations | |
7405f74b | 297 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
298 | */ |
299 | struct dma_device { | |
300 | ||
301 | unsigned int chancnt; | |
302 | struct list_head channels; | |
303 | struct list_head global_node; | |
7405f74b DW |
304 | dma_cap_mask_t cap_mask; |
305 | int max_xor; | |
c13c8260 CL |
306 | |
307 | struct kref refcount; | |
308 | struct completion done; | |
309 | ||
310 | int dev_id; | |
7405f74b | 311 | struct device *dev; |
c13c8260 | 312 | |
848c536a HS |
313 | int (*device_alloc_chan_resources)(struct dma_chan *chan, |
314 | struct dma_client *client); | |
c13c8260 | 315 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
316 | |
317 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 318 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 319 | size_t len, unsigned long flags); |
7405f74b | 320 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 321 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 322 | unsigned int src_cnt, size_t len, unsigned long flags); |
7405f74b | 323 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
0036731c | 324 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
d4c56f97 | 325 | size_t len, u32 *result, unsigned long flags); |
7405f74b | 326 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 327 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 328 | unsigned long flags); |
7405f74b | 329 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 330 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 331 | |
dc0ee643 HS |
332 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
333 | struct dma_chan *chan, struct scatterlist *sgl, | |
334 | unsigned int sg_len, enum dma_data_direction direction, | |
335 | unsigned long flags); | |
336 | void (*device_terminate_all)(struct dma_chan *chan); | |
337 | ||
7405f74b | 338 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
339 | dma_cookie_t cookie, dma_cookie_t *last, |
340 | dma_cookie_t *used); | |
7405f74b | 341 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
342 | }; |
343 | ||
344 | /* --- public DMA engine API --- */ | |
345 | ||
d379b01e | 346 | void dma_async_client_register(struct dma_client *client); |
c13c8260 | 347 | void dma_async_client_unregister(struct dma_client *client); |
d379b01e | 348 | void dma_async_client_chan_request(struct dma_client *client); |
7405f74b DW |
349 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
350 | void *dest, void *src, size_t len); | |
351 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
352 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
353 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
354 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
355 | unsigned int src_off, size_t len); | |
356 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
357 | struct dma_chan *chan); | |
c13c8260 | 358 | |
0839875e | 359 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 360 | { |
636bdeaa DW |
361 | tx->flags |= DMA_CTRL_ACK; |
362 | } | |
363 | ||
0839875e | 364 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 365 | { |
0839875e | 366 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
367 | } |
368 | ||
7405f74b DW |
369 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
370 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 371 | { |
7405f74b DW |
372 | return min_t(int, DMA_TX_TYPE_END, |
373 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
374 | } | |
c13c8260 | 375 | |
7405f74b DW |
376 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
377 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
378 | { | |
379 | return min_t(int, DMA_TX_TYPE_END, | |
380 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
381 | } |
382 | ||
7405f74b DW |
383 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
384 | static inline void | |
385 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 386 | { |
7405f74b DW |
387 | set_bit(tx_type, dstp->bits); |
388 | } | |
c13c8260 | 389 | |
7405f74b DW |
390 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
391 | static inline int | |
392 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
393 | { | |
394 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
395 | } |
396 | ||
7405f74b DW |
397 | #define for_each_dma_cap_mask(cap, mask) \ |
398 | for ((cap) = first_dma_cap(mask); \ | |
399 | (cap) < DMA_TX_TYPE_END; \ | |
400 | (cap) = next_dma_cap((cap), (mask))) | |
401 | ||
c13c8260 | 402 | /** |
7405f74b | 403 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 404 | * @chan: target DMA channel |
c13c8260 CL |
405 | * |
406 | * This allows drivers to push copies to HW in batches, | |
407 | * reducing MMIO writes where possible. | |
408 | */ | |
7405f74b | 409 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 410 | { |
ec8670f1 | 411 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
412 | } |
413 | ||
7405f74b DW |
414 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
415 | ||
c13c8260 | 416 | /** |
7405f74b | 417 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
418 | * @chan: DMA channel |
419 | * @cookie: transaction identifier to check status of | |
420 | * @last: returns last completed cookie, can be NULL | |
421 | * @used: returns last issued cookie, can be NULL | |
422 | * | |
423 | * If @last and @used are passed in, upon return they reflect the driver | |
424 | * internal state and can be used with dma_async_is_complete() to check | |
425 | * the status of multiple cookies without re-checking hardware state. | |
426 | */ | |
7405f74b | 427 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
428 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
429 | { | |
7405f74b | 430 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
431 | } |
432 | ||
7405f74b DW |
433 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
434 | dma_async_is_tx_complete(chan, cookie, last, used) | |
435 | ||
c13c8260 CL |
436 | /** |
437 | * dma_async_is_complete - test a cookie against chan state | |
438 | * @cookie: transaction identifier to test status of | |
439 | * @last_complete: last know completed transaction | |
440 | * @last_used: last cookie value handed out | |
441 | * | |
442 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 443 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
444 | */ |
445 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
446 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
447 | { | |
448 | if (last_complete <= last_used) { | |
449 | if ((cookie <= last_complete) || (cookie > last_used)) | |
450 | return DMA_SUCCESS; | |
451 | } else { | |
452 | if ((cookie <= last_complete) && (cookie > last_used)) | |
453 | return DMA_SUCCESS; | |
454 | } | |
455 | return DMA_IN_PROGRESS; | |
456 | } | |
457 | ||
7405f74b | 458 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
459 | #ifdef CONFIG_DMA_ENGINE |
460 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
461 | #else | |
462 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
463 | { | |
464 | return DMA_SUCCESS; | |
465 | } | |
466 | #endif | |
c13c8260 CL |
467 | |
468 | /* --- DMA device --- */ | |
469 | ||
470 | int dma_async_device_register(struct dma_device *device); | |
471 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 472 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 473 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
2ba05622 | 474 | void dma_issue_pending_all(void); |
c13c8260 | 475 | |
de5506e1 CL |
476 | /* --- Helper iov-locking functions --- */ |
477 | ||
478 | struct dma_page_list { | |
b2ddb901 | 479 | char __user *base_address; |
de5506e1 CL |
480 | int nr_pages; |
481 | struct page **pages; | |
482 | }; | |
483 | ||
484 | struct dma_pinned_list { | |
485 | int nr_iovecs; | |
486 | struct dma_page_list page_list[0]; | |
487 | }; | |
488 | ||
489 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
490 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
491 | ||
492 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
493 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
494 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
495 | struct dma_pinned_list *pinned_list, struct page *page, | |
496 | unsigned int offset, size_t len); | |
497 | ||
c13c8260 | 498 | #endif /* DMAENGINE_H */ |