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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
1531a6a6 | 27 | #include <linux/irqreturn.h> |
3a5670e8 | 28 | #include <linux/rwsem.h> |
0e242612 | 29 | #include <linux/rcupdate.h> |
10e5247f | 30 | |
6eea69dd AM |
31 | struct acpi_dmar_header; |
32 | ||
41750d31 SS |
33 | /* DMAR Flags */ |
34 | #define DMAR_INTR_REMAP 0x1 | |
35 | #define DMAR_X2APIC_OPT_OUT 0x2 | |
36 | ||
ba395927 | 37 | struct intel_iommu; |
694835dc | 38 | |
832bd858 DW |
39 | struct dmar_dev_scope { |
40 | struct device __rcu *dev; | |
41 | u8 bus; | |
42 | u8 devfn; | |
43 | }; | |
44 | ||
d3f13810 | 45 | #ifdef CONFIG_DMAR_TABLE |
41750d31 | 46 | extern struct acpi_table_header *dmar_tbl; |
2ae21010 SS |
47 | struct dmar_drhd_unit { |
48 | struct list_head list; /* list of drhd units */ | |
49 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
50 | u64 reg_base_addr; /* register base address*/ | |
832bd858 | 51 | struct dmar_dev_scope *devices;/* target device array */ |
2ae21010 | 52 | int devices_cnt; /* target device count */ |
276dbf99 | 53 | u16 segment; /* PCI domain */ |
2ae21010 SS |
54 | u8 ignored:1; /* ignore drhd */ |
55 | u8 include_all:1; | |
56 | struct intel_iommu *iommu; | |
57 | }; | |
58 | ||
57384592 JR |
59 | struct dmar_pci_path { |
60 | u8 bus; | |
61 | u8 device; | |
62 | u8 function; | |
63 | }; | |
64 | ||
59ce0515 JL |
65 | struct dmar_pci_notify_info { |
66 | struct pci_dev *dev; | |
67 | unsigned long event; | |
68 | int bus; | |
69 | u16 seg; | |
70 | u16 level; | |
57384592 | 71 | struct dmar_pci_path path[]; |
59ce0515 JL |
72 | } __attribute__((packed)); |
73 | ||
3a5670e8 | 74 | extern struct rw_semaphore dmar_global_lock; |
2ae21010 SS |
75 | extern struct list_head dmar_drhd_units; |
76 | ||
77 | #define for_each_drhd_unit(drhd) \ | |
0e242612 | 78 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) |
2ae21010 | 79 | |
7c919779 | 80 | #define for_each_active_drhd_unit(drhd) \ |
0e242612 | 81 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
7c919779 JL |
82 | if (drhd->ignored) {} else |
83 | ||
8f912ba4 | 84 | #define for_each_active_iommu(i, drhd) \ |
0e242612 | 85 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
8f912ba4 DW |
86 | if (i=drhd->iommu, drhd->ignored) {} else |
87 | ||
88 | #define for_each_iommu(i, drhd) \ | |
0e242612 | 89 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
8f912ba4 DW |
90 | if (i=drhd->iommu, 0) {} else |
91 | ||
0e242612 JL |
92 | static inline bool dmar_rcu_check(void) |
93 | { | |
94 | return rwsem_is_locked(&dmar_global_lock) || | |
95 | system_state == SYSTEM_BOOTING; | |
96 | } | |
97 | ||
98 | #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) | |
99 | ||
b683b230 | 100 | #define for_each_dev_scope(a, c, p, d) \ |
832bd858 | 101 | for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)].dev) : \ |
0e242612 | 102 | NULL, (p) < (c)); (p)++) |
b683b230 JL |
103 | |
104 | #define for_each_active_dev_scope(a, c, p, d) \ | |
105 | for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else | |
106 | ||
2ae21010 | 107 | extern int dmar_table_init(void); |
2ae21010 | 108 | extern int dmar_dev_scope_init(void); |
ada4d4b2 | 109 | extern int dmar_parse_dev_scope(void *start, void *end, int *cnt, |
832bd858 | 110 | struct dmar_dev_scope **devices, u16 segment); |
bb3a6b78 | 111 | extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); |
832bd858 | 112 | extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt); |
59ce0515 JL |
113 | extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, |
114 | void *start, void*end, u16 segment, | |
832bd858 | 115 | struct dmar_dev_scope *devices, |
59ce0515 JL |
116 | int devices_cnt); |
117 | extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, | |
832bd858 | 118 | u16 segment, struct dmar_dev_scope *devices, |
59ce0515 | 119 | int count); |
2ae21010 | 120 | /* Intel IOMMU detection */ |
480125ba | 121 | extern int detect_intel_iommu(void); |
9d783ba0 | 122 | extern int enable_drhd_fault_handling(void); |
8594d832 JL |
123 | |
124 | #ifdef CONFIG_INTEL_IOMMU | |
125 | extern int iommu_detected, no_iommu; | |
126 | extern int intel_iommu_init(void); | |
127 | extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header); | |
128 | extern int dmar_parse_one_atsr(struct acpi_dmar_header *header); | |
129 | extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info); | |
130 | #else /* !CONFIG_INTEL_IOMMU: */ | |
131 | static inline int intel_iommu_init(void) { return -ENODEV; } | |
132 | static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header) | |
2ae21010 | 133 | { |
8594d832 | 134 | return 0; |
2ae21010 | 135 | } |
8594d832 | 136 | static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header) |
2ae21010 | 137 | { |
8594d832 | 138 | return 0; |
2ae21010 | 139 | } |
8594d832 | 140 | static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
29b61be6 | 141 | { |
8594d832 | 142 | return 0; |
29b61be6 | 143 | } |
8594d832 JL |
144 | #endif /* CONFIG_INTEL_IOMMU */ |
145 | ||
146 | #endif /* CONFIG_DMAR_TABLE */ | |
2ae21010 | 147 | |
2ae21010 SS |
148 | struct irte { |
149 | union { | |
150 | struct { | |
151 | __u64 present : 1, | |
152 | fpd : 1, | |
153 | dst_mode : 1, | |
154 | redir_hint : 1, | |
155 | trigger_mode : 1, | |
156 | dlvry_mode : 3, | |
157 | avail : 4, | |
158 | __reserved_1 : 4, | |
159 | vector : 8, | |
160 | __reserved_2 : 8, | |
161 | dest_id : 32; | |
162 | }; | |
163 | __u64 low; | |
164 | }; | |
165 | ||
166 | union { | |
167 | struct { | |
168 | __u64 sid : 16, | |
169 | sq : 2, | |
170 | svt : 2, | |
171 | __reserved_3 : 44; | |
172 | }; | |
173 | __u64 high; | |
174 | }; | |
175 | }; | |
423f0859 | 176 | |
41750d31 SS |
177 | enum { |
178 | IRQ_REMAP_XAPIC_MODE, | |
179 | IRQ_REMAP_X2APIC_MODE, | |
180 | }; | |
181 | ||
3460a6d9 KA |
182 | /* Can't use the common MSI interrupt functions |
183 | * since DMAR is not a pci device | |
184 | */ | |
5c2837fb TG |
185 | struct irq_data; |
186 | extern void dmar_msi_unmask(struct irq_data *data); | |
187 | extern void dmar_msi_mask(struct irq_data *data); | |
3460a6d9 KA |
188 | extern void dmar_msi_read(int irq, struct msi_msg *msg); |
189 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
190 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 191 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
3460a6d9 KA |
192 | extern int arch_setup_dmar_msi(unsigned int irq); |
193 | ||
10e5247f | 194 | #endif /* __DMAR_H__ */ |