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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
1531a6a6 | 27 | #include <linux/irqreturn.h> |
3a5670e8 | 28 | #include <linux/rwsem.h> |
0e242612 | 29 | #include <linux/rcupdate.h> |
10e5247f | 30 | |
6eea69dd AM |
31 | struct acpi_dmar_header; |
32 | ||
78d8e704 JL |
33 | #ifdef CONFIG_X86 |
34 | # define DMAR_UNITS_SUPPORTED MAX_IO_APICS | |
35 | #else | |
36 | # define DMAR_UNITS_SUPPORTED 64 | |
37 | #endif | |
38 | ||
41750d31 SS |
39 | /* DMAR Flags */ |
40 | #define DMAR_INTR_REMAP 0x1 | |
41 | #define DMAR_X2APIC_OPT_OUT 0x2 | |
42 | ||
ba395927 | 43 | struct intel_iommu; |
694835dc | 44 | |
832bd858 DW |
45 | struct dmar_dev_scope { |
46 | struct device __rcu *dev; | |
47 | u8 bus; | |
48 | u8 devfn; | |
49 | }; | |
50 | ||
d3f13810 | 51 | #ifdef CONFIG_DMAR_TABLE |
41750d31 | 52 | extern struct acpi_table_header *dmar_tbl; |
2ae21010 SS |
53 | struct dmar_drhd_unit { |
54 | struct list_head list; /* list of drhd units */ | |
55 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
56 | u64 reg_base_addr; /* register base address*/ | |
832bd858 | 57 | struct dmar_dev_scope *devices;/* target device array */ |
2ae21010 | 58 | int devices_cnt; /* target device count */ |
276dbf99 | 59 | u16 segment; /* PCI domain */ |
2ae21010 SS |
60 | u8 ignored:1; /* ignore drhd */ |
61 | u8 include_all:1; | |
62 | struct intel_iommu *iommu; | |
63 | }; | |
64 | ||
57384592 JR |
65 | struct dmar_pci_path { |
66 | u8 bus; | |
67 | u8 device; | |
68 | u8 function; | |
69 | }; | |
70 | ||
59ce0515 JL |
71 | struct dmar_pci_notify_info { |
72 | struct pci_dev *dev; | |
73 | unsigned long event; | |
74 | int bus; | |
75 | u16 seg; | |
76 | u16 level; | |
57384592 | 77 | struct dmar_pci_path path[]; |
59ce0515 JL |
78 | } __attribute__((packed)); |
79 | ||
3a5670e8 | 80 | extern struct rw_semaphore dmar_global_lock; |
2ae21010 SS |
81 | extern struct list_head dmar_drhd_units; |
82 | ||
83 | #define for_each_drhd_unit(drhd) \ | |
0e242612 | 84 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) |
2ae21010 | 85 | |
7c919779 | 86 | #define for_each_active_drhd_unit(drhd) \ |
0e242612 | 87 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
7c919779 JL |
88 | if (drhd->ignored) {} else |
89 | ||
8f912ba4 | 90 | #define for_each_active_iommu(i, drhd) \ |
0e242612 | 91 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
8f912ba4 DW |
92 | if (i=drhd->iommu, drhd->ignored) {} else |
93 | ||
94 | #define for_each_iommu(i, drhd) \ | |
0e242612 | 95 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
8f912ba4 DW |
96 | if (i=drhd->iommu, 0) {} else |
97 | ||
0e242612 JL |
98 | static inline bool dmar_rcu_check(void) |
99 | { | |
100 | return rwsem_is_locked(&dmar_global_lock) || | |
101 | system_state == SYSTEM_BOOTING; | |
102 | } | |
103 | ||
104 | #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) | |
105 | ||
b683b230 | 106 | #define for_each_dev_scope(a, c, p, d) \ |
832bd858 | 107 | for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)].dev) : \ |
0e242612 | 108 | NULL, (p) < (c)); (p)++) |
b683b230 JL |
109 | |
110 | #define for_each_active_dev_scope(a, c, p, d) \ | |
111 | for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else | |
112 | ||
2ae21010 | 113 | extern int dmar_table_init(void); |
2ae21010 | 114 | extern int dmar_dev_scope_init(void); |
ada4d4b2 | 115 | extern int dmar_parse_dev_scope(void *start, void *end, int *cnt, |
832bd858 | 116 | struct dmar_dev_scope **devices, u16 segment); |
bb3a6b78 | 117 | extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); |
832bd858 | 118 | extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt); |
59ce0515 JL |
119 | extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, |
120 | void *start, void*end, u16 segment, | |
832bd858 | 121 | struct dmar_dev_scope *devices, |
59ce0515 JL |
122 | int devices_cnt); |
123 | extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, | |
832bd858 | 124 | u16 segment, struct dmar_dev_scope *devices, |
59ce0515 | 125 | int count); |
2ae21010 | 126 | /* Intel IOMMU detection */ |
480125ba | 127 | extern int detect_intel_iommu(void); |
9d783ba0 | 128 | extern int enable_drhd_fault_handling(void); |
6b197249 JL |
129 | extern int dmar_device_add(acpi_handle handle); |
130 | extern int dmar_device_remove(acpi_handle handle); | |
8594d832 | 131 | |
c2a0b538 JL |
132 | static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg) |
133 | { | |
134 | return 0; | |
135 | } | |
136 | ||
8594d832 JL |
137 | #ifdef CONFIG_INTEL_IOMMU |
138 | extern int iommu_detected, no_iommu; | |
139 | extern int intel_iommu_init(void); | |
c2a0b538 JL |
140 | extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg); |
141 | extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg); | |
6b197249 JL |
142 | extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg); |
143 | extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg); | |
144 | extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
8594d832 JL |
145 | extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info); |
146 | #else /* !CONFIG_INTEL_IOMMU: */ | |
147 | static inline int intel_iommu_init(void) { return -ENODEV; } | |
6b197249 | 148 | |
c2a0b538 JL |
149 | #define dmar_parse_one_rmrr dmar_res_noop |
150 | #define dmar_parse_one_atsr dmar_res_noop | |
6b197249 JL |
151 | #define dmar_check_one_atsr dmar_res_noop |
152 | #define dmar_release_one_atsr dmar_res_noop | |
153 | ||
8594d832 | 154 | static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
29b61be6 | 155 | { |
8594d832 | 156 | return 0; |
29b61be6 | 157 | } |
6b197249 JL |
158 | |
159 | static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
160 | { | |
161 | return 0; | |
162 | } | |
8594d832 JL |
163 | #endif /* CONFIG_INTEL_IOMMU */ |
164 | ||
6b197249 JL |
165 | #ifdef CONFIG_IRQ_REMAP |
166 | extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
167 | #else /* CONFIG_IRQ_REMAP */ | |
168 | static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
169 | { return 0; } | |
170 | #endif /* CONFIG_IRQ_REMAP */ | |
171 | ||
172 | #else /* CONFIG_DMAR_TABLE */ | |
173 | ||
174 | static inline int dmar_device_add(void *handle) | |
175 | { | |
176 | return 0; | |
177 | } | |
178 | ||
179 | static inline int dmar_device_remove(void *handle) | |
180 | { | |
181 | return 0; | |
182 | } | |
183 | ||
8594d832 | 184 | #endif /* CONFIG_DMAR_TABLE */ |
2ae21010 | 185 | |
2ae21010 SS |
186 | struct irte { |
187 | union { | |
3bf17472 | 188 | /* Shared between remapped and posted mode*/ |
2ae21010 | 189 | struct { |
3bf17472 TG |
190 | __u64 present : 1, /* 0 */ |
191 | fpd : 1, /* 1 */ | |
192 | __res0 : 6, /* 2 - 6 */ | |
193 | avail : 4, /* 8 - 11 */ | |
194 | __res1 : 3, /* 12 - 14 */ | |
195 | pst : 1, /* 15 */ | |
196 | vector : 8, /* 16 - 23 */ | |
197 | __res2 : 40; /* 24 - 63 */ | |
198 | }; | |
199 | ||
200 | /* Remapped mode */ | |
201 | struct { | |
202 | __u64 r_present : 1, /* 0 */ | |
203 | r_fpd : 1, /* 1 */ | |
204 | dst_mode : 1, /* 2 */ | |
205 | redir_hint : 1, /* 3 */ | |
206 | trigger_mode : 1, /* 4 */ | |
207 | dlvry_mode : 3, /* 5 - 7 */ | |
208 | r_avail : 4, /* 8 - 11 */ | |
209 | r_res0 : 4, /* 12 - 15 */ | |
210 | r_vector : 8, /* 16 - 23 */ | |
211 | r_res1 : 8, /* 24 - 31 */ | |
212 | dest_id : 32; /* 32 - 63 */ | |
213 | }; | |
214 | ||
215 | /* Posted mode */ | |
216 | struct { | |
217 | __u64 p_present : 1, /* 0 */ | |
218 | p_fpd : 1, /* 1 */ | |
219 | p_res0 : 6, /* 2 - 7 */ | |
220 | p_avail : 4, /* 8 - 11 */ | |
221 | p_res1 : 2, /* 12 - 13 */ | |
222 | p_urgent : 1, /* 14 */ | |
223 | p_pst : 1, /* 15 */ | |
224 | p_vector : 8, /* 16 - 23 */ | |
225 | p_res2 : 14, /* 24 - 37 */ | |
226 | pda_l : 26; /* 38 - 63 */ | |
2ae21010 SS |
227 | }; |
228 | __u64 low; | |
229 | }; | |
230 | ||
231 | union { | |
3bf17472 | 232 | /* Shared between remapped and posted mode*/ |
2ae21010 | 233 | struct { |
3bf17472 TG |
234 | __u64 sid : 16, /* 64 - 79 */ |
235 | sq : 2, /* 80 - 81 */ | |
236 | svt : 2, /* 82 - 83 */ | |
237 | __res3 : 44; /* 84 - 127 */ | |
238 | }; | |
239 | ||
240 | /* Posted mode*/ | |
241 | struct { | |
242 | __u64 p_sid : 16, /* 64 - 79 */ | |
243 | p_sq : 2, /* 80 - 81 */ | |
244 | p_svt : 2, /* 82 - 83 */ | |
245 | p_res3 : 12, /* 84 - 95 */ | |
246 | pda_h : 32; /* 96 - 127 */ | |
2ae21010 SS |
247 | }; |
248 | __u64 high; | |
249 | }; | |
250 | }; | |
423f0859 | 251 | |
bf56027f TG |
252 | static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src) |
253 | { | |
254 | dst->present = src->present; | |
255 | dst->fpd = src->fpd; | |
256 | dst->avail = src->avail; | |
257 | dst->pst = src->pst; | |
258 | dst->vector = src->vector; | |
259 | dst->sid = src->sid; | |
260 | dst->sq = src->sq; | |
261 | dst->svt = src->svt; | |
262 | } | |
263 | ||
3bf17472 TG |
264 | #define PDA_LOW_BIT 26 |
265 | #define PDA_HIGH_BIT 32 | |
266 | ||
41750d31 SS |
267 | enum { |
268 | IRQ_REMAP_XAPIC_MODE, | |
269 | IRQ_REMAP_X2APIC_MODE, | |
270 | }; | |
271 | ||
3460a6d9 KA |
272 | /* Can't use the common MSI interrupt functions |
273 | * since DMAR is not a pci device | |
274 | */ | |
5c2837fb TG |
275 | struct irq_data; |
276 | extern void dmar_msi_unmask(struct irq_data *data); | |
277 | extern void dmar_msi_mask(struct irq_data *data); | |
3460a6d9 KA |
278 | extern void dmar_msi_read(int irq, struct msi_msg *msg); |
279 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
280 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 281 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
34742db8 JL |
282 | extern int dmar_alloc_hwirq(int id, int node, void *arg); |
283 | extern void dmar_free_hwirq(int irq); | |
3460a6d9 | 284 | |
10e5247f | 285 | #endif /* __DMAR_H__ */ |