[mirror_ubuntu-bionic-kernel.git] / include / linux / dmar.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
 */

#ifndef __DMAR_H__
#define __DMAR_H__

#include <linux/acpi.h>
#include <linux/types.h>
#include <linux/msi.h>
#include <linux/irqreturn.h>
#include <linux/rwsem.h>
#include <linux/rcupdate.h>

struct acpi_dmar_header;

/* DMAR Flags */
#define DMAR_INTR_REMAP		0x1
#define DMAR_X2APIC_OPT_OUT	0x2

struct intel_iommu;

#ifdef CONFIG_DMAR_TABLE
extern struct acpi_table_header *dmar_tbl;
struct dmar_drhd_unit {
	struct list_head list;		/* list of drhd units	*/
	struct  acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	reg_base_addr;		/* register base address*/
	struct	pci_dev __rcu **devices;/* target device array	*/
	int	devices_cnt;		/* target device count	*/
	u16	segment;		/* PCI domain		*/
	u8	ignored:1; 		/* ignore drhd		*/
	u8	include_all:1;
	struct intel_iommu *iommu;
};

extern struct rw_semaphore dmar_global_lock;
extern struct list_head dmar_drhd_units;

#define for_each_drhd_unit(drhd) \
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)

#define for_each_active_drhd_unit(drhd)					\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (drhd->ignored) {} else

#define for_each_active_iommu(i, drhd)					\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, drhd->ignored) {} else

#define for_each_iommu(i, drhd)						\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, 0) {} else 

static inline bool dmar_rcu_check(void)
{
	return rwsem_is_locked(&dmar_global_lock) ||
	       system_state == SYSTEM_BOOTING;
}

#define	dmar_rcu_dereference(p)	rcu_dereference_check((p), dmar_rcu_check())

#define	for_each_dev_scope(a, c, p, d)	\
	for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)]) : \
			NULL, (p) < (c)); (p)++)

#define	for_each_active_dev_scope(a, c, p, d)	\
	for_each_dev_scope((a), (c), (p), (d))	if (!(d)) { continue; } else

extern int dmar_table_init(void);
extern int dmar_dev_scope_init(void);
extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
				struct pci_dev ***devices, u16 segment);
extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
extern void dmar_free_dev_scope(struct pci_dev __rcu ***devices, int *cnt);
extern void dmar_free_dev_scope(struct pci_dev ***devices, int *cnt);

/* Intel IOMMU detection */
extern int detect_intel_iommu(void);
extern int enable_drhd_fault_handling(void);
#else
static inline int detect_intel_iommu(void)
{
	return -ENODEV;
}

static inline int dmar_table_init(void)
{
	return -ENODEV;
}
static inline int enable_drhd_fault_handling(void)
{
	return -1;
}
#endif /* !CONFIG_DMAR_TABLE */

struct irte {
	union {
		struct {
			__u64	present 	: 1,
				fpd		: 1,
				dst_mode	: 1,
				redir_hint	: 1,
				trigger_mode	: 1,
				dlvry_mode	: 3,
				avail		: 4,
				__reserved_1	: 4,
				vector		: 8,
				__reserved_2	: 8,
				dest_id		: 32;
		};
		__u64 low;
	};

	union {
		struct {
			__u64	sid		: 16,
				sq		: 2,
				svt		: 2,
				__reserved_3	: 44;
		};
		__u64 high;
	};
};

enum {
	IRQ_REMAP_XAPIC_MODE,
	IRQ_REMAP_X2APIC_MODE,
};

/* Can't use the common MSI interrupt functions
 * since DMAR is not a pci device
 */
struct irq_data;
extern void dmar_msi_unmask(struct irq_data *data);
extern void dmar_msi_mask(struct irq_data *data);
extern void dmar_msi_read(int irq, struct msi_msg *msg);
extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern irqreturn_t dmar_fault(int irq, void *dev_id);
extern int arch_setup_dmar_msi(unsigned int irq);

#ifdef CONFIG_INTEL_IOMMU
extern int iommu_detected, no_iommu;
extern int dmar_parse_rmrr_atsr_dev(void);
extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
extern int intel_iommu_init(void);
#else /* !CONFIG_INTEL_IOMMU: */
static inline int intel_iommu_init(void) { return -ENODEV; }
static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
{
	return 0;
}
static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
{
	return 0;
}
static inline int dmar_parse_rmrr_atsr_dev(void)
{
	return 0;
}
#endif /* CONFIG_INTEL_IOMMU */

#endif /* __DMAR_H__ */
Commit	Line	Data
10e5247f KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
	17	* Copyright (C) Ashok Raj <ashok.raj@intel.com>
	18	* Copyright (C) Shaohua Li <shaohua.li@intel.com>
	19	*/
	20
	21	#ifndef __DMAR_H__
	22	#define __DMAR_H__
	23
	24	#include <linux/acpi.h>
	25	#include <linux/types.h>
ba395927	26	#include <linux/msi.h>
1531a6a6	27	#include <linux/irqreturn.h>
3a5670e8	28	#include <linux/rwsem.h>
0e242612	29	#include <linux/rcupdate.h>
10e5247f	30
6eea69dd AM	31	struct acpi_dmar_header;
6eea69dd AM	32
41750d31 SS	33	/* DMAR Flags */
	34	#define DMAR_INTR_REMAP 0x1
	35	#define DMAR_X2APIC_OPT_OUT 0x2
	36
ba395927	37	struct intel_iommu;
694835dc	38
d3f13810	39	#ifdef CONFIG_DMAR_TABLE
41750d31	40	extern struct acpi_table_header *dmar_tbl;
2ae21010 SS	41	struct dmar_drhd_unit {
	42	struct list_head list; /* list of drhd units */
	43	struct acpi_dmar_header hdr; / ACPI header */
	44	u64 reg_base_addr; /* register base address*/
0e242612	45	struct pci_dev __rcu *devices;/ target device array */
2ae21010	46	int devices_cnt; /* target device count */
276dbf99	47	u16 segment; /* PCI domain */
2ae21010 SS	48	u8 ignored:1; /* ignore drhd */
	49	u8 include_all:1;
	50	struct intel_iommu *iommu;
	51	};
	52
3a5670e8	53	extern struct rw_semaphore dmar_global_lock;
2ae21010 SS	54	extern struct list_head dmar_drhd_units;
	55
	56	#define for_each_drhd_unit(drhd) \
0e242612	57	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)
2ae21010	58
7c919779	59	#define for_each_active_drhd_unit(drhd) \
0e242612	60	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
7c919779 JL	61	if (drhd->ignored) {} else
7c919779 JL	62
8f912ba4	63	#define for_each_active_iommu(i, drhd) \
0e242612	64	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
8f912ba4 DW	65	if (i=drhd->iommu, drhd->ignored) {} else
	66
	67	#define for_each_iommu(i, drhd) \
0e242612	68	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
8f912ba4 DW	69	if (i=drhd->iommu, 0) {} else
8f912ba4 DW	70
0e242612 JL	71	static inline bool dmar_rcu_check(void)
	72	{
	73	return rwsem_is_locked(&dmar_global_lock) \|\|
	74	system_state == SYSTEM_BOOTING;
	75	}
	76
	77	#define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
	78
b683b230	79	#define for_each_dev_scope(a, c, p, d) \
0e242612 JL	80	for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)]) : \
0e242612 JL	81	NULL, (p) < (c)); (p)++)
b683b230 JL	82
	83	#define for_each_active_dev_scope(a, c, p, d) \
	84	for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else
	85
2ae21010	86	extern int dmar_table_init(void);
2ae21010	87	extern int dmar_dev_scope_init(void);
ada4d4b2 JL	88	extern int dmar_parse_dev_scope(void start, void end, int *cnt,
ada4d4b2 JL	89	struct pci_dev ***devices, u16 segment);
bb3a6b78	90	extern void dmar_alloc_dev_scope(void start, void end, int cnt);
0e242612	91	extern void dmar_free_dev_scope(struct pci_dev __rcu **devices, int cnt);
ada4d4b2	92	extern void dmar_free_dev_scope(struct pci_dev **devices, int cnt);
2ae21010 SS	93
2ae21010 SS	94	/* Intel IOMMU detection */
480125ba	95	extern int detect_intel_iommu(void);
9d783ba0	96	extern int enable_drhd_fault_handling(void);
2ae21010	97	#else
480125ba	98	static inline int detect_intel_iommu(void)
2ae21010	99	{
480125ba	100	return -ENODEV;
2ae21010 SS	101	}
	102
	103	static inline int dmar_table_init(void)
	104	{
	105	return -ENODEV;
	106	}
29b61be6 SS	107	static inline int enable_drhd_fault_handling(void)
	108	{
	109	return -1;
	110	}
d3f13810	111	#endif /* !CONFIG_DMAR_TABLE */
2ae21010	112
2ae21010 SS	113	struct irte {
	114	union {
	115	struct {
	116	__u64 present : 1,
	117	fpd : 1,
	118	dst_mode : 1,
	119	redir_hint : 1,
	120	trigger_mode : 1,
	121	dlvry_mode : 3,
	122	avail : 4,
	123	__reserved_1 : 4,
	124	vector : 8,
	125	__reserved_2 : 8,
	126	dest_id : 32;
	127	};
	128	__u64 low;
	129	};
	130
	131	union {
	132	struct {
	133	__u64 sid : 16,
	134	sq : 2,
	135	svt : 2,
	136	__reserved_3 : 44;
	137	};
	138	__u64 high;
	139	};
	140	};
423f0859	141
41750d31 SS	142	enum {
	143	IRQ_REMAP_XAPIC_MODE,
	144	IRQ_REMAP_X2APIC_MODE,
	145	};
	146
3460a6d9 KA	147	/* Can't use the common MSI interrupt functions
	148	* since DMAR is not a pci device
	149	*/
5c2837fb TG	150	struct irq_data;
	151	extern void dmar_msi_unmask(struct irq_data *data);
	152	extern void dmar_msi_mask(struct irq_data *data);
3460a6d9 KA	153	extern void dmar_msi_read(int irq, struct msi_msg *msg);
	154	extern void dmar_msi_write(int irq, struct msi_msg *msg);
	155	extern int dmar_set_interrupt(struct intel_iommu *iommu);
1531a6a6	156	extern irqreturn_t dmar_fault(int irq, void *dev_id);
3460a6d9 KA	157	extern int arch_setup_dmar_msi(unsigned int irq);
3460a6d9 KA	158
d3f13810	159	#ifdef CONFIG_INTEL_IOMMU
2ae21010	160	extern int iommu_detected, no_iommu;
b94e4117	161	extern int dmar_parse_rmrr_atsr_dev(void);
318fe7df SS	162	extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
318fe7df SS	163	extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
2ae21010	164	extern int intel_iommu_init(void);
d3f13810	165	#else /* !CONFIG_INTEL_IOMMU: */
9d5ce73a	166	static inline int intel_iommu_init(void) { return -ENODEV; }
318fe7df SS	167	static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
	168	{
	169	return 0;
	170	}
	171	static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
	172	{
	173	return 0;
	174	}
	175	static inline int dmar_parse_rmrr_atsr_dev(void)
	176	{
	177	return 0;
	178	}
d3f13810	179	#endif /* CONFIG_INTEL_IOMMU */
9d5ce73a	180
10e5247f	181	#endif /* __DMAR_H__ */