]>
Commit | Line | Data |
---|---|---|
c0d12172 DJ |
1 | /* |
2 | * Generic EDAC defs | |
3 | * | |
4 | * Author: Dave Jiang <djiang@mvista.com> | |
5 | * | |
c3c52bce | 6 | * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under |
c0d12172 DJ |
7 | * the terms of the GNU General Public License version 2. This program |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | */ | |
12 | #ifndef _LINUX_EDAC_H_ | |
13 | #define _LINUX_EDAC_H_ | |
14 | ||
60063497 | 15 | #include <linux/atomic.h> |
7a623c03 | 16 | #include <linux/device.h> |
313162d0 PG |
17 | #include <linux/completion.h> |
18 | #include <linux/workqueue.h> | |
452a6bf9 | 19 | #include <linux/debugfs.h> |
6b588594 | 20 | #include <linux/numa.h> |
313162d0 | 21 | |
0b892c71 MCC |
22 | #define EDAC_DEVICE_NAME_LEN 31 |
23 | ||
313162d0 | 24 | struct device; |
c0d12172 DJ |
25 | |
26 | #define EDAC_OPSTATE_INVAL -1 | |
27 | #define EDAC_OPSTATE_POLL 0 | |
28 | #define EDAC_OPSTATE_NMI 1 | |
29 | #define EDAC_OPSTATE_INT 2 | |
30 | ||
31 | extern int edac_op_state; | |
c0d12172 | 32 | |
fee27d7d | 33 | struct bus_type *edac_get_sysfs_subsys(void); |
c700f013 | 34 | |
c3c52bce HM |
35 | static inline void opstate_init(void) |
36 | { | |
37 | switch (edac_op_state) { | |
38 | case EDAC_OPSTATE_POLL: | |
39 | case EDAC_OPSTATE_NMI: | |
40 | break; | |
41 | default: | |
42 | edac_op_state = EDAC_OPSTATE_POLL; | |
43 | } | |
44 | return; | |
45 | } | |
46 | ||
c7ef7645 | 47 | /* Max length of a DIMM label*/ |
ddeb3547 | 48 | #define EDAC_MC_LABEL_LEN 31 |
ddeb3547 | 49 | |
c7ef7645 | 50 | /* Maximum size of the location string */ |
56507694 | 51 | #define LOCATION_SIZE 256 |
c7ef7645 MCC |
52 | |
53 | /* Defines the maximum number of labels that can be reported */ | |
54 | #define EDAC_MAX_LABELS 8 | |
55 | ||
56 | /* String used to join two or more labels */ | |
57 | #define OTHER_LABEL " or " | |
58 | ||
b0610bb8 MCC |
59 | /** |
60 | * enum dev_type - describe the type of memory DRAM chips used at the stick | |
61 | * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it | |
62 | * @DEV_X1: 1 bit for data | |
63 | * @DEV_X2: 2 bits for data | |
64 | * @DEV_X4: 4 bits for data | |
65 | * @DEV_X8: 8 bits for data | |
66 | * @DEV_X16: 16 bits for data | |
67 | * @DEV_X32: 32 bits for data | |
68 | * @DEV_X64: 64 bits for data | |
69 | * | |
70 | * Typical values are x4 and x8. | |
71 | */ | |
ddeb3547 MCC |
72 | enum dev_type { |
73 | DEV_UNKNOWN = 0, | |
74 | DEV_X1, | |
75 | DEV_X2, | |
76 | DEV_X4, | |
77 | DEV_X8, | |
78 | DEV_X16, | |
79 | DEV_X32, /* Do these parts exist? */ | |
80 | DEV_X64 /* Do these parts exist? */ | |
81 | }; | |
82 | ||
83 | #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) | |
84 | #define DEV_FLAG_X1 BIT(DEV_X1) | |
85 | #define DEV_FLAG_X2 BIT(DEV_X2) | |
86 | #define DEV_FLAG_X4 BIT(DEV_X4) | |
87 | #define DEV_FLAG_X8 BIT(DEV_X8) | |
88 | #define DEV_FLAG_X16 BIT(DEV_X16) | |
89 | #define DEV_FLAG_X32 BIT(DEV_X32) | |
90 | #define DEV_FLAG_X64 BIT(DEV_X64) | |
91 | ||
982216a4 MCC |
92 | /** |
93 | * enum hw_event_mc_err_type - type of the detected error | |
94 | * | |
95 | * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC | |
96 | * corrected error was detected | |
97 | * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that | |
98 | * can't be corrected by ECC, but it is not | |
99 | * fatal (maybe it is on an unused memory area, | |
100 | * or the memory controller could recover from | |
101 | * it for example, by re-trying the operation). | |
4838a0de YG |
102 | * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable |
103 | * error whose handling is not urgent. This could | |
104 | * be due to hardware data poisoning where the | |
105 | * system can continue operation until the poisoned | |
106 | * data is consumed. Preemptive measures may also | |
107 | * be taken, e.g. offlining pages, etc. | |
982216a4 MCC |
108 | * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not |
109 | * be recovered. | |
e0020758 MCC |
110 | * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth |
111 | * type of error: informational logs. | |
982216a4 MCC |
112 | */ |
113 | enum hw_event_mc_err_type { | |
114 | HW_EVENT_ERR_CORRECTED, | |
115 | HW_EVENT_ERR_UNCORRECTED, | |
d12a969e | 116 | HW_EVENT_ERR_DEFERRED, |
982216a4 | 117 | HW_EVENT_ERR_FATAL, |
8dd93d45 | 118 | HW_EVENT_ERR_INFO, |
982216a4 MCC |
119 | }; |
120 | ||
8dd93d45 MCC |
121 | static inline char *mc_event_error_type(const unsigned int err_type) |
122 | { | |
123 | switch (err_type) { | |
124 | case HW_EVENT_ERR_CORRECTED: | |
125 | return "Corrected"; | |
126 | case HW_EVENT_ERR_UNCORRECTED: | |
127 | return "Uncorrected"; | |
d12a969e YG |
128 | case HW_EVENT_ERR_DEFERRED: |
129 | return "Deferred"; | |
8dd93d45 MCC |
130 | case HW_EVENT_ERR_FATAL: |
131 | return "Fatal"; | |
132 | default: | |
133 | case HW_EVENT_ERR_INFO: | |
134 | return "Info"; | |
135 | } | |
136 | } | |
137 | ||
01a6e28b MCC |
138 | /** |
139 | * enum mem_type - memory types. For a more detailed reference, please see | |
140 | * http://en.wikipedia.org/wiki/DRAM | |
141 | * | |
e0020758 | 142 | * @MEM_EMPTY: Empty csrow |
01a6e28b MCC |
143 | * @MEM_RESERVED: Reserved csrow type |
144 | * @MEM_UNKNOWN: Unknown csrow type | |
145 | * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. | |
146 | * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. | |
147 | * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. | |
148 | * @MEM_SDR: SDR - Single data rate SDRAM | |
149 | * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory | |
150 | * They use 3 pins for chip select: Pins 0 and 2 are | |
151 | * for rank 0; pins 1 and 3 are for rank 1, if the memory | |
152 | * is dual-rank. | |
153 | * @MEM_RDR: Registered SDR SDRAM | |
154 | * @MEM_DDR: Double data rate SDRAM | |
155 | * http://en.wikipedia.org/wiki/DDR_SDRAM | |
156 | * @MEM_RDDR: Registered Double data rate SDRAM | |
157 | * This is a variant of the DDR memories. | |
158 | * A registered memory has a buffer inside it, hiding | |
159 | * part of the memory details to the memory controller. | |
160 | * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. | |
161 | * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. | |
eca90a3b AA |
162 | * Those memories are labeled as "PC2-" instead of "PC" to |
163 | * differentiate from DDR. | |
01a6e28b MCC |
164 | * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 |
165 | * and JESD206. | |
166 | * Those memories are accessed per DIMM slot, and not by | |
167 | * a chip select signal. | |
168 | * @MEM_RDDR2: Registered DDR2 RAM | |
169 | * This is a variant of the DDR2 memories. | |
170 | * @MEM_XDR: Rambus XDR | |
171 | * It is an evolution of the original RAMBUS memories, | |
172 | * created to compete with DDR2. Weren't used on any | |
173 | * x86 arch, but cell_edac PPC memory controller uses it. | |
174 | * @MEM_DDR3: DDR3 RAM | |
175 | * @MEM_RDDR3: Registered DDR3 RAM | |
176 | * This is a variant of the DDR3 memories. | |
1e8096bb | 177 | * @MEM_LRDDR3: Load-Reduced DDR3 memory. |
3b203693 | 178 | * @MEM_LPDDR3: Low-Power DDR3 memory. |
348fec70 | 179 | * @MEM_DDR4: Unbuffered DDR4 RAM |
7b827835 AR |
180 | * @MEM_RDDR4: Registered DDR4 RAM |
181 | * This is a variant of the DDR4 memories. | |
1e8096bb | 182 | * @MEM_LRDDR4: Load-Reduced DDR4 memory. |
3b203693 | 183 | * @MEM_LPDDR4: Low-Power DDR4 memory. |
bc1c99a5 | 184 | * @MEM_DDR5: Unbuffered DDR5 RAM |
001f8613 | 185 | * @MEM_NVDIMM: Non-volatile RAM |
3b203693 | 186 | * @MEM_WIO2: Wide I/O 2. |
e1ca90b7 | 187 | * @MEM_HBM2: High bandwidth Memory Gen 2. |
01a6e28b | 188 | */ |
ddeb3547 | 189 | enum mem_type { |
01a6e28b MCC |
190 | MEM_EMPTY = 0, |
191 | MEM_RESERVED, | |
192 | MEM_UNKNOWN, | |
193 | MEM_FPM, | |
194 | MEM_EDO, | |
195 | MEM_BEDO, | |
196 | MEM_SDR, | |
197 | MEM_RDR, | |
198 | MEM_DDR, | |
199 | MEM_RDDR, | |
200 | MEM_RMBS, | |
201 | MEM_DDR2, | |
202 | MEM_FB_DDR2, | |
203 | MEM_RDDR2, | |
204 | MEM_XDR, | |
205 | MEM_DDR3, | |
206 | MEM_RDDR3, | |
348fec70 | 207 | MEM_LRDDR3, |
3b203693 | 208 | MEM_LPDDR3, |
7b827835 AR |
209 | MEM_DDR4, |
210 | MEM_RDDR4, | |
1e8096bb | 211 | MEM_LRDDR4, |
3b203693 | 212 | MEM_LPDDR4, |
bc1c99a5 | 213 | MEM_DDR5, |
001f8613 | 214 | MEM_NVDIMM, |
3b203693 | 215 | MEM_WIO2, |
e1ca90b7 | 216 | MEM_HBM2, |
ddeb3547 MCC |
217 | }; |
218 | ||
219 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | |
220 | #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) | |
221 | #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) | |
222 | #define MEM_FLAG_FPM BIT(MEM_FPM) | |
223 | #define MEM_FLAG_EDO BIT(MEM_EDO) | |
224 | #define MEM_FLAG_BEDO BIT(MEM_BEDO) | |
225 | #define MEM_FLAG_SDR BIT(MEM_SDR) | |
226 | #define MEM_FLAG_RDR BIT(MEM_RDR) | |
227 | #define MEM_FLAG_DDR BIT(MEM_DDR) | |
228 | #define MEM_FLAG_RDDR BIT(MEM_RDDR) | |
229 | #define MEM_FLAG_RMBS BIT(MEM_RMBS) | |
230 | #define MEM_FLAG_DDR2 BIT(MEM_DDR2) | |
231 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) | |
232 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) | |
233 | #define MEM_FLAG_XDR BIT(MEM_XDR) | |
255379ae JS |
234 | #define MEM_FLAG_DDR3 BIT(MEM_DDR3) |
235 | #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) | |
3b203693 | 236 | #define MEM_FLAG_LPDDR3 BIT(MEM_LPDDR3) |
255379ae JS |
237 | #define MEM_FLAG_DDR4 BIT(MEM_DDR4) |
238 | #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4) | |
1e8096bb | 239 | #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) |
3b203693 | 240 | #define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4) |
bc1c99a5 | 241 | #define MEM_FLAG_DDR5 BIT(MEM_DDR5) |
001f8613 | 242 | #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) |
3b203693 | 243 | #define MEM_FLAG_WIO2 BIT(MEM_WIO2) |
e1ca90b7 | 244 | #define MEM_FLAG_HBM2 BIT(MEM_HBM2) |
ddeb3547 | 245 | |
b0610bb8 | 246 | /** |
24269999 | 247 | * enum edac_type - Error Detection and Correction capabilities and mode |
b0610bb8 MCC |
248 | * @EDAC_UNKNOWN: Unknown if ECC is available |
249 | * @EDAC_NONE: Doesn't support ECC | |
250 | * @EDAC_RESERVED: Reserved ECC type | |
251 | * @EDAC_PARITY: Detects parity errors | |
252 | * @EDAC_EC: Error Checking - no correction | |
253 | * @EDAC_SECDED: Single bit error correction, Double detection | |
254 | * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? | |
255 | * @EDAC_S4ECD4ED: Chipkill x4 devices | |
256 | * @EDAC_S8ECD8ED: Chipkill x8 devices | |
257 | * @EDAC_S16ECD16ED: Chipkill x16 devices | |
258 | */ | |
ddeb3547 | 259 | enum edac_type { |
b0610bb8 MCC |
260 | EDAC_UNKNOWN = 0, |
261 | EDAC_NONE, | |
262 | EDAC_RESERVED, | |
263 | EDAC_PARITY, | |
264 | EDAC_EC, | |
265 | EDAC_SECDED, | |
266 | EDAC_S2ECD2ED, | |
267 | EDAC_S4ECD4ED, | |
268 | EDAC_S8ECD8ED, | |
269 | EDAC_S16ECD16ED, | |
ddeb3547 MCC |
270 | }; |
271 | ||
272 | #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) | |
273 | #define EDAC_FLAG_NONE BIT(EDAC_NONE) | |
274 | #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) | |
275 | #define EDAC_FLAG_EC BIT(EDAC_EC) | |
276 | #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) | |
277 | #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) | |
278 | #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) | |
279 | #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) | |
280 | #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) | |
281 | ||
b0610bb8 MCC |
282 | /** |
283 | * enum scrub_type - scrubbing capabilities | |
e0020758 | 284 | * @SCRUB_UNKNOWN: Unknown if scrubber is available |
b0610bb8 MCC |
285 | * @SCRUB_NONE: No scrubber |
286 | * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing | |
287 | * @SCRUB_SW_SRC: Software scrub only errors | |
288 | * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error | |
289 | * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable | |
290 | * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing | |
291 | * @SCRUB_HW_SRC: Hardware scrub only errors | |
292 | * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error | |
e0020758 | 293 | * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable |
b0610bb8 | 294 | */ |
ddeb3547 | 295 | enum scrub_type { |
b0610bb8 MCC |
296 | SCRUB_UNKNOWN = 0, |
297 | SCRUB_NONE, | |
298 | SCRUB_SW_PROG, | |
299 | SCRUB_SW_SRC, | |
300 | SCRUB_SW_PROG_SRC, | |
301 | SCRUB_SW_TUNABLE, | |
302 | SCRUB_HW_PROG, | |
303 | SCRUB_HW_SRC, | |
304 | SCRUB_HW_PROG_SRC, | |
305 | SCRUB_HW_TUNABLE | |
ddeb3547 MCC |
306 | }; |
307 | ||
308 | #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) | |
309 | #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) | |
310 | #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) | |
311 | #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) | |
312 | #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) | |
313 | #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) | |
314 | #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) | |
315 | #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) | |
316 | ||
317 | /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ | |
318 | ||
319 | /* EDAC internal operation states */ | |
320 | #define OP_ALLOC 0x100 | |
321 | #define OP_RUNNING_POLL 0x201 | |
322 | #define OP_RUNNING_INTERRUPT 0x202 | |
323 | #define OP_RUNNING_POLL_INTR 0x203 | |
324 | #define OP_OFFLINE 0x300 | |
325 | ||
982216a4 | 326 | /** |
24269999 | 327 | * enum edac_mc_layer_type - memory controller hierarchy layer |
982216a4 MCC |
328 | * |
329 | * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" | |
330 | * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" | |
331 | * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" | |
332 | * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" | |
c66b5a79 MCC |
333 | * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped |
334 | * as a single memory area. This is used when | |
335 | * retrieving errors from a firmware driven driver. | |
982216a4 MCC |
336 | * |
337 | * This enum is used by the drivers to tell edac_mc_sysfs what name should | |
338 | * be used when describing a memory stick location. | |
339 | */ | |
340 | enum edac_mc_layer_type { | |
341 | EDAC_MC_LAYER_BRANCH, | |
342 | EDAC_MC_LAYER_CHANNEL, | |
343 | EDAC_MC_LAYER_SLOT, | |
344 | EDAC_MC_LAYER_CHIP_SELECT, | |
c66b5a79 | 345 | EDAC_MC_LAYER_ALL_MEM, |
982216a4 MCC |
346 | }; |
347 | ||
348 | /** | |
349 | * struct edac_mc_layer - describes the memory controller hierarchy | |
e0020758 | 350 | * @type: layer type |
982216a4 MCC |
351 | * @size: number of components per layer. For example, |
352 | * if the channel layer has two channels, size = 2 | |
353 | * @is_virt_csrow: This layer is part of the "csrow" when old API | |
354 | * compatibility mode is enabled. Otherwise, it is | |
355 | * a channel | |
356 | */ | |
357 | struct edac_mc_layer { | |
358 | enum edac_mc_layer_type type; | |
359 | unsigned size; | |
360 | bool is_virt_csrow; | |
361 | }; | |
362 | ||
363 | /* | |
364 | * Maximum number of layers used by the memory controller to uniquely | |
365 | * identify a single memory stick. | |
366 | * NOTE: Changing this constant requires not only to change the constant | |
367 | * below, but also to change the existing code at the core, as there are | |
368 | * some code there that are optimized for 3 layers. | |
369 | */ | |
370 | #define EDAC_MAX_LAYERS 3 | |
371 | ||
a7d7d2e1 | 372 | struct dimm_info { |
7a623c03 MCC |
373 | struct device dev; |
374 | ||
a7d7d2e1 | 375 | char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ |
4275be63 MCC |
376 | |
377 | /* Memory location data */ | |
d55c79ac | 378 | unsigned int location[EDAC_MAX_LAYERS]; |
4275be63 MCC |
379 | |
380 | struct mem_ctl_info *mci; /* the parent */ | |
977b1ce7 | 381 | unsigned int idx; /* index within the parent dimm array */ |
084a4fcc MCC |
382 | |
383 | u32 grain; /* granularity of reported error in bytes */ | |
384 | enum dev_type dtype; /* memory device type */ | |
385 | enum mem_type mtype; /* memory dimm type */ | |
386 | enum edac_type edac_mode; /* EDAC mode for this dimm */ | |
387 | ||
4275be63 | 388 | u32 nr_pages; /* number of pages on this dimm */ |
a895bf8b | 389 | |
d55c79ac | 390 | unsigned int csrow, cschannel; /* Points to the old API data */ |
c798c88f FW |
391 | |
392 | u16 smbios_handle; /* Handle for SMBIOS type 17 */ | |
4aa92c86 RR |
393 | |
394 | u32 ce_count; | |
395 | u32 ue_count; | |
a7d7d2e1 MCC |
396 | }; |
397 | ||
a4b4be3f MCC |
398 | /** |
399 | * struct rank_info - contains the information for one DIMM rank | |
400 | * | |
401 | * @chan_idx: channel number where the rank is (typically, 0 or 1) | |
402 | * @ce_count: number of correctable errors for this rank | |
a4b4be3f MCC |
403 | * @csrow: A pointer to the chip select row structure (the parent |
404 | * structure). The location of the rank is given by | |
405 | * the (csrow->csrow_idx, chan_idx) vector. | |
a7d7d2e1 MCC |
406 | * @dimm: A pointer to the DIMM structure, where the DIMM label |
407 | * information is stored. | |
408 | * | |
409 | * FIXME: Currently, the EDAC core model will assume one DIMM per rank. | |
410 | * This is a bad assumption, but it makes this patch easier. Later | |
411 | * patches in this series will fix this issue. | |
a4b4be3f MCC |
412 | */ |
413 | struct rank_info { | |
414 | int chan_idx; | |
a7d7d2e1 MCC |
415 | struct csrow_info *csrow; |
416 | struct dimm_info *dimm; | |
4275be63 MCC |
417 | |
418 | u32 ce_count; /* Correctable Errors for this csrow */ | |
ddeb3547 MCC |
419 | }; |
420 | ||
421 | struct csrow_info { | |
7a623c03 MCC |
422 | struct device dev; |
423 | ||
a895bf8b | 424 | /* Used only by edac_mc_find_csrow_by_page() */ |
084a4fcc MCC |
425 | unsigned long first_page; /* first page number in csrow */ |
426 | unsigned long last_page; /* last page number in csrow */ | |
ddeb3547 | 427 | unsigned long page_mask; /* used for interleaving - |
a895bf8b MCC |
428 | * 0UL for non intlv */ |
429 | ||
084a4fcc MCC |
430 | int csrow_idx; /* the chip-select row */ |
431 | ||
ddeb3547 MCC |
432 | u32 ue_count; /* Uncorrectable Errors for this csrow */ |
433 | u32 ce_count; /* Correctable Errors for this csrow */ | |
084a4fcc | 434 | |
ddeb3547 MCC |
435 | struct mem_ctl_info *mci; /* the parent */ |
436 | ||
ddeb3547 MCC |
437 | /* channel information for this csrow */ |
438 | u32 nr_channels; | |
de3910eb | 439 | struct rank_info **channels; |
ddeb3547 MCC |
440 | }; |
441 | ||
7a623c03 MCC |
442 | /* |
443 | * struct errcount_attribute - used to store the several error counts | |
444 | */ | |
445 | struct errcount_attribute_data { | |
446 | int n_layers; | |
447 | int pos[EDAC_MAX_LAYERS]; | |
448 | int layer0, layer1, layer2; | |
ddeb3547 MCC |
449 | }; |
450 | ||
c7ef7645 | 451 | /** |
e0020758 | 452 | * struct edac_raw_error_desc - Raw error report structure |
c7ef7645 MCC |
453 | * @grain: minimum granularity for an error report, in bytes |
454 | * @error_count: number of errors of the same type | |
672ef0e5 | 455 | * @type: severity of the error (CE/UE/Fatal) |
c7ef7645 MCC |
456 | * @top_layer: top layer of the error (layer[0]) |
457 | * @mid_layer: middle layer of the error (layer[1]) | |
458 | * @low_layer: low layer of the error (layer[2]) | |
459 | * @page_frame_number: page where the error happened | |
460 | * @offset_in_page: page offset | |
461 | * @syndrome: syndrome of the error (or 0 if unknown or if | |
462 | * the syndrome is not applicable) | |
463 | * @msg: error message | |
464 | * @location: location of the error | |
465 | * @label: label of the affected DIMM(s) | |
466 | * @other_detail: other driver-specific detail about the error | |
c7ef7645 MCC |
467 | */ |
468 | struct edac_raw_error_desc { | |
c7ef7645 MCC |
469 | char location[LOCATION_SIZE]; |
470 | char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; | |
471 | long grain; | |
472 | ||
c7ef7645 | 473 | u16 error_count; |
672ef0e5 | 474 | enum hw_event_mc_err_type type; |
c7ef7645 MCC |
475 | int top_layer; |
476 | int mid_layer; | |
477 | int low_layer; | |
478 | unsigned long page_frame_number; | |
479 | unsigned long offset_in_page; | |
480 | unsigned long syndrome; | |
481 | const char *msg; | |
482 | const char *other_detail; | |
c7ef7645 MCC |
483 | }; |
484 | ||
ddeb3547 MCC |
485 | /* MEMORY controller information structure |
486 | */ | |
487 | struct mem_ctl_info { | |
7a623c03 | 488 | struct device dev; |
88d84ac9 | 489 | struct bus_type *bus; |
7a623c03 | 490 | |
ddeb3547 MCC |
491 | struct list_head link; /* for global list of mem_ctl_info structs */ |
492 | ||
493 | struct module *owner; /* Module owner of this control struct */ | |
494 | ||
495 | unsigned long mtype_cap; /* memory types supported by mc */ | |
496 | unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ | |
497 | unsigned long edac_cap; /* configuration capabilities - this is | |
498 | * closely related to edac_ctl_cap. The | |
499 | * difference is that the controller may be | |
500 | * capable of s4ecd4ed which would be listed | |
501 | * in edac_ctl_cap, but if channels aren't | |
502 | * capable of s4ecd4ed then the edac_cap would | |
503 | * not have that capability. | |
504 | */ | |
505 | unsigned long scrub_cap; /* chipset scrub capabilities */ | |
506 | enum scrub_type scrub_mode; /* current scrub mode */ | |
507 | ||
508 | /* Translates sdram memory scrub rate given in bytes/sec to the | |
509 | internal representation and configures whatever else needs | |
510 | to be configured. | |
511 | */ | |
512 | int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); | |
513 | ||
514 | /* Get the current sdram memory scrub rate from the internal | |
515 | representation and converts it to the closest matching | |
516 | bandwidth in bytes/sec. | |
517 | */ | |
518 | int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); | |
519 | ||
520 | ||
521 | /* pointer to edac checking routine */ | |
522 | void (*edac_check) (struct mem_ctl_info * mci); | |
523 | ||
524 | /* | |
525 | * Remaps memory pages: controller pages to physical pages. | |
526 | * For most MC's, this will be NULL. | |
527 | */ | |
528 | /* FIXME - why not send the phys page to begin with? */ | |
529 | unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, | |
530 | unsigned long page); | |
531 | int mc_idx; | |
de3910eb | 532 | struct csrow_info **csrows; |
d55c79ac | 533 | unsigned int nr_csrows, num_cschannel; |
4275be63 | 534 | |
7a623c03 MCC |
535 | /* |
536 | * Memory Controller hierarchy | |
537 | * | |
538 | * There are basically two types of memory controller: the ones that | |
539 | * sees memory sticks ("dimms"), and the ones that sees memory ranks. | |
540 | * All old memory controllers enumerate memories per rank, but most | |
541 | * of the recent drivers enumerate memories per DIMM, instead. | |
9713faec | 542 | * When the memory controller is per rank, csbased is true. |
7a623c03 | 543 | */ |
d55c79ac | 544 | unsigned int n_layers; |
4275be63 | 545 | struct edac_mc_layer *layers; |
9713faec | 546 | bool csbased; |
a7d7d2e1 MCC |
547 | |
548 | /* | |
549 | * DIMM info. Will eventually remove the entire csrows_info some day | |
550 | */ | |
d55c79ac | 551 | unsigned int tot_dimms; |
de3910eb | 552 | struct dimm_info **dimms; |
a7d7d2e1 | 553 | |
ddeb3547 MCC |
554 | /* |
555 | * FIXME - what about controllers on other busses? - IDs must be | |
556 | * unique. dev pointer should be sufficiently unique, but | |
557 | * BUS:SLOT.FUNC numbers may not be unique. | |
558 | */ | |
fd687502 | 559 | struct device *pdev; |
ddeb3547 | 560 | const char *mod_name; |
ddeb3547 MCC |
561 | const char *ctl_name; |
562 | const char *dev_name; | |
ddeb3547 | 563 | void *pvt_info; |
ddeb3547 MCC |
564 | unsigned long start_time; /* mci load start time (in jiffies) */ |
565 | ||
4275be63 MCC |
566 | /* |
567 | * drivers shouldn't access those fields directly, as the core | |
568 | * already handles that. | |
569 | */ | |
570 | u32 ce_noinfo_count, ue_noinfo_count; | |
5926ff50 | 571 | u32 ue_mc, ce_mc; |
4275be63 | 572 | |
ddeb3547 MCC |
573 | struct completion complete; |
574 | ||
ddeb3547 MCC |
575 | /* Additional top controller level attributes, but specified |
576 | * by the low level driver. | |
577 | * | |
578 | * Set by the low level driver to provide attributes at the | |
4275be63 | 579 | * controller level. |
ddeb3547 MCC |
580 | * An array of structures, NULL terminated |
581 | * | |
582 | * If attributes are desired, then set to array of attributes | |
583 | * If no attributes are desired, leave NULL | |
584 | */ | |
585 | const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; | |
586 | ||
587 | /* work struct for this MC */ | |
588 | struct delayed_work work; | |
589 | ||
c7ef7645 MCC |
590 | /* |
591 | * Used to report an error - by being at the global struct | |
592 | * makes the memory allocated by the EDAC core | |
593 | */ | |
594 | struct edac_raw_error_desc error_desc; | |
595 | ||
ddeb3547 MCC |
596 | /* the internal state of this controller instance */ |
597 | int op_state; | |
452a6bf9 | 598 | |
452a6bf9 MCC |
599 | struct dentry *debugfs; |
600 | u8 fake_inject_layer[EDAC_MAX_LAYERS]; | |
621a5f7a | 601 | bool fake_inject_ue; |
38ced28b | 602 | u16 fake_inject_count; |
ddeb3547 | 603 | }; |
bc9ad9e4 | 604 | |
c498afaf RR |
605 | #define mci_for_each_dimm(mci, dimm) \ |
606 | for ((dimm) = (mci)->dimms[0]; \ | |
607 | (dimm); \ | |
608 | (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \ | |
609 | ? (mci)->dimms[(dimm)->idx + 1] \ | |
610 | : NULL) | |
611 | ||
bc9ad9e4 RR |
612 | /** |
613 | * edac_get_dimm - Get DIMM info from a memory controller given by | |
614 | * [layer0,layer1,layer2] position | |
615 | * | |
616 | * @mci: MC descriptor struct mem_ctl_info | |
617 | * @layer0: layer0 position | |
618 | * @layer1: layer1 position. Unused if n_layers < 2 | |
619 | * @layer2: layer2 position. Unused if n_layers < 3 | |
620 | * | |
621 | * For 1 layer, this function returns "dimms[layer0]"; | |
622 | * | |
623 | * For 2 layers, this function is similar to allocating a two-dimensional | |
624 | * array and returning "dimms[layer0][layer1]"; | |
625 | * | |
626 | * For 3 layers, this function is similar to allocating a tri-dimensional | |
627 | * array and returning "dimms[layer0][layer1][layer2]"; | |
628 | */ | |
629 | static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci, | |
630 | int layer0, int layer1, int layer2) | |
631 | { | |
632 | int index; | |
633 | ||
634 | if (layer0 < 0 | |
635 | || (mci->n_layers > 1 && layer1 < 0) | |
636 | || (mci->n_layers > 2 && layer2 < 0)) | |
637 | return NULL; | |
638 | ||
639 | index = layer0; | |
640 | ||
641 | if (mci->n_layers > 1) | |
642 | index = index * mci->layers[1].size + layer1; | |
643 | ||
644 | if (mci->n_layers > 2) | |
645 | index = index * mci->layers[2].size + layer2; | |
646 | ||
e370f886 BP |
647 | if (index < 0 || index >= mci->tot_dimms) |
648 | return NULL; | |
649 | ||
650 | if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) | |
651 | return NULL; | |
652 | ||
653 | return mci->dimms[index]; | |
bc9ad9e4 RR |
654 | } |
655 | #endif /* _LINUX_EDAC_H_ */ |