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48257c4f PA |
1 | /* |
2 | * Platform information definitions for the | |
3 | * universal Freescale Ethernet driver. | |
4 | * | |
5 | * Copyright (c) 2003 Intracom S.A. | |
6 | * by Pantelis Antoniou <panto@intracom.gr> | |
7 | * | |
8 | * 2005 (c) MontaVista Software, Inc. | |
9 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public License | |
12 | * version 2. This program is licensed "as is" without any warranty of any | |
13 | * kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #ifndef FS_ENET_PD_H | |
17 | #define FS_ENET_PD_H | |
18 | ||
48257c4f PA |
19 | #include <asm/types.h> |
20 | ||
21 | #define FS_ENET_NAME "fs_enet" | |
22 | ||
23 | enum fs_id { | |
24 | fsid_fec1, | |
25 | fsid_fec2, | |
26 | fsid_fcc1, | |
27 | fsid_fcc2, | |
28 | fsid_fcc3, | |
29 | fsid_scc1, | |
30 | fsid_scc2, | |
31 | fsid_scc3, | |
32 | fsid_scc4, | |
33 | }; | |
34 | ||
35 | #define FS_MAX_INDEX 9 | |
36 | ||
37 | static inline int fs_get_fec_index(enum fs_id id) | |
38 | { | |
39 | if (id >= fsid_fec1 && id <= fsid_fec2) | |
40 | return id - fsid_fec1; | |
41 | return -1; | |
42 | } | |
43 | ||
44 | static inline int fs_get_fcc_index(enum fs_id id) | |
45 | { | |
46 | if (id >= fsid_fcc1 && id <= fsid_fcc3) | |
47 | return id - fsid_fcc1; | |
48 | return -1; | |
49 | } | |
50 | ||
51 | static inline int fs_get_scc_index(enum fs_id id) | |
52 | { | |
53 | if (id >= fsid_scc1 && id <= fsid_scc4) | |
54 | return id - fsid_scc1; | |
55 | return -1; | |
56 | } | |
57 | ||
58 | enum fs_mii_method { | |
59 | fsmii_fixed, | |
60 | fsmii_fec, | |
61 | fsmii_bitbang, | |
62 | }; | |
63 | ||
64 | enum fs_ioport { | |
65 | fsiop_porta, | |
66 | fsiop_portb, | |
67 | fsiop_portc, | |
68 | fsiop_portd, | |
69 | fsiop_porte, | |
70 | }; | |
71 | ||
2ca2d5e8 VB |
72 | struct fs_mii_bit { |
73 | u32 offset; | |
74 | u8 bit; | |
75 | u8 polarity; | |
76 | }; | |
77 | struct fs_mii_bb_platform_info { | |
78 | struct fs_mii_bit mdio_dir; | |
79 | struct fs_mii_bit mdio_dat; | |
80 | struct fs_mii_bit mdc_dat; | |
81 | int mdio_port; /* port & bit for MDIO */ | |
82 | int mdio_bit; | |
83 | int mdc_port; /* port & bit for MDC */ | |
84 | int mdc_bit; | |
85 | int delay; /* delay in us */ | |
86 | int irq[32]; /* irqs per phy's */ | |
48257c4f PA |
87 | }; |
88 | ||
89 | struct fs_platform_info { | |
d3465c92 VB |
90 | |
91 | void(*init_ioports)(struct fs_platform_info *); | |
48257c4f PA |
92 | /* device specific information */ |
93 | int fs_no; /* controller index */ | |
94 | ||
95 | u32 cp_page; /* CPM page */ | |
96 | u32 cp_block; /* CPM sblock */ | |
d3465c92 | 97 | |
48257c4f | 98 | u32 clk_trx; /* some stuff for pins & mux configuration*/ |
d3465c92 VB |
99 | u32 clk_rx; |
100 | u32 clk_tx; | |
48257c4f PA |
101 | u32 clk_route; |
102 | u32 clk_mask; | |
d3465c92 | 103 | |
48257c4f PA |
104 | u32 mem_offset; |
105 | u32 dpram_offset; | |
106 | u32 fcc_regs_c; | |
107 | ||
108 | u32 device_flags; | |
109 | ||
110 | int phy_addr; /* the phy address (-1 no phy) */ | |
2ca2d5e8 | 111 | const char* bus_id; |
48257c4f PA |
112 | int phy_irq; /* the phy irq (if it exists) */ |
113 | ||
114 | const struct fs_mii_bus_info *bus_info; | |
115 | ||
116 | int rx_ring, tx_ring; /* number of buffers on rx */ | |
117 | __u8 macaddr[6]; /* mac address */ | |
118 | int rx_copybreak; /* limit we copy small frames */ | |
119 | int use_napi; /* use NAPI */ | |
120 | int napi_weight; /* NAPI weight */ | |
121 | ||
122 | int use_rmii; /* use RMII mode */ | |
2ca2d5e8 VB |
123 | int has_phy; /* if the network is phy container as well...*/ |
124 | }; | |
125 | struct fs_mii_fec_platform_info { | |
126 | u32 irq[32]; | |
127 | u32 mii_speed; | |
48257c4f | 128 | }; |
48257c4f | 129 | #endif |