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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
79a9becd AC |
2 | #ifndef __LINUX_GPIO_DRIVER_H |
3 | #define __LINUX_GPIO_DRIVER_H | |
4 | ||
ff2b1359 | 5 | #include <linux/device.h> |
79a9becd | 6 | #include <linux/types.h> |
14250520 LW |
7 | #include <linux/irq.h> |
8 | #include <linux/irqchip/chained_irq.h> | |
9 | #include <linux/irqdomain.h> | |
a0a8bcf4 | 10 | #include <linux/lockdep.h> |
964cb341 | 11 | #include <linux/pinctrl/pinctrl.h> |
2956b5d9 | 12 | #include <linux/pinctrl/pinconf-generic.h> |
79a9becd | 13 | |
79a9becd | 14 | struct gpio_desc; |
c9a9972b AC |
15 | struct of_phandle_args; |
16 | struct device_node; | |
f3ed0b66 | 17 | struct seq_file; |
ff2b1359 | 18 | struct gpio_device; |
d47529b2 | 19 | struct module; |
21abf103 | 20 | enum gpiod_flags; |
79a9becd | 21 | |
bb1e88cc AC |
22 | #ifdef CONFIG_GPIOLIB |
23 | ||
c44eafd7 TR |
24 | #ifdef CONFIG_GPIOLIB_IRQCHIP |
25 | /** | |
26 | * struct gpio_irq_chip - GPIO interrupt controller | |
27 | */ | |
28 | struct gpio_irq_chip { | |
da80ff81 TR |
29 | /** |
30 | * @chip: | |
31 | * | |
32 | * GPIO IRQ chip implementation, provided by GPIO driver. | |
33 | */ | |
34 | struct irq_chip *chip; | |
35 | ||
f0fbe7bc TR |
36 | /** |
37 | * @domain: | |
38 | * | |
39 | * Interrupt translation domain; responsible for mapping between GPIO | |
40 | * hwirq number and Linux IRQ number. | |
41 | */ | |
42 | struct irq_domain *domain; | |
43 | ||
c44eafd7 TR |
44 | /** |
45 | * @domain_ops: | |
46 | * | |
47 | * Table of interrupt domain operations for this IRQ chip. | |
48 | */ | |
49 | const struct irq_domain_ops *domain_ops; | |
50 | ||
c7a0aa59 TR |
51 | /** |
52 | * @handler: | |
53 | * | |
54 | * The IRQ handler to use (often a predefined IRQ core function) for | |
55 | * GPIO IRQs, provided by GPIO driver. | |
56 | */ | |
57 | irq_flow_handler_t handler; | |
58 | ||
3634eeb0 TR |
59 | /** |
60 | * @default_type: | |
61 | * | |
62 | * Default IRQ triggering type applied during GPIO driver | |
63 | * initialization, provided by GPIO driver. | |
64 | */ | |
65 | unsigned int default_type; | |
66 | ||
ca9df053 TR |
67 | /** |
68 | * @lock_key: | |
69 | * | |
02ad0437 | 70 | * Per GPIO IRQ chip lockdep class for IRQ lock. |
ca9df053 TR |
71 | */ |
72 | struct lock_class_key *lock_key; | |
02ad0437 RD |
73 | |
74 | /** | |
75 | * @request_key: | |
76 | * | |
77 | * Per GPIO IRQ chip lockdep class for IRQ request. | |
78 | */ | |
39c3fd58 | 79 | struct lock_class_key *request_key; |
ca9df053 | 80 | |
c44eafd7 TR |
81 | /** |
82 | * @parent_handler: | |
83 | * | |
84 | * The interrupt handler for the GPIO chip's parent interrupts, may be | |
85 | * NULL if the parent interrupts are nested rather than cascaded. | |
86 | */ | |
87 | irq_flow_handler_t parent_handler; | |
88 | ||
89 | /** | |
90 | * @parent_handler_data: | |
91 | * | |
92 | * Data associated, and passed to, the handler for the parent | |
93 | * interrupt. | |
94 | */ | |
95 | void *parent_handler_data; | |
39e5f096 TR |
96 | |
97 | /** | |
98 | * @num_parents: | |
99 | * | |
100 | * The number of interrupt parents of a GPIO chip. | |
101 | */ | |
102 | unsigned int num_parents; | |
103 | ||
3e779a2e SB |
104 | /** |
105 | * @parent_irq: | |
106 | * | |
107 | * For use by gpiochip_set_cascaded_irqchip() | |
108 | */ | |
109 | unsigned int parent_irq; | |
110 | ||
39e5f096 TR |
111 | /** |
112 | * @parents: | |
113 | * | |
114 | * A list of interrupt parents of a GPIO chip. This is owned by the | |
115 | * driver, so the core will only reference this list, not modify it. | |
116 | */ | |
117 | unsigned int *parents; | |
dc6bafee | 118 | |
e0d89728 TR |
119 | /** |
120 | * @map: | |
121 | * | |
122 | * A list of interrupt parents for each line of a GPIO chip. | |
123 | */ | |
124 | unsigned int *map; | |
125 | ||
dc6bafee | 126 | /** |
60ed54ca | 127 | * @threaded: |
dc6bafee | 128 | * |
60ed54ca | 129 | * True if set the interrupt handling uses nested threads. |
dc6bafee | 130 | */ |
60ed54ca | 131 | bool threaded; |
dc7b0387 TR |
132 | |
133 | /** | |
134 | * @need_valid_mask: | |
135 | * | |
136 | * If set core allocates @valid_mask with all bits set to one. | |
137 | */ | |
138 | bool need_valid_mask; | |
139 | ||
140 | /** | |
141 | * @valid_mask: | |
142 | * | |
143 | * If not %NULL holds bitmask of GPIOs which are valid to be included | |
144 | * in IRQ domain of the chip. | |
145 | */ | |
146 | unsigned long *valid_mask; | |
8302cf58 TR |
147 | |
148 | /** | |
149 | * @first: | |
150 | * | |
151 | * Required for static IRQ allocation. If set, irq_domain_add_simple() | |
152 | * will allocate and map all IRQs during initialization. | |
153 | */ | |
154 | unsigned int first; | |
461c1a7d HV |
155 | |
156 | /** | |
157 | * @irq_enable: | |
158 | * | |
159 | * Store old irq_chip irq_enable callback | |
160 | */ | |
161 | void (*irq_enable)(struct irq_data *data); | |
162 | ||
163 | /** | |
164 | * @irq_disable: | |
165 | * | |
166 | * Store old irq_chip irq_disable callback | |
167 | */ | |
168 | void (*irq_disable)(struct irq_data *data); | |
c44eafd7 TR |
169 | }; |
170 | #endif | |
171 | ||
79a9becd AC |
172 | /** |
173 | * struct gpio_chip - abstract a GPIO controller | |
df4878e9 LW |
174 | * @label: a functional name for the GPIO device, such as a part |
175 | * number or the name of the SoC IP-block implementing it. | |
ff2b1359 | 176 | * @gpiodev: the internal state holder, opaque struct |
58383c78 | 177 | * @parent: optional parent device providing the GPIOs |
79a9becd | 178 | * @owner: helps prevent removal of modules exporting active GPIOs |
79a9becd AC |
179 | * @request: optional hook for chip-specific activation, such as |
180 | * enabling module power and clock; may sleep | |
181 | * @free: optional hook for chip-specific deactivation, such as | |
182 | * disabling module power and clock; may sleep | |
183 | * @get_direction: returns direction for signal "offset", 0=out, 1=in, | |
e48d194d LW |
184 | * (same as GPIOF_DIR_XXX), or negative error. |
185 | * It is recommended to always implement this function, even on | |
186 | * input-only or output-only gpio chips. | |
79a9becd | 187 | * @direction_input: configures signal "offset" as input, or returns error |
e48d194d | 188 | * This can be omitted on input-only or output-only gpio chips. |
79a9becd | 189 | * @direction_output: configures signal "offset" as output, or returns error |
e48d194d | 190 | * This can be omitted on input-only or output-only gpio chips. |
60befd2e | 191 | * @get: returns value for signal "offset", 0=low, 1=high, or negative error |
eec1d566 LW |
192 | * @get_multiple: reads values for multiple signals defined by "mask" and |
193 | * stores them in "bits", returns 0 on success or negative error | |
79a9becd | 194 | * @set: assigns output value for signal "offset" |
5f424243 | 195 | * @set_multiple: assigns output values for multiple signals defined by "mask" |
2956b5d9 MW |
196 | * @set_config: optional hook for all kinds of settings. Uses the same |
197 | * packed config format as generic pinconf. | |
79a9becd AC |
198 | * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; |
199 | * implementation may not sleep | |
200 | * @dbg_show: optional routine to show contents in debugfs; default code | |
201 | * will be used when this is omitted, but custom code can show extra | |
202 | * state (such as pullup/pulldown configuration). | |
af6c235d LW |
203 | * @base: identifies the first GPIO number handled by this chip; |
204 | * or, if negative during registration, requests dynamic ID allocation. | |
205 | * DEPRECATION: providing anything non-negative and nailing the base | |
30bb6fb3 | 206 | * offset of GPIO chips is deprecated. Please pass -1 as base to |
af6c235d LW |
207 | * let gpiolib select the chip base in all possible cases. We want to |
208 | * get rid of the static GPIO number space in the long run. | |
79a9becd AC |
209 | * @ngpio: the number of GPIOs handled by this controller; the last GPIO |
210 | * handled is (base + ngpio - 1). | |
79a9becd AC |
211 | * @names: if set, must be an array of strings to use as alternative |
212 | * names for the GPIOs in this chip. Any entry in the array | |
213 | * may be NULL if there is no alias for the GPIO, however the | |
214 | * array must be @ngpio entries long. A name can include a single printk | |
215 | * format specifier for an unsigned int. It is substituted by the actual | |
216 | * number of the gpio. | |
9fb1f39e | 217 | * @can_sleep: flag must be set iff get()/set() methods sleep, as they |
1c8732bb LW |
218 | * must while accessing GPIO expander chips over I2C or SPI. This |
219 | * implies that if the chip supports IRQs, these IRQs need to be threaded | |
220 | * as the chip access may sleep when e.g. reading out the IRQ status | |
221 | * registers. | |
0f4630f3 LW |
222 | * @read_reg: reader function for generic GPIO |
223 | * @write_reg: writer function for generic GPIO | |
24efd94b LW |
224 | * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing |
225 | * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the | |
226 | * generic GPIO core. It is for internal housekeeping only. | |
0f4630f3 LW |
227 | * @reg_dat: data (in) register for generic GPIO |
228 | * @reg_set: output set register (out=high) for generic GPIO | |
08bcd3ed | 229 | * @reg_clr: output clear register (out=low) for generic GPIO |
0f4630f3 | 230 | * @reg_dir: direction setting register for generic GPIO |
d799a4de LW |
231 | * @bgpio_dir_inverted: indicates that the direction register is inverted |
232 | * (gpiolib private state variable) | |
0f4630f3 LW |
233 | * @bgpio_bits: number of register bits used for a generic GPIO i.e. |
234 | * <register width> * 8 | |
235 | * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep | |
236 | * shadowed and real data registers writes together. | |
237 | * @bgpio_data: shadowed data register for generic GPIO to clear/set bits | |
238 | * safely. | |
239 | * @bgpio_dir: shadowed direction register for generic GPIO to clear/set | |
240 | * direction safely. | |
79a9becd AC |
241 | * |
242 | * A gpio_chip can help platforms abstract various sources of GPIOs so | |
243 | * they can all be accessed through a common programing interface. | |
244 | * Example sources would be SOC controllers, FPGAs, multifunction | |
245 | * chips, dedicated GPIO expanders, and so on. | |
246 | * | |
247 | * Each chip controls a number of signals, identified in method calls | |
248 | * by "offset" values in the range 0..(@ngpio - 1). When those signals | |
249 | * are referenced through calls like gpio_get_value(gpio), the offset | |
250 | * is calculated by subtracting @base from the gpio number. | |
251 | */ | |
252 | struct gpio_chip { | |
253 | const char *label; | |
ff2b1359 | 254 | struct gpio_device *gpiodev; |
58383c78 | 255 | struct device *parent; |
79a9becd | 256 | struct module *owner; |
79a9becd AC |
257 | |
258 | int (*request)(struct gpio_chip *chip, | |
259 | unsigned offset); | |
260 | void (*free)(struct gpio_chip *chip, | |
261 | unsigned offset); | |
262 | int (*get_direction)(struct gpio_chip *chip, | |
263 | unsigned offset); | |
264 | int (*direction_input)(struct gpio_chip *chip, | |
265 | unsigned offset); | |
266 | int (*direction_output)(struct gpio_chip *chip, | |
267 | unsigned offset, int value); | |
268 | int (*get)(struct gpio_chip *chip, | |
269 | unsigned offset); | |
eec1d566 LW |
270 | int (*get_multiple)(struct gpio_chip *chip, |
271 | unsigned long *mask, | |
272 | unsigned long *bits); | |
79a9becd AC |
273 | void (*set)(struct gpio_chip *chip, |
274 | unsigned offset, int value); | |
5f424243 RI |
275 | void (*set_multiple)(struct gpio_chip *chip, |
276 | unsigned long *mask, | |
277 | unsigned long *bits); | |
2956b5d9 MW |
278 | int (*set_config)(struct gpio_chip *chip, |
279 | unsigned offset, | |
280 | unsigned long config); | |
79a9becd AC |
281 | int (*to_irq)(struct gpio_chip *chip, |
282 | unsigned offset); | |
283 | ||
284 | void (*dbg_show)(struct seq_file *s, | |
285 | struct gpio_chip *chip); | |
f8ec92a9 RRD |
286 | |
287 | int (*init_valid_mask)(struct gpio_chip *chip); | |
288 | ||
79a9becd AC |
289 | int base; |
290 | u16 ngpio; | |
79a9becd | 291 | const char *const *names; |
9fb1f39e | 292 | bool can_sleep; |
79a9becd | 293 | |
0f4630f3 LW |
294 | #if IS_ENABLED(CONFIG_GPIO_GENERIC) |
295 | unsigned long (*read_reg)(void __iomem *reg); | |
296 | void (*write_reg)(void __iomem *reg, unsigned long data); | |
24efd94b | 297 | bool be_bits; |
0f4630f3 LW |
298 | void __iomem *reg_dat; |
299 | void __iomem *reg_set; | |
300 | void __iomem *reg_clr; | |
301 | void __iomem *reg_dir; | |
d799a4de | 302 | bool bgpio_dir_inverted; |
0f4630f3 LW |
303 | int bgpio_bits; |
304 | spinlock_t bgpio_lock; | |
305 | unsigned long bgpio_data; | |
306 | unsigned long bgpio_dir; | |
307 | #endif | |
308 | ||
14250520 LW |
309 | #ifdef CONFIG_GPIOLIB_IRQCHIP |
310 | /* | |
7d75a871 | 311 | * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib |
14250520 LW |
312 | * to handle IRQs for most practical cases. |
313 | */ | |
c44eafd7 TR |
314 | |
315 | /** | |
316 | * @irq: | |
317 | * | |
318 | * Integrates interrupt chip functionality with the GPIO chip. Can be | |
319 | * used to handle IRQs for most practical cases. | |
320 | */ | |
321 | struct gpio_irq_chip irq; | |
14250520 LW |
322 | #endif |
323 | ||
726cb3ba SB |
324 | /** |
325 | * @need_valid_mask: | |
326 | * | |
f8ec92a9 RRD |
327 | * If set core allocates @valid_mask with all its values initialized |
328 | * with init_valid_mask() or set to one if init_valid_mask() is not | |
329 | * defined | |
726cb3ba SB |
330 | */ |
331 | bool need_valid_mask; | |
332 | ||
333 | /** | |
334 | * @valid_mask: | |
335 | * | |
336 | * If not %NULL holds bitmask of GPIOs which are valid to be used | |
337 | * from the chip. | |
338 | */ | |
339 | unsigned long *valid_mask; | |
340 | ||
79a9becd AC |
341 | #if defined(CONFIG_OF_GPIO) |
342 | /* | |
343 | * If CONFIG_OF is enabled, then all GPIO controllers described in the | |
344 | * device tree automatically may have an OF translation | |
345 | */ | |
67049c50 TR |
346 | |
347 | /** | |
348 | * @of_node: | |
349 | * | |
350 | * Pointer to a device tree node representing this GPIO controller. | |
351 | */ | |
79a9becd | 352 | struct device_node *of_node; |
67049c50 TR |
353 | |
354 | /** | |
355 | * @of_gpio_n_cells: | |
356 | * | |
357 | * Number of cells used to form the GPIO specifier. | |
358 | */ | |
e3b445d7 | 359 | unsigned int of_gpio_n_cells; |
67049c50 TR |
360 | |
361 | /** | |
362 | * @of_xlate: | |
363 | * | |
364 | * Callback to translate a device tree GPIO specifier into a chip- | |
365 | * relative GPIO number and flags. | |
366 | */ | |
79a9becd AC |
367 | int (*of_xlate)(struct gpio_chip *gc, |
368 | const struct of_phandle_args *gpiospec, u32 *flags); | |
369 | #endif | |
79a9becd AC |
370 | }; |
371 | ||
372 | extern const char *gpiochip_is_requested(struct gpio_chip *chip, | |
373 | unsigned offset); | |
374 | ||
375 | /* add/remove chips */ | |
959bc7b2 | 376 | extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, |
39c3fd58 AL |
377 | struct lock_class_key *lock_key, |
378 | struct lock_class_key *request_key); | |
959bc7b2 TR |
379 | |
380 | /** | |
381 | * gpiochip_add_data() - register a gpio_chip | |
382 | * @chip: the chip to register, with chip->base initialized | |
383 | * @data: driver-private data associated with this chip | |
384 | * | |
385 | * Context: potentially before irqs will work | |
386 | * | |
387 | * When gpiochip_add_data() is called very early during boot, so that GPIOs | |
388 | * can be freely used, the chip->parent device must be registered before | |
389 | * the gpio framework's arch_initcall(). Otherwise sysfs initialization | |
390 | * for GPIOs will fail rudely. | |
391 | * | |
392 | * gpiochip_add_data() must only be called after gpiolib initialization, | |
393 | * ie after core_initcall(). | |
394 | * | |
395 | * If chip->base is negative, this requests dynamic assignment of | |
396 | * a range of valid GPIOs. | |
397 | * | |
398 | * Returns: | |
399 | * A negative errno if the chip can't be registered, such as because the | |
400 | * chip->base is invalid or already associated with a different chip. | |
401 | * Otherwise it returns zero as a success code. | |
402 | */ | |
403 | #ifdef CONFIG_LOCKDEP | |
404 | #define gpiochip_add_data(chip, data) ({ \ | |
39c3fd58 AL |
405 | static struct lock_class_key lock_key; \ |
406 | static struct lock_class_key request_key; \ | |
407 | gpiochip_add_data_with_key(chip, data, &lock_key, \ | |
408 | &request_key); \ | |
959bc7b2 TR |
409 | }) |
410 | #else | |
39c3fd58 | 411 | #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL) |
959bc7b2 TR |
412 | #endif |
413 | ||
b08ea35a LW |
414 | static inline int gpiochip_add(struct gpio_chip *chip) |
415 | { | |
416 | return gpiochip_add_data(chip, NULL); | |
417 | } | |
e1db1706 | 418 | extern void gpiochip_remove(struct gpio_chip *chip); |
0cf3292c LD |
419 | extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, |
420 | void *data); | |
0cf3292c | 421 | |
79a9becd AC |
422 | extern struct gpio_chip *gpiochip_find(void *data, |
423 | int (*match)(struct gpio_chip *chip, void *data)); | |
424 | ||
425 | /* lock/unlock as IRQ */ | |
e3a2e878 AC |
426 | int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); |
427 | void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); | |
6cee3821 | 428 | bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset); |
4e6b8238 HV |
429 | int gpiochip_reqres_irq(struct gpio_chip *chip, unsigned int offset); |
430 | void gpiochip_relres_irq(struct gpio_chip *chip, unsigned int offset); | |
4e9439dd HV |
431 | void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset); |
432 | void gpiochip_enable_irq(struct gpio_chip *chip, unsigned int offset); | |
79a9becd | 433 | |
143b65d6 LW |
434 | /* Line status inquiry for drivers */ |
435 | bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset); | |
436 | bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); | |
437 | ||
05f479bf CK |
438 | /* Sleep persistence inquiry for drivers */ |
439 | bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset); | |
726cb3ba | 440 | bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); |
05f479bf | 441 | |
b08ea35a | 442 | /* get driver data */ |
43c54eca | 443 | void *gpiochip_get_data(struct gpio_chip *chip); |
b08ea35a | 444 | |
bb1e88cc AC |
445 | struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); |
446 | ||
0f4630f3 LW |
447 | struct bgpio_pdata { |
448 | const char *label; | |
449 | int base; | |
450 | int ngpio; | |
451 | }; | |
452 | ||
c474e348 AB |
453 | #if IS_ENABLED(CONFIG_GPIO_GENERIC) |
454 | ||
0f4630f3 LW |
455 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
456 | unsigned long sz, void __iomem *dat, void __iomem *set, | |
457 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
458 | unsigned long flags); | |
459 | ||
460 | #define BGPIOF_BIG_ENDIAN BIT(0) | |
461 | #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ | |
462 | #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ | |
463 | #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) | |
464 | #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ | |
465 | #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ | |
466 | ||
467 | #endif | |
468 | ||
14250520 LW |
469 | #ifdef CONFIG_GPIOLIB_IRQCHIP |
470 | ||
1b95b4eb TR |
471 | int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, |
472 | irq_hw_number_t hwirq); | |
473 | void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); | |
474 | ||
ef74f70e BM |
475 | int gpiochip_irq_domain_activate(struct irq_domain *domain, |
476 | struct irq_data *data, bool reserve); | |
477 | void gpiochip_irq_domain_deactivate(struct irq_domain *domain, | |
478 | struct irq_data *data); | |
479 | ||
14250520 LW |
480 | void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, |
481 | struct irq_chip *irqchip, | |
6f79309a | 482 | unsigned int parent_irq, |
14250520 LW |
483 | irq_flow_handler_t parent_handler); |
484 | ||
d245b3f9 LW |
485 | void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip, |
486 | struct irq_chip *irqchip, | |
6f79309a | 487 | unsigned int parent_irq); |
d245b3f9 | 488 | |
739e6f59 LW |
489 | int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip, |
490 | struct irq_chip *irqchip, | |
491 | unsigned int first_irq, | |
492 | irq_flow_handler_t handler, | |
493 | unsigned int type, | |
60ed54ca | 494 | bool threaded, |
39c3fd58 AL |
495 | struct lock_class_key *lock_key, |
496 | struct lock_class_key *request_key); | |
739e6f59 | 497 | |
64ff2c8e SB |
498 | bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, |
499 | unsigned int offset); | |
500 | ||
739e6f59 LW |
501 | #ifdef CONFIG_LOCKDEP |
502 | ||
503 | /* | |
504 | * Lockdep requires that each irqchip instance be created with a | |
505 | * unique key so as to avoid unnecessary warnings. This upfront | |
506 | * boilerplate static inlines provides such a key for each | |
507 | * unique instance. | |
508 | */ | |
509 | static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, | |
510 | struct irq_chip *irqchip, | |
511 | unsigned int first_irq, | |
512 | irq_flow_handler_t handler, | |
513 | unsigned int type) | |
514 | { | |
39c3fd58 AL |
515 | static struct lock_class_key lock_key; |
516 | static struct lock_class_key request_key; | |
739e6f59 LW |
517 | |
518 | return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, | |
39c3fd58 AL |
519 | handler, type, false, |
520 | &lock_key, &request_key); | |
739e6f59 LW |
521 | } |
522 | ||
523 | static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, | |
a0a8bcf4 GS |
524 | struct irq_chip *irqchip, |
525 | unsigned int first_irq, | |
526 | irq_flow_handler_t handler, | |
739e6f59 LW |
527 | unsigned int type) |
528 | { | |
529 | ||
39c3fd58 AL |
530 | static struct lock_class_key lock_key; |
531 | static struct lock_class_key request_key; | |
739e6f59 LW |
532 | |
533 | return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, | |
39c3fd58 AL |
534 | handler, type, true, |
535 | &lock_key, &request_key); | |
739e6f59 LW |
536 | } |
537 | #else | |
538 | static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, | |
539 | struct irq_chip *irqchip, | |
540 | unsigned int first_irq, | |
541 | irq_flow_handler_t handler, | |
542 | unsigned int type) | |
543 | { | |
544 | return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, | |
39c3fd58 | 545 | handler, type, false, NULL, NULL); |
739e6f59 | 546 | } |
a0a8bcf4 | 547 | |
d245b3f9 LW |
548 | static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, |
549 | struct irq_chip *irqchip, | |
550 | unsigned int first_irq, | |
551 | irq_flow_handler_t handler, | |
552 | unsigned int type) | |
553 | { | |
739e6f59 | 554 | return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, |
39c3fd58 | 555 | handler, type, true, NULL, NULL); |
d245b3f9 | 556 | } |
739e6f59 | 557 | #endif /* CONFIG_LOCKDEP */ |
14250520 | 558 | |
7d75a871 | 559 | #endif /* CONFIG_GPIOLIB_IRQCHIP */ |
14250520 | 560 | |
c771c2f4 JG |
561 | int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset); |
562 | void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset); | |
2956b5d9 MW |
563 | int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset, |
564 | unsigned long config); | |
c771c2f4 | 565 | |
964cb341 LW |
566 | #ifdef CONFIG_PINCTRL |
567 | ||
568 | /** | |
569 | * struct gpio_pin_range - pin range controlled by a gpio chip | |
950d55f5 | 570 | * @node: list for maintaining set of pin ranges, used internally |
964cb341 LW |
571 | * @pctldev: pinctrl device which handles corresponding pins |
572 | * @range: actual range of pins controlled by a gpio controller | |
573 | */ | |
964cb341 LW |
574 | struct gpio_pin_range { |
575 | struct list_head node; | |
576 | struct pinctrl_dev *pctldev; | |
577 | struct pinctrl_gpio_range range; | |
578 | }; | |
579 | ||
580 | int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, | |
581 | unsigned int gpio_offset, unsigned int pin_offset, | |
582 | unsigned int npins); | |
583 | int gpiochip_add_pingroup_range(struct gpio_chip *chip, | |
584 | struct pinctrl_dev *pctldev, | |
585 | unsigned int gpio_offset, const char *pin_group); | |
586 | void gpiochip_remove_pin_ranges(struct gpio_chip *chip); | |
587 | ||
588 | #else | |
589 | ||
590 | static inline int | |
591 | gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, | |
592 | unsigned int gpio_offset, unsigned int pin_offset, | |
593 | unsigned int npins) | |
594 | { | |
595 | return 0; | |
596 | } | |
597 | static inline int | |
598 | gpiochip_add_pingroup_range(struct gpio_chip *chip, | |
599 | struct pinctrl_dev *pctldev, | |
600 | unsigned int gpio_offset, const char *pin_group) | |
601 | { | |
602 | return 0; | |
603 | } | |
604 | ||
605 | static inline void | |
606 | gpiochip_remove_pin_ranges(struct gpio_chip *chip) | |
607 | { | |
608 | } | |
609 | ||
610 | #endif /* CONFIG_PINCTRL */ | |
611 | ||
abdc08a3 | 612 | struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum, |
21abf103 LW |
613 | const char *label, |
614 | enum gpiod_flags flags); | |
f7d4ad98 GR |
615 | void gpiochip_free_own_desc(struct gpio_desc *desc); |
616 | ||
bb1e88cc AC |
617 | #else /* CONFIG_GPIOLIB */ |
618 | ||
619 | static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) | |
620 | { | |
621 | /* GPIO can never have been requested */ | |
622 | WARN_ON(1); | |
623 | return ERR_PTR(-ENODEV); | |
624 | } | |
625 | ||
626 | #endif /* CONFIG_GPIOLIB */ | |
627 | ||
79a9becd | 628 | #endif |