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1da177e4 LT |
1 | #ifndef LINUX_HARDIRQ_H |
2 | #define LINUX_HARDIRQ_H | |
3 | ||
67bc4eb0 | 4 | #include <linux/preempt.h> |
405f5571 | 5 | #ifdef CONFIG_PREEMPT |
1da177e4 | 6 | #include <linux/smp_lock.h> |
405f5571 | 7 | #endif |
fbb9ce95 | 8 | #include <linux/lockdep.h> |
6a60dd12 | 9 | #include <linux/ftrace_irq.h> |
1da177e4 LT |
10 | #include <asm/hardirq.h> |
11 | #include <asm/system.h> | |
12 | ||
13 | /* | |
14 | * We put the hardirq and softirq counter into the preemption | |
15 | * counter. The bitmask has the following meaning: | |
16 | * | |
17 | * - bits 0-7 are the preemption count (max preemption depth: 256) | |
18 | * - bits 8-15 are the softirq count (max # of softirqs: 256) | |
19 | * | |
5a5fb7db SR |
20 | * The hardirq count can in theory reach the same as NR_IRQS. |
21 | * In reality, the number of nested IRQS is limited to the stack | |
22 | * size as well. For archs with over 1000 IRQS it is not practical | |
23 | * to expect that they will all nest. We give a max of 10 bits for | |
24 | * hardirq nesting. An arch may choose to give less than 10 bits. | |
25 | * m68k expects it to be 8. | |
1da177e4 | 26 | * |
5a5fb7db SR |
27 | * - bits 16-25 are the hardirq count (max # of nested hardirqs: 1024) |
28 | * - bit 26 is the NMI_MASK | |
29 | * - bit 28 is the PREEMPT_ACTIVE flag | |
1da177e4 LT |
30 | * |
31 | * PREEMPT_MASK: 0x000000ff | |
32 | * SOFTIRQ_MASK: 0x0000ff00 | |
5a5fb7db SR |
33 | * HARDIRQ_MASK: 0x03ff0000 |
34 | * NMI_MASK: 0x04000000 | |
1da177e4 LT |
35 | */ |
36 | #define PREEMPT_BITS 8 | |
37 | #define SOFTIRQ_BITS 8 | |
5a5fb7db | 38 | #define NMI_BITS 1 |
1da177e4 | 39 | |
5a5fb7db | 40 | #define MAX_HARDIRQ_BITS 10 |
23d0b8b0 | 41 | |
5a5fb7db SR |
42 | #ifndef HARDIRQ_BITS |
43 | # define HARDIRQ_BITS MAX_HARDIRQ_BITS | |
23d0b8b0 EB |
44 | #endif |
45 | ||
5a5fb7db SR |
46 | #if HARDIRQ_BITS > MAX_HARDIRQ_BITS |
47 | #error HARDIRQ_BITS too high! | |
1da177e4 LT |
48 | #endif |
49 | ||
50 | #define PREEMPT_SHIFT 0 | |
51 | #define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) | |
52 | #define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) | |
5a5fb7db | 53 | #define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS) |
1da177e4 LT |
54 | |
55 | #define __IRQ_MASK(x) ((1UL << (x))-1) | |
56 | ||
57 | #define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT) | |
1da177e4 | 58 | #define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) |
8f28e8fa | 59 | #define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT) |
5a5fb7db | 60 | #define NMI_MASK (__IRQ_MASK(NMI_BITS) << NMI_SHIFT) |
1da177e4 LT |
61 | |
62 | #define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT) | |
63 | #define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT) | |
64 | #define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT) | |
5a5fb7db | 65 | #define NMI_OFFSET (1UL << NMI_SHIFT) |
1da177e4 | 66 | |
75e1056f VP |
67 | #define SOFTIRQ_DISABLE_OFFSET (2 * SOFTIRQ_OFFSET) |
68 | ||
8e5b59a2 AB |
69 | #ifndef PREEMPT_ACTIVE |
70 | #define PREEMPT_ACTIVE_BITS 1 | |
71 | #define PREEMPT_ACTIVE_SHIFT (NMI_SHIFT + NMI_BITS) | |
72 | #define PREEMPT_ACTIVE (__IRQ_MASK(PREEMPT_ACTIVE_BITS) << PREEMPT_ACTIVE_SHIFT) | |
73 | #endif | |
74 | ||
5a5fb7db | 75 | #if PREEMPT_ACTIVE < (1 << (NMI_SHIFT + NMI_BITS)) |
8f28e8fa PBG |
76 | #error PREEMPT_ACTIVE is too low! |
77 | #endif | |
78 | ||
1da177e4 LT |
79 | #define hardirq_count() (preempt_count() & HARDIRQ_MASK) |
80 | #define softirq_count() (preempt_count() & SOFTIRQ_MASK) | |
5a5fb7db SR |
81 | #define irq_count() (preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK \ |
82 | | NMI_MASK)) | |
1da177e4 LT |
83 | |
84 | /* | |
85 | * Are we doing bottom half or hardware interrupt processing? | |
86 | * Are we in a softirq context? Interrupt context? | |
75e1056f VP |
87 | * in_softirq - Are we currently processing softirq or have bh disabled? |
88 | * in_serving_softirq - Are we currently processing softirq? | |
1da177e4 LT |
89 | */ |
90 | #define in_irq() (hardirq_count()) | |
91 | #define in_softirq() (softirq_count()) | |
92 | #define in_interrupt() (irq_count()) | |
75e1056f | 93 | #define in_serving_softirq() (softirq_count() & SOFTIRQ_OFFSET) |
1da177e4 | 94 | |
375b38b4 SR |
95 | /* |
96 | * Are we in NMI context? | |
97 | */ | |
5a5fb7db | 98 | #define in_nmi() (preempt_count() & NMI_MASK) |
375b38b4 | 99 | |
8e3e076c LT |
100 | #if defined(CONFIG_PREEMPT) |
101 | # define PREEMPT_INATOMIC_BASE kernel_locked() | |
102 | # define PREEMPT_CHECK_OFFSET 1 | |
103 | #else | |
104 | # define PREEMPT_INATOMIC_BASE 0 | |
105 | # define PREEMPT_CHECK_OFFSET 0 | |
106 | #endif | |
107 | ||
8c703d35 JC |
108 | /* |
109 | * Are we running in atomic context? WARNING: this macro cannot | |
110 | * always detect atomic context; in particular, it cannot know about | |
111 | * held spinlocks in non-preemptible kernels. Thus it should not be | |
112 | * used in the general case to determine whether sleeping is possible. | |
113 | * Do not use in_atomic() in driver code. | |
114 | */ | |
8e3e076c | 115 | #define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_INATOMIC_BASE) |
4da1ce6d IM |
116 | |
117 | /* | |
118 | * Check whether we were atomic before we did preempt_disable(): | |
8e3e076c | 119 | * (used by the scheduler, *after* releasing the kernel lock) |
4da1ce6d IM |
120 | */ |
121 | #define in_atomic_preempt_off() \ | |
122 | ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_CHECK_OFFSET) | |
123 | ||
1da177e4 LT |
124 | #ifdef CONFIG_PREEMPT |
125 | # define preemptible() (preempt_count() == 0 && !irqs_disabled()) | |
126 | # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1) | |
127 | #else | |
128 | # define preemptible() 0 | |
129 | # define IRQ_EXIT_OFFSET HARDIRQ_OFFSET | |
130 | #endif | |
131 | ||
3aa551c9 | 132 | #if defined(CONFIG_SMP) || defined(CONFIG_GENERIC_HARDIRQS) |
1da177e4 LT |
133 | extern void synchronize_irq(unsigned int irq); |
134 | #else | |
135 | # define synchronize_irq(irq) barrier() | |
136 | #endif | |
137 | ||
f037360f AV |
138 | struct task_struct; |
139 | ||
1da177e4 | 140 | #ifndef CONFIG_VIRT_CPU_ACCOUNTING |
1da177e4 LT |
141 | static inline void account_system_vtime(struct task_struct *tsk) |
142 | { | |
143 | } | |
144 | #endif | |
145 | ||
b560d8ad | 146 | #if defined(CONFIG_NO_HZ) |
9b1d82fa PM |
147 | #if defined(CONFIG_TINY_RCU) |
148 | extern void rcu_enter_nohz(void); | |
149 | extern void rcu_exit_nohz(void); | |
150 | ||
151 | static inline void rcu_irq_enter(void) | |
152 | { | |
153 | rcu_exit_nohz(); | |
154 | } | |
155 | ||
156 | static inline void rcu_irq_exit(void) | |
157 | { | |
158 | rcu_enter_nohz(); | |
159 | } | |
160 | ||
161 | static inline void rcu_nmi_enter(void) | |
162 | { | |
163 | } | |
164 | ||
165 | static inline void rcu_nmi_exit(void) | |
166 | { | |
167 | } | |
168 | ||
169 | #else | |
2232c2d8 SR |
170 | extern void rcu_irq_enter(void); |
171 | extern void rcu_irq_exit(void); | |
64db4cff PM |
172 | extern void rcu_nmi_enter(void); |
173 | extern void rcu_nmi_exit(void); | |
9b1d82fa | 174 | #endif |
2232c2d8 SR |
175 | #else |
176 | # define rcu_irq_enter() do { } while (0) | |
177 | # define rcu_irq_exit() do { } while (0) | |
64db4cff PM |
178 | # define rcu_nmi_enter() do { } while (0) |
179 | # define rcu_nmi_exit() do { } while (0) | |
b560d8ad | 180 | #endif /* #if defined(CONFIG_NO_HZ) */ |
2232c2d8 | 181 | |
de30a2b3 IM |
182 | /* |
183 | * It is safe to do non-atomic ops on ->hardirq_context, | |
184 | * because NMI handlers may not preempt and the ops are | |
185 | * always balanced, so the interrupted value of ->hardirq_context | |
186 | * will always be restored. | |
187 | */ | |
79bf2bb3 TG |
188 | #define __irq_enter() \ |
189 | do { \ | |
190 | account_system_vtime(current); \ | |
191 | add_preempt_count(HARDIRQ_OFFSET); \ | |
192 | trace_hardirq_enter(); \ | |
193 | } while (0) | |
194 | ||
195 | /* | |
196 | * Enter irq context (on NO_HZ, update jiffies): | |
197 | */ | |
dde4b2b5 | 198 | extern void irq_enter(void); |
de30a2b3 IM |
199 | |
200 | /* | |
201 | * Exit irq context without processing softirqs: | |
202 | */ | |
203 | #define __irq_exit() \ | |
204 | do { \ | |
205 | trace_hardirq_exit(); \ | |
206 | account_system_vtime(current); \ | |
207 | sub_preempt_count(HARDIRQ_OFFSET); \ | |
1da177e4 LT |
208 | } while (0) |
209 | ||
de30a2b3 IM |
210 | /* |
211 | * Exit irq context and process softirqs if needed: | |
212 | */ | |
1da177e4 LT |
213 | extern void irq_exit(void); |
214 | ||
2a7b8df0 SR |
215 | #define nmi_enter() \ |
216 | do { \ | |
217 | ftrace_nmi_enter(); \ | |
218 | BUG_ON(in_nmi()); \ | |
219 | add_preempt_count(NMI_OFFSET + HARDIRQ_OFFSET); \ | |
220 | lockdep_off(); \ | |
221 | rcu_nmi_enter(); \ | |
222 | trace_hardirq_enter(); \ | |
17666f02 | 223 | } while (0) |
5f34fe1c | 224 | |
2a7b8df0 SR |
225 | #define nmi_exit() \ |
226 | do { \ | |
227 | trace_hardirq_exit(); \ | |
228 | rcu_nmi_exit(); \ | |
229 | lockdep_on(); \ | |
230 | BUG_ON(!in_nmi()); \ | |
231 | sub_preempt_count(NMI_OFFSET + HARDIRQ_OFFSET); \ | |
232 | ftrace_nmi_exit(); \ | |
17666f02 | 233 | } while (0) |
de30a2b3 | 234 | |
1da177e4 | 235 | #endif /* LINUX_HARDIRQ_H */ |