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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT
2#ifndef _IDE_H
3#define _IDE_H
4/*
5 * linux/include/linux/ide.h
6 *
7 * Copyright (C) 1994-2002 Linus Torvalds & authors
8 */
9
1da177e4
LT
10#include <linux/init.h>
11#include <linux/ioport.h>
3ceca727 12#include <linux/ata.h>
60033520 13#include <linux/blk-mq.h>
1da177e4
LT
14#include <linux/proc_fs.h>
15#include <linux/interrupt.h>
16#include <linux/bitops.h>
17#include <linux/bio.h>
1da177e4 18#include <linux/pci.h>
f36d4024 19#include <linux/completion.h>
feb22b7f 20#include <linux/pm.h>
245e3718 21#include <linux/mutex.h>
a1df5169
BP
22/* for request_sense */
23#include <linux/cdrom.h>
82ed4db4 24#include <scsi/scsi_cmnd.h>
8b48463f
LZ
25#include <asm/byteorder.h>
26#include <asm/io.h>
a1df5169 27
1da177e4
LT
28/*
29 * Probably not wise to fiddle with these
30 */
a687a533 31#define SUPPORT_VLB_SYNC 1
b40d1b88 32#define IDE_DEFAULT_MAX_FAILURES 1
1da177e4
LT
33#define ERROR_MAX 8 /* Max read/write errors per sector */
34#define ERROR_RESET 3 /* Reset controller every 4th retry */
35#define ERROR_RECAL 1 /* Recalibrate every 2nd retry */
36
313162d0
PG
37struct device;
38
2f5a8e80
CH
39/* values for ide_request.type */
40enum ata_priv_type {
41 ATA_PRIV_MISC,
42 ATA_PRIV_TASKFILE,
43 ATA_PRIV_PC,
44 ATA_PRIV_SENSE, /* sense request */
45 ATA_PRIV_PM_SUSPEND, /* suspend request */
46 ATA_PRIV_PM_RESUME, /* resume request */
b42171ef
CH
47};
48
82ed4db4
CH
49struct ide_request {
50 struct scsi_request sreq;
51 u8 sense[SCSI_SENSE_BUFFERSIZE];
2f5a8e80 52 u8 type;
22ce0a7c 53 void *special;
82ed4db4
CH
54};
55
2f5a8e80
CH
56static inline struct ide_request *ide_req(struct request *rq)
57{
58 return blk_mq_rq_to_pdu(rq);
59}
60
61static inline bool ata_misc_request(struct request *rq)
62{
aebf526b 63 return blk_rq_is_private(rq) && ide_req(rq)->type == ATA_PRIV_MISC;
2f5a8e80
CH
64}
65
66static inline bool ata_taskfile_request(struct request *rq)
67{
aebf526b 68 return blk_rq_is_private(rq) && ide_req(rq)->type == ATA_PRIV_TASKFILE;
2f5a8e80
CH
69}
70
71static inline bool ata_pc_request(struct request *rq)
72{
aebf526b 73 return blk_rq_is_private(rq) && ide_req(rq)->type == ATA_PRIV_PC;
2f5a8e80
CH
74}
75
76static inline bool ata_sense_request(struct request *rq)
77{
aebf526b 78 return blk_rq_is_private(rq) && ide_req(rq)->type == ATA_PRIV_SENSE;
2f5a8e80
CH
79}
80
81static inline bool ata_pm_request(struct request *rq)
82{
aebf526b 83 return blk_rq_is_private(rq) &&
2f5a8e80
CH
84 (ide_req(rq)->type == ATA_PRIV_PM_SUSPEND ||
85 ide_req(rq)->type == ATA_PRIV_PM_RESUME);
86}
87
17d5363b 88/* Error codes returned in result to the higher part of the driver. */
c152cc1a
BZ
89enum {
90 IDE_DRV_ERROR_GENERAL = 101,
91 IDE_DRV_ERROR_FILEMARK = 102,
92 IDE_DRV_ERROR_EOD = 103,
93};
94
1da177e4
LT
95/*
96 * Definitions for accessing IDE controller registers
97 */
98#define IDE_NR_PORTS (10)
99
4c3032d8
BZ
100struct ide_io_ports {
101 unsigned long data_addr;
102
103 union {
104 unsigned long error_addr; /* read: error */
105 unsigned long feature_addr; /* write: feature */
106 };
107
108 unsigned long nsect_addr;
109 unsigned long lbal_addr;
110 unsigned long lbam_addr;
111 unsigned long lbah_addr;
112
113 unsigned long device_addr;
114
115 union {
116 unsigned long status_addr; /*  read: status  */
117 unsigned long command_addr; /* write: command */
118 };
119
120 unsigned long ctl_addr;
121
122 unsigned long irq_addr;
123};
1da177e4
LT
124
125#define OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
1da177e4 126
3a7d2484
BZ
127#define BAD_R_STAT (ATA_BUSY | ATA_ERR)
128#define BAD_W_STAT (BAD_R_STAT | ATA_DF)
129#define BAD_STAT (BAD_R_STAT | ATA_DRQ)
130#define DRIVE_READY (ATA_DRDY | ATA_DSC)
131
132#define BAD_CRC (ATA_ABORTED | ATA_ICRC)
1da177e4
LT
133
134#define SATA_NR_PORTS (3) /* 16 possible ?? */
135
136#define SATA_STATUS_OFFSET (0)
1da177e4 137#define SATA_ERROR_OFFSET (1)
1da177e4 138#define SATA_CONTROL_OFFSET (2)
1da177e4 139
1da177e4
LT
140/*
141 * Our Physical Region Descriptor (PRD) table should be large enough
142 * to handle the biggest I/O request we are likely to see. Since requests
143 * can have no more than 256 sectors, and since the typical blocksize is
144 * two or more sectors, we could get by with a limit of 128 entries here for
145 * the usual worst case. Most requests seem to include some contiguous blocks,
146 * further reducing the number of table entries required.
147 *
148 * The driver reverts to PIO mode for individual requests that exceed
149 * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
150 * 100% of all crazy scenarios here is not necessary.
151 *
152 * As it turns out though, we must allocate a full 4KB page for this,
153 * so the two PRD tables (ide0 & ide1) will each get half of that,
154 * allowing each to have about 256 entries (8 bytes each) from this.
155 */
156#define PRD_BYTES 8
157#define PRD_ENTRIES 256
158
159/*
160 * Some more useful definitions
161 */
162#define PARTN_BITS 6 /* number of minor dev bits for partitions */
163#define MAX_DRIVES 2 /* per interface; 2 assumed by lots of code */
151a6701 164
1da177e4
LT
165/*
166 * Timeouts for various operations:
167 */
d6e2955a 168enum {
602da297
DM
169 /* spec allows up to 20ms, but CF cards and SSD drives need more */
170 WAIT_DRQ = 1 * HZ, /* 1s */
d6e2955a
BZ
171 /* some laptops are very slow */
172 WAIT_READY = 5 * HZ, /* 5s */
173 /* should be less than 3ms (?), if all ATAPI CD is closed at boot */
174 WAIT_PIDENTIFY = 10 * HZ, /* 10s */
175 /* worst case when spinning up */
176 WAIT_WORSTCASE = 30 * HZ, /* 30s */
177 /* maximum wait for an IRQ to happen */
178 WAIT_CMD = 10 * HZ, /* 10s */
179 /* Some drives require a longer IRQ timeout. */
180 WAIT_FLOPPY_CMD = 50 * HZ, /* 50s */
181 /*
182 * Some drives (for example, Seagate STT3401A Travan) require a very
183 * long timeout, because they don't return an interrupt or clear their
184 * BSY bit until after the command completes (even retension commands).
185 */
186 WAIT_TAPE_CMD = 900 * HZ, /* 900s */
187 /* minimum sleep time */
188 WAIT_MIN_SLEEP = HZ / 50, /* 20ms */
189};
1da177e4 190
79e36a9f
EO
191/*
192 * Op codes for special requests to be handled by ide_special_rq().
193 * Values should be in the range of 0x20 to 0x3f.
194 */
195#define REQ_DRIVE_RESET 0x20
92f1f8fd 196#define REQ_DEVSET_EXEC 0x21
4abdc6ee
EO
197#define REQ_PARK_HEADS 0x22
198#define REQ_UNPARK_HEADS 0x23
79e36a9f 199
1da177e4
LT
200/*
201 * hwif_chipset_t is used to keep track of the specific hardware
202 * chipset used by each IDE interface, if known.
203 */
528a572d 204enum { ide_unknown, ide_generic, ide_pci,
1da177e4
LT
205 ide_cmd640, ide_dtc2278, ide_ali14xx,
206 ide_qd65xx, ide_umc8672, ide_ht6560b,
b7876a6f 207 ide_4drives, ide_pmac, ide_acorn,
9a0e77f2 208 ide_au1xxx, ide_palm3710
528a572d
BZ
209};
210
211typedef u8 hwif_chipset_t;
1da177e4
LT
212
213/*
214 * Structure to hold all information about the location of this port
215 */
9f36d314 216struct ide_hw {
4c3032d8
BZ
217 union {
218 struct ide_io_ports io_ports;
219 unsigned long io_ports_array[IDE_NR_PORTS];
220 };
221
1da177e4 222 int irq; /* our irq number */
c56c5648 223 struct device *dev, *parent;
d6276b5f 224 unsigned long config;
9f36d314 225};
1da177e4 226
9f36d314 227static inline void ide_std_init_ports(struct ide_hw *hw,
1da177e4
LT
228 unsigned long io_addr,
229 unsigned long ctl_addr)
230{
231 unsigned int i;
232
4c3032d8
BZ
233 for (i = 0; i <= 7; i++)
234 hw->io_ports_array[i] = io_addr++;
1da177e4 235
4c3032d8 236 hw->io_ports.ctl_addr = ctl_addr;
1da177e4
LT
237}
238
c5bfc375 239#define MAX_HWIFS 10
83ae20c8 240
1da177e4
LT
241/*
242 * Now for the data we need to maintain per-drive: ide_drive_t
243 */
244
245#define ide_scsi 0x21
246#define ide_disk 0x20
247#define ide_optical 0x7
248#define ide_cdrom 0x5
249#define ide_tape 0x1
250#define ide_floppy 0x0
251
252/*
253 * Special Driver Flags
1da177e4 254 */
ca1b96e0 255enum {
13990cf8
AS
256 IDE_SFLAG_SET_GEOMETRY = BIT(0),
257 IDE_SFLAG_RECALIBRATE = BIT(1),
258 IDE_SFLAG_SET_MULTMODE = BIT(2),
ca1b96e0 259};
1da177e4 260
1da177e4
LT
261/*
262 * Status returned from various ide_ functions
263 */
264typedef enum {
265 ide_stopped, /* no drive operation was started */
266 ide_started, /* a drive operation was started, handler was set */
267} ide_startstop_t;
268
60f85019 269enum {
13990cf8 270 IDE_VALID_ERROR = BIT(1),
60f85019 271 IDE_VALID_FEATURE = IDE_VALID_ERROR,
13990cf8
AS
272 IDE_VALID_NSECT = BIT(2),
273 IDE_VALID_LBAL = BIT(3),
274 IDE_VALID_LBAM = BIT(4),
275 IDE_VALID_LBAH = BIT(5),
276 IDE_VALID_DEVICE = BIT(6),
60f85019
SS
277 IDE_VALID_LBA = IDE_VALID_LBAL |
278 IDE_VALID_LBAM |
279 IDE_VALID_LBAH,
280 IDE_VALID_OUT_TF = IDE_VALID_FEATURE |
281 IDE_VALID_NSECT |
282 IDE_VALID_LBA,
283 IDE_VALID_IN_TF = IDE_VALID_NSECT |
284 IDE_VALID_LBA,
285 IDE_VALID_OUT_HOB = IDE_VALID_OUT_TF,
286 IDE_VALID_IN_HOB = IDE_VALID_ERROR |
287 IDE_VALID_NSECT |
288 IDE_VALID_LBA,
289};
290
d6ff9f64 291enum {
13990cf8
AS
292 IDE_TFLAG_LBA48 = BIT(0),
293 IDE_TFLAG_WRITE = BIT(1),
294 IDE_TFLAG_CUSTOM_HANDLER = BIT(2),
295 IDE_TFLAG_DMA_PIO_FALLBACK = BIT(3),
d6ff9f64 296 /* force 16-bit I/O operations */
13990cf8 297 IDE_TFLAG_IO_16BIT = BIT(4),
22aa4b32 298 /* struct ide_cmd was allocated using kmalloc() */
13990cf8
AS
299 IDE_TFLAG_DYN = BIT(5),
300 IDE_TFLAG_FS = BIT(6),
301 IDE_TFLAG_MULTI_PIO = BIT(7),
302 IDE_TFLAG_SET_XFER = BIT(8),
19710d25
BZ
303};
304
305enum {
13990cf8
AS
306 IDE_FTFLAG_FLAGGED = BIT(0),
307 IDE_FTFLAG_SET_IN_FLAGS = BIT(1),
308 IDE_FTFLAG_OUT_DATA = BIT(2),
309 IDE_FTFLAG_IN_DATA = BIT(3),
d6ff9f64
BZ
310};
311
312struct ide_taskfile {
745483f1
SS
313 u8 data; /* 0: data byte (for TASKFILE ioctl) */
314 union { /* 1: */
315 u8 error; /* read: error */
316 u8 feature; /* write: feature */
d6ff9f64 317 };
745483f1
SS
318 u8 nsect; /* 2: number of sectors */
319 u8 lbal; /* 3: LBA low */
320 u8 lbam; /* 4: LBA mid */
321 u8 lbah; /* 5: LBA high */
322 u8 device; /* 6: device select */
323 union { /* 7: */
324 u8 status; /* read: status */
d6ff9f64
BZ
325 u8 command; /* write: command */
326 };
327};
328
22aa4b32 329struct ide_cmd {
745483f1
SS
330 struct ide_taskfile tf;
331 struct ide_taskfile hob;
60f85019
SS
332 struct {
333 struct {
334 u8 tf;
335 u8 hob;
336 } out, in;
337 } valid;
338
665d66e8 339 u16 tf_flags;
19710d25 340 u8 ftf_flags; /* for TASKFILE ioctl */
0dfb991c 341 int protocol;
b6308ee0
BZ
342
343 int sg_nents; /* number of sg entries */
344 int orig_sg_nents;
345 int sg_dma_direction; /* DMA transfer direction */
346
bf717c0a 347 unsigned int nbytes;
b6308ee0 348 unsigned int nleft;
a08915ba
BZ
349 unsigned int last_xfer_len;
350
b6308ee0
BZ
351 struct scatterlist *cursg;
352 unsigned int cursg_ofs;
353
d6ff9f64 354 struct request *rq; /* copy of request */
22aa4b32 355};
d6ff9f64 356
67c56364
BZ
357/* ATAPI packet command flags */
358enum {
359 /* set when an error is considered normal - no retry (ide-tape) */
13990cf8
AS
360 PC_FLAG_ABORT = BIT(0),
361 PC_FLAG_SUPPRESS_ERROR = BIT(1),
362 PC_FLAG_WAIT_FOR_DSC = BIT(2),
363 PC_FLAG_DMA_OK = BIT(3),
364 PC_FLAG_DMA_IN_PROGRESS = BIT(4),
365 PC_FLAG_DMA_ERROR = BIT(5),
366 PC_FLAG_WRITING = BIT(6),
67c56364
BZ
367};
368
4cad085e 369#define ATAPI_WAIT_PC (60 * HZ)
67c56364
BZ
370
371struct ide_atapi_pc {
372 /* actual packet bytes */
373 u8 c[12];
374 /* incremented on each retry */
375 int retries;
376 int error;
377
378 /* bytes to transfer */
379 int req_xfer;
67c56364
BZ
380
381 /* the corresponding request */
382 struct request *rq;
383
384 unsigned long flags;
385
386 /*
387 * those are more or less driver-specific and some of them are subject
388 * to change/removal later.
389 */
67c56364
BZ
390 unsigned long timeout;
391};
392
8185d5aa 393struct ide_devset;
7f3c868b 394struct ide_driver;
1da177e4 395
e3a59b4d
HR
396#ifdef CONFIG_BLK_DEV_IDEACPI
397struct ide_acpi_drive_link;
398struct ide_acpi_hwif_link;
399#endif
400
806f80a6
BZ
401struct ide_drive_s;
402
403struct ide_disk_ops {
404 int (*check)(struct ide_drive_s *, const char *);
405 int (*get_capacity)(struct ide_drive_s *);
c3e33e04 406 void (*unlock_native_capacity)(struct ide_drive_s *);
806f80a6
BZ
407 void (*setup)(struct ide_drive_s *);
408 void (*flush)(struct ide_drive_s *);
409 int (*init_media)(struct ide_drive_s *, struct gendisk *);
410 int (*set_doorlock)(struct ide_drive_s *, struct gendisk *,
411 int);
412 ide_startstop_t (*do_request)(struct ide_drive_s *, struct request *,
413 sector_t);
badf8082
AV
414 int (*ioctl)(struct ide_drive_s *, struct block_device *,
415 fmode_t, unsigned int, unsigned long);
c103d6ee
AB
416 int (*compat_ioctl)(struct ide_drive_s *, struct block_device *,
417 fmode_t, unsigned int, unsigned long);
806f80a6
BZ
418};
419
3b8ac539
BP
420/* ATAPI device flags */
421enum {
13990cf8 422 IDE_AFLAG_DRQ_INTERRUPT = BIT(0),
0578042d
BZ
423
424 /* ide-cd */
3b8ac539 425 /* Drive cannot eject the disc. */
13990cf8 426 IDE_AFLAG_NO_EJECT = BIT(1),
3b8ac539 427 /* Drive is a pre ATAPI 1.2 drive. */
13990cf8 428 IDE_AFLAG_PRE_ATAPI12 = BIT(2),
3b8ac539 429 /* TOC addresses are in BCD. */
13990cf8 430 IDE_AFLAG_TOCADDR_AS_BCD = BIT(3),
3b8ac539 431 /* TOC track numbers are in BCD. */
13990cf8 432 IDE_AFLAG_TOCTRACKS_AS_BCD = BIT(4),
3b8ac539 433 /* Saved TOC information is current. */
13990cf8 434 IDE_AFLAG_TOC_VALID = BIT(6),
3b8ac539 435 /* We think that the drive door is locked. */
13990cf8 436 IDE_AFLAG_DOOR_LOCKED = BIT(7),
3b8ac539 437 /* SET_CD_SPEED command is unsupported. */
13990cf8
AS
438 IDE_AFLAG_NO_SPEED_SELECT = BIT(8),
439 IDE_AFLAG_VERTOS_300_SSD = BIT(9),
440 IDE_AFLAG_VERTOS_600_ESD = BIT(10),
441 IDE_AFLAG_SANYO_3CD = BIT(11),
442 IDE_AFLAG_FULL_CAPS_PAGE = BIT(12),
443 IDE_AFLAG_PLAY_AUDIO_OK = BIT(13),
444 IDE_AFLAG_LE_SPEED_FIELDS = BIT(14),
3b8ac539
BP
445
446 /* ide-floppy */
3b8ac539 447 /* Avoid commands not supported in Clik drive */
13990cf8 448 IDE_AFLAG_CLIK_DRIVE = BIT(15),
3b8ac539 449 /* Requires BH algorithm for packets */
13990cf8 450 IDE_AFLAG_ZIP_DRIVE = BIT(16),
49cac39e 451 /* Supports format progress report */
13990cf8 452 IDE_AFLAG_SRFP = BIT(17),
3b8ac539
BP
453
454 /* ide-tape */
13990cf8 455 IDE_AFLAG_IGNORE_DSC = BIT(18),
3b8ac539 456 /* 0 When the tape position is unknown */
13990cf8 457 IDE_AFLAG_ADDRESS_VALID = BIT(19),
3b8ac539 458 /* Device already opened */
13990cf8 459 IDE_AFLAG_BUSY = BIT(20),
3b8ac539 460 /* Attempt to auto-detect the current user block size */
13990cf8 461 IDE_AFLAG_DETECT_BS = BIT(21),
3b8ac539 462 /* Currently on a filemark */
13990cf8 463 IDE_AFLAG_FILEMARK = BIT(22),
3b8ac539 464 /* 0 = no tape is loaded, so we don't rewind after ejecting */
13990cf8 465 IDE_AFLAG_MEDIUM_PRESENT = BIT(23),
f20f2586 466
13990cf8 467 IDE_AFLAG_NO_AUTOCLOSE = BIT(24),
3b8ac539
BP
468};
469
97100fc8
BZ
470/* device flags */
471enum {
472 /* restore settings after device reset */
13990cf8 473 IDE_DFLAG_KEEP_SETTINGS = BIT(0),
97100fc8 474 /* device is using DMA for read/write */
13990cf8 475 IDE_DFLAG_USING_DMA = BIT(1),
97100fc8 476 /* okay to unmask other IRQs */
13990cf8 477 IDE_DFLAG_UNMASK = BIT(2),
97100fc8 478 /* don't attempt flushes */
13990cf8 479 IDE_DFLAG_NOFLUSH = BIT(3),
97100fc8 480 /* DSC overlap */
13990cf8 481 IDE_DFLAG_DSC_OVERLAP = BIT(4),
97100fc8 482 /* give potential excess bandwidth */
13990cf8 483 IDE_DFLAG_NICE1 = BIT(5),
97100fc8 484 /* device is physically present */
13990cf8 485 IDE_DFLAG_PRESENT = BIT(6),
075affcb 486 /* disable Host Protected Area */
13990cf8 487 IDE_DFLAG_NOHPA = BIT(7),
97100fc8 488 /* id read from device (synthetic if not set) */
13990cf8
AS
489 IDE_DFLAG_ID_READ = BIT(8),
490 IDE_DFLAG_NOPROBE = BIT(9),
97100fc8 491 /* need to do check_media_change() */
13990cf8 492 IDE_DFLAG_REMOVABLE = BIT(10),
97100fc8 493 /* needed for removable devices */
13990cf8
AS
494 IDE_DFLAG_ATTACH = BIT(11),
495 IDE_DFLAG_FORCED_GEOM = BIT(12),
97100fc8 496 /* disallow setting unmask bit */
13990cf8 497 IDE_DFLAG_NO_UNMASK = BIT(13),
97100fc8 498 /* disallow enabling 32-bit I/O */
13990cf8 499 IDE_DFLAG_NO_IO_32BIT = BIT(14),
97100fc8 500 /* for removable only: door lock/unlock works */
13990cf8 501 IDE_DFLAG_DOORLOCKING = BIT(15),
97100fc8 502 /* disallow DMA */
13990cf8 503 IDE_DFLAG_NODMA = BIT(16),
65155b37 504 /* powermanagement told us not to do anything, so sleep nicely */
13990cf8 505 IDE_DFLAG_BLOCKED = BIT(17),
97100fc8 506 /* sleeping & sleep field valid */
13990cf8
AS
507 IDE_DFLAG_SLEEPING = BIT(18),
508 IDE_DFLAG_POST_RESET = BIT(19),
509 IDE_DFLAG_UDMA33_WARNED = BIT(20),
510 IDE_DFLAG_LBA48 = BIT(21),
97100fc8 511 /* status of write cache */
13990cf8 512 IDE_DFLAG_WCACHE = BIT(22),
97100fc8 513 /* used for ignoring ATA_DF */
13990cf8 514 IDE_DFLAG_NOWERR = BIT(23),
c3922048 515 /* retrying in PIO */
13990cf8
AS
516 IDE_DFLAG_DMA_PIO_RETRY = BIT(24),
517 IDE_DFLAG_LBA = BIT(25),
4abdc6ee 518 /* don't unload heads */
13990cf8 519 IDE_DFLAG_NO_UNLOAD = BIT(26),
4abdc6ee 520 /* heads unloaded, please don't reset port */
13990cf8
AS
521 IDE_DFLAG_PARKED = BIT(27),
522 IDE_DFLAG_MEDIA_CHANGED = BIT(28),
da167876 523 /* write protect */
13990cf8
AS
524 IDE_DFLAG_WP = BIT(29),
525 IDE_DFLAG_FORMAT_IN_PROGRESS = BIT(30),
526 IDE_DFLAG_NIEN_QUIRK = BIT(31),
97100fc8
BZ
527};
528
d7c26ebb 529struct ide_drive_s {
1da177e4
LT
530 char name[4]; /* drive name, such as "hda" */
531 char driver_req[10]; /* requests specific driver */
532
165125e1 533 struct request_queue *queue; /* request queue */
1da177e4 534
535ac5d3 535 bool (*prep_rq)(struct ide_drive_s *, struct request *);
60033520
JA
536
537 struct blk_mq_tag_set tag_set;
538
1da177e4 539 struct request *rq; /* current request */
1da177e4 540 void *driver_data; /* extra driver data */
48fb2688 541 u16 *id; /* identification info */
7662d046 542#ifdef CONFIG_IDE_PROC_FS
1da177e4 543 struct proc_dir_entry *proc; /* /proc/ide/ directory entry */
92f1f8fd 544 const struct ide_proc_devset *settings; /* /proc/ide/ drive settings */
7662d046 545#endif
1da177e4
LT
546 struct hwif_s *hwif; /* actually (ide_hwif_t *) */
547
806f80a6
BZ
548 const struct ide_disk_ops *disk_ops;
549
97100fc8
BZ
550 unsigned long dev_flags;
551
1da177e4 552 unsigned long sleep; /* sleep until this time */
1da177e4
LT
553 unsigned long timeout; /* max time to wait for irq */
554
ca1b96e0 555 u8 special_flags; /* special action flags */
1da177e4 556
7f612f27 557 u8 select; /* basic drive/head select reg value */
1da177e4 558 u8 retry_pio; /* retrying dma capable host in pio */
1da177e4 559 u8 waiting_for_dma; /* dma currently in progress */
0a9b6f88 560 u8 dma; /* atapi dma flag */
1da177e4 561
1da177e4 562 u8 init_speed; /* transfer rate set at boot */
1da177e4 563 u8 current_speed; /* current transfer rate set */
513daadd 564 u8 desired_speed; /* desired transfer rate set */
d2d4e780 565 u8 pio_mode; /* for ->set_pio_mode _only_ */
54a4ec46
SS
566 u8 dma_mode; /* for ->set_dma_mode _only_ */
567 u8 dn; /* now wide spread use */
1da177e4
LT
568 u8 acoustic; /* acoustic management */
569 u8 media; /* disk, cdrom, tape, floppy, ... */
1da177e4
LT
570 u8 ready_stat; /* min status value for drive ready */
571 u8 mult_count; /* current multiple sector setting */
572 u8 mult_req; /* requested multiple sector setting */
1da177e4 573 u8 io_32bit; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
3a7d2484 574 u8 bad_wstat; /* used for ignoring ATA_DF */
1da177e4
LT
575 u8 head; /* "real" number of heads */
576 u8 sect; /* "real" sectors per track */
577 u8 bios_head; /* BIOS/fdisk/LILO number of heads */
578 u8 bios_sect; /* BIOS/fdisk/LILO sectors per track */
579
baf08f0b
BZ
580 /* delay this long before sending packet command */
581 u8 pc_delay;
582
1da177e4
LT
583 unsigned int bios_cyl; /* BIOS/fdisk/LILO number of cyls */
584 unsigned int cyl; /* "real" number of cyls */
5bfb151f 585 void *drive_data; /* used by set_pio_mode/dev_select() */
1da177e4
LT
586 unsigned int failures; /* current failure count */
587 unsigned int max_failures; /* maximum allowed failure count */
e957b60d 588 u64 probed_capacity;/* initial/native media capacity */
1da177e4
LT
589 u64 capacity64; /* total number of sectors */
590
591 int lun; /* logical unit */
592 int crc_count; /* crc counter to reduce drive speed */
b22b2ca4
BP
593
594 unsigned long debug_mask; /* debugging levels switch */
595
e3a59b4d
HR
596#ifdef CONFIG_BLK_DEV_IDEACPI
597 struct ide_acpi_drive_link *acpidata;
598#endif
1da177e4
LT
599 struct list_head list;
600 struct device gendev;
f36d4024 601 struct completion gendev_rel_comp; /* to deal with device release() */
d7c26ebb 602
2b9efba4
BZ
603 /* current packet command */
604 struct ide_atapi_pc *pc;
605
5e2040fd
BZ
606 /* last failed packet command */
607 struct ide_atapi_pc *failed_pc;
608
d7c26ebb 609 /* callback for packet commands */
03a2faae 610 int (*pc_callback)(struct ide_drive_s *, int);
3b8ac539 611
d6251d44
BP
612 ide_startstop_t (*irq_handler)(struct ide_drive_s *);
613
3b8ac539 614 unsigned long atapi_flags;
67c56364
BZ
615
616 struct ide_atapi_pc request_sense_pc;
a1df5169
BP
617
618 /* current sense rq and buffer */
619 bool sense_rq_armed;
9a6d5488 620 bool sense_rq_active;
82ed4db4 621 struct request *sense_rq;
a1df5169 622 struct request_sense sense_data;
60033520
JA
623
624 /* async sense insertion */
625 struct work_struct rq_work;
626 struct list_head rq_list;
d7c26ebb
BP
627};
628
629typedef struct ide_drive_s ide_drive_t;
1da177e4 630
5aeddf90
BP
631#define to_ide_device(dev) container_of(dev, ide_drive_t, gendev)
632
633#define to_ide_drv(obj, cont_type) \
8fed4368 634 container_of(obj, struct cont_type, dev)
5aeddf90
BP
635
636#define ide_drv_g(disk, cont_type) \
637 container_of((disk)->private_data, struct cont_type, driver)
8604affd 638
039788e1 639struct ide_port_info;
1da177e4 640
374e042c
BZ
641struct ide_tp_ops {
642 void (*exec_command)(struct hwif_s *, u8);
643 u8 (*read_status)(struct hwif_s *);
644 u8 (*read_altstatus)(struct hwif_s *);
ecf3a31d 645 void (*write_devctl)(struct hwif_s *, u8);
374e042c 646
abb596b2 647 void (*dev_select)(ide_drive_t *);
c9ff9e7b 648 void (*tf_load)(ide_drive_t *, struct ide_taskfile *, u8);
3153c26b 649 void (*tf_read)(ide_drive_t *, struct ide_taskfile *, u8);
374e042c 650
adb1af98
BZ
651 void (*input_data)(ide_drive_t *, struct ide_cmd *,
652 void *, unsigned int);
653 void (*output_data)(ide_drive_t *, struct ide_cmd *,
654 void *, unsigned int);
374e042c
BZ
655};
656
657extern const struct ide_tp_ops default_tp_ops;
658
39b986a6
BZ
659/**
660 * struct ide_port_ops - IDE port operations
661 *
662 * @init_dev: host specific initialization of a device
663 * @set_pio_mode: routine to program host for PIO mode
664 * @set_dma_mode: routine to program host for DMA mode
39b986a6
BZ
665 * @reset_poll: chipset polling based on hba specifics
666 * @pre_reset: chipset specific changes to default for device-hba resets
667 * @resetproc: routine to reset controller after a disk reset
668 * @maskproc: special host masking for drive selection
669 * @quirkproc: check host's drive quirk list
bfa7d8e5 670 * @clear_irq: clear IRQ
39b986a6
BZ
671 *
672 * @mdma_filter: filter MDMA modes
673 * @udma_filter: filter UDMA modes
674 *
675 * @cable_detect: detect cable type
676 */
ac95beed 677struct ide_port_ops {
e6d95bd1 678 void (*init_dev)(ide_drive_t *);
e085b3ca 679 void (*set_pio_mode)(struct hwif_s *, ide_drive_t *);
8776168c 680 void (*set_dma_mode)(struct hwif_s *, ide_drive_t *);
2a842aca 681 blk_status_t (*reset_poll)(ide_drive_t *);
ac95beed 682 void (*pre_reset)(ide_drive_t *);
ac95beed 683 void (*resetproc)(ide_drive_t *);
ac95beed 684 void (*maskproc)(ide_drive_t *, int);
ac95beed 685 void (*quirkproc)(ide_drive_t *);
bfa7d8e5 686 void (*clear_irq)(ide_drive_t *);
f4d3ffa5 687 int (*test_irq)(struct hwif_s *);
ac95beed
BZ
688
689 u8 (*mdma_filter)(ide_drive_t *);
690 u8 (*udma_filter)(ide_drive_t *);
691
692 u8 (*cable_detect)(struct hwif_s *);
693};
694
5e37bdc0
BZ
695struct ide_dma_ops {
696 void (*dma_host_set)(struct ide_drive_s *, int);
22981694 697 int (*dma_setup)(struct ide_drive_s *, struct ide_cmd *);
5e37bdc0
BZ
698 void (*dma_start)(struct ide_drive_s *);
699 int (*dma_end)(struct ide_drive_s *);
700 int (*dma_test_irq)(struct ide_drive_s *);
701 void (*dma_lost_irq)(struct ide_drive_s *);
35c9b4da 702 /* below ones are optional */
8a4a5738 703 int (*dma_check)(struct ide_drive_s *, struct ide_cmd *);
22117d6e 704 int (*dma_timer_expiry)(struct ide_drive_s *);
35c9b4da 705 void (*dma_clear)(struct ide_drive_s *);
592b5315
SS
706 /*
707 * The following method is optional and only required to be
708 * implemented for the SFF-8038i compatible controllers.
709 */
710 u8 (*dma_sff_read_status)(struct hwif_s *);
5e37bdc0
BZ
711};
712
5880b5de 713enum {
13990cf8 714 IDE_PFLAG_PROBING = BIT(0),
5880b5de
BZ
715};
716
08da591e
BZ
717struct ide_host;
718
1da177e4 719typedef struct hwif_s {
1da177e4 720 struct hwif_s *mate; /* other hwif from same PCI chip */
1da177e4
LT
721 struct proc_dir_entry *proc; /* /proc/ide/ directory entry */
722
08da591e
BZ
723 struct ide_host *host;
724
1da177e4
LT
725 char name[6]; /* name of interface, eg. "ide0" */
726
4c3032d8
BZ
727 struct ide_io_ports io_ports;
728
1da177e4 729 unsigned long sata_scr[SATA_NR_PORTS];
1da177e4 730
2bd24a1c 731 ide_drive_t *devices[MAX_DRIVES + 1];
1da177e4 732
5880b5de
BZ
733 unsigned long port_flags;
734
1da177e4
LT
735 u8 major; /* our major number */
736 u8 index; /* 0 for ide0; 1 for ide1; ... */
737 u8 channel; /* for dual-port chips: 0=primary, 1=secondary */
1da177e4 738
e95d9c6b 739 u32 host_flags;
6a824c92 740
4099d143
BZ
741 u8 pio_mask;
742
1da177e4
LT
743 u8 ultra_mask;
744 u8 mwdma_mask;
745 u8 swdma_mask;
746
49521f97
BZ
747 u8 cbl; /* cable type */
748
1da177e4
LT
749 hwif_chipset_t chipset; /* sub-module for tuning.. */
750
36501650
BZ
751 struct device *dev;
752
1da177e4
LT
753 void (*rw_disk)(ide_drive_t *, struct request *);
754
374e042c 755 const struct ide_tp_ops *tp_ops;
ac95beed 756 const struct ide_port_ops *port_ops;
f37afdac 757 const struct ide_dma_ops *dma_ops;
bfa14b42 758
1da177e4
LT
759 /* dma physical region descriptor table (cpu view) */
760 unsigned int *dmatable_cpu;
761 /* dma physical region descriptor table (dma view) */
762 dma_addr_t dmatable_dma;
2bbd57ca
BZ
763
764 /* maximum number of PRD table entries */
765 int prd_max_nents;
766 /* PRD entry size in bytes */
767 int prd_ent_size;
768
1da177e4
LT
769 /* Scatter-gather list used to build the above */
770 struct scatterlist *sg_table;
771 int sg_max_nents; /* Maximum number of entries in it */
1da177e4 772
22aa4b32 773 struct ide_cmd cmd; /* current command */
d6ff9f64 774
1da177e4
LT
775 int rqsize; /* max sectors per request */
776 int irq; /* our irq number */
777
1da177e4 778 unsigned long dma_base; /* base addr for dma ports */
1da177e4 779
1da177e4
LT
780 unsigned long config_data; /* for use by chipset-specific code */
781 unsigned long select_data; /* for use by chipset-specific code */
782
020e322d
SS
783 unsigned long extra_base; /* extra addr for dma ports */
784 unsigned extra_ports; /* number of extra dma ports */
785
1da177e4 786 unsigned present : 1; /* this interface exists */
5b31f855 787 unsigned busy : 1; /* serializes devices on a port */
1da177e4 788
f74c9141
BZ
789 struct device gendev;
790 struct device *portdev;
791
f36d4024 792 struct completion gendev_rel_comp; /* To deal with device release() */
1da177e4
LT
793
794 void *hwif_data; /* extra hwif data */
795
e3a59b4d
HR
796#ifdef CONFIG_BLK_DEV_IDEACPI
797 struct ide_acpi_hwif_link *acpidata;
798#endif
b65fac32
BZ
799
800 /* IRQ handler, if active */
801 ide_startstop_t (*handler)(ide_drive_t *);
802
803 /* BOOL: polling active & poll_timeout field valid */
804 unsigned int polling : 1;
805
806 /* current drive */
807 ide_drive_t *cur_dev;
808
809 /* current request */
810 struct request *rq;
811
812 /* failsafe timer */
813 struct timer_list timer;
814 /* timeout value during long polls */
815 unsigned long poll_timeout;
816 /* queried upon timeouts */
817 int (*expiry)(ide_drive_t *);
818
819 int req_gen;
820 int req_gen_timer;
821
822 spinlock_t lock;
22fc6ecc 823} ____cacheline_internodealigned_in_smp ide_hwif_t;
1da177e4 824
a36223b0
BZ
825#define MAX_HOST_PORTS 4
826
48c3c107 827struct ide_host {
2bd24a1c 828 ide_hwif_t *ports[MAX_HOST_PORTS + 1];
48c3c107 829 unsigned int n_ports;
6cdf6eb3 830 struct device *dev[2];
e354c1d8 831
2ed0ef54 832 int (*init_chipset)(struct pci_dev *);
e354c1d8
BZ
833
834 void (*get_lock)(irq_handler_t, void *);
835 void (*release_lock)(void);
836
849d7130 837 irq_handler_t irq_handler;
e354c1d8 838
ef0b0427 839 unsigned long host_flags;
255115fb
BZ
840
841 int irq_flags;
842
6cdf6eb3 843 void *host_priv;
bd53cbcc 844 ide_hwif_t *cur_port; /* for hosts requiring serialization */
5b31f855
BZ
845
846 /* used for hosts requiring serialization */
e720b9e4 847 volatile unsigned long host_busy;
48c3c107
BZ
848};
849
5b31f855
BZ
850#define IDE_HOST_BUSY 0
851
1da177e4
LT
852/*
853 * internal ide interrupt handler type
854 */
1da177e4
LT
855typedef ide_startstop_t (ide_handler_t)(ide_drive_t *);
856typedef int (ide_expiry_t)(ide_drive_t *);
857
0eea6458 858/* used by ide-cd, ide-floppy, etc. */
adb1af98 859typedef void (xfer_func_t)(ide_drive_t *, struct ide_cmd *, void *, unsigned);
0eea6458 860
f9383c42 861extern struct mutex ide_setting_mtx;
1da177e4 862
92f1f8fd
EO
863/*
864 * configurable drive settings
865 */
866
13990cf8 867#define DS_SYNC BIT(0)
92f1f8fd
EO
868
869struct ide_devset {
870 int (*get)(ide_drive_t *);
871 int (*set)(ide_drive_t *, int);
872 unsigned int flags;
873};
874
875#define __DEVSET(_flags, _get, _set) { \
876 .flags = _flags, \
877 .get = _get, \
878 .set = _set, \
879}
7662d046 880
8185d5aa 881#define ide_devset_get(name, field) \
92f1f8fd 882static int get_##name(ide_drive_t *drive) \
8185d5aa
BZ
883{ \
884 return drive->field; \
885}
886
887#define ide_devset_set(name, field) \
92f1f8fd 888static int set_##name(ide_drive_t *drive, int arg) \
8185d5aa
BZ
889{ \
890 drive->field = arg; \
891 return 0; \
892}
893
97100fc8
BZ
894#define ide_devset_get_flag(name, flag) \
895static int get_##name(ide_drive_t *drive) \
896{ \
897 return !!(drive->dev_flags & flag); \
898}
899
900#define ide_devset_set_flag(name, flag) \
901static int set_##name(ide_drive_t *drive, int arg) \
902{ \
903 if (arg) \
904 drive->dev_flags |= flag; \
905 else \
906 drive->dev_flags &= ~flag; \
907 return 0; \
908}
909
92f1f8fd
EO
910#define __IDE_DEVSET(_name, _flags, _get, _set) \
911const struct ide_devset ide_devset_##_name = \
912 __DEVSET(_flags, _get, _set)
913
914#define IDE_DEVSET(_name, _flags, _get, _set) \
915static __IDE_DEVSET(_name, _flags, _get, _set)
916
917#define ide_devset_rw(_name, _func) \
918IDE_DEVSET(_name, 0, get_##_func, set_##_func)
919
920#define ide_devset_w(_name, _func) \
921IDE_DEVSET(_name, 0, NULL, set_##_func)
922
f8790489
BZ
923#define ide_ext_devset_rw(_name, _func) \
924__IDE_DEVSET(_name, 0, get_##_func, set_##_func)
925
926#define ide_ext_devset_rw_sync(_name, _func) \
927__IDE_DEVSET(_name, DS_SYNC, get_##_func, set_##_func)
92f1f8fd
EO
928
929#define ide_decl_devset(_name) \
930extern const struct ide_devset ide_devset_##_name
931
932ide_decl_devset(io_32bit);
933ide_decl_devset(keepsettings);
934ide_decl_devset(pio_mode);
935ide_decl_devset(unmaskirq);
936ide_decl_devset(using_dma);
937
7662d046 938#ifdef CONFIG_IDE_PROC_FS
1da177e4 939/*
92f1f8fd 940 * /proc/ide interface
1da177e4
LT
941 */
942
92f1f8fd
EO
943#define ide_devset_rw_field(_name, _field) \
944ide_devset_get(_name, _field); \
945ide_devset_set(_name, _field); \
946IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name)
947
2fd3c5c6
DC
948#define ide_devset_ro_field(_name, _field) \
949ide_devset_get(_name, _field); \
950IDE_DEVSET(_name, 0, get_##_name, NULL)
951
97100fc8
BZ
952#define ide_devset_rw_flag(_name, _field) \
953ide_devset_get_flag(_name, _field); \
954ide_devset_set_flag(_name, _field); \
955IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name)
956
92f1f8fd
EO
957struct ide_proc_devset {
958 const char *name;
959 const struct ide_devset *setting;
960 int min, max;
961 int (*mulf)(ide_drive_t *);
962 int (*divf)(ide_drive_t *);
8185d5aa
BZ
963};
964
92f1f8fd
EO
965#define __IDE_PROC_DEVSET(_name, _min, _max, _mulf, _divf) { \
966 .name = __stringify(_name), \
967 .setting = &ide_devset_##_name, \
968 .min = _min, \
969 .max = _max, \
970 .mulf = _mulf, \
971 .divf = _divf, \
8185d5aa
BZ
972}
973
92f1f8fd
EO
974#define IDE_PROC_DEVSET(_name, _min, _max) \
975__IDE_PROC_DEVSET(_name, _min, _max, NULL, NULL)
8185d5aa 976
1da177e4
LT
977typedef struct {
978 const char *name;
d161a13f 979 umode_t mode;
ec7d9c9c 980 int (*show)(struct seq_file *, void *);
1da177e4
LT
981} ide_proc_entry_t;
982
ecfd80e4
BZ
983void proc_ide_create(void);
984void proc_ide_destroy(void);
5cbf79cd 985void ide_proc_register_port(ide_hwif_t *);
d9270a3f 986void ide_proc_port_register_devices(ide_hwif_t *);
5b0c4b30 987void ide_proc_unregister_device(ide_drive_t *);
5cbf79cd 988void ide_proc_unregister_port(ide_hwif_t *);
7f3c868b
BZ
989void ide_proc_register_driver(ide_drive_t *, struct ide_driver *);
990void ide_proc_unregister_driver(ide_drive_t *, struct ide_driver *);
7662d046 991
ec7d9c9c
CH
992int ide_capacity_proc_show(struct seq_file *m, void *v);
993int ide_geometry_proc_show(struct seq_file *m, void *v);
1da177e4 994#else
ecfd80e4
BZ
995static inline void proc_ide_create(void) { ; }
996static inline void proc_ide_destroy(void) { ; }
5cbf79cd 997static inline void ide_proc_register_port(ide_hwif_t *hwif) { ; }
d9270a3f 998static inline void ide_proc_port_register_devices(ide_hwif_t *hwif) { ; }
5b0c4b30 999static inline void ide_proc_unregister_device(ide_drive_t *drive) { ; }
5cbf79cd 1000static inline void ide_proc_unregister_port(ide_hwif_t *hwif) { ; }
7f3c868b
BZ
1001static inline void ide_proc_register_driver(ide_drive_t *drive,
1002 struct ide_driver *driver) { ; }
1003static inline void ide_proc_unregister_driver(ide_drive_t *drive,
1004 struct ide_driver *driver) { ; }
1da177e4
LT
1005#endif
1006
e1c7c464
BP
1007enum {
1008 /* enter/exit functions */
13990cf8 1009 IDE_DBG_FUNC = BIT(0),
e1c7c464 1010 /* sense key/asc handling */
13990cf8 1011 IDE_DBG_SENSE = BIT(1),
e1c7c464 1012 /* packet commands handling */
13990cf8 1013 IDE_DBG_PC = BIT(2),
e1c7c464 1014 /* request handling */
13990cf8 1015 IDE_DBG_RQ = BIT(3),
e1c7c464 1016 /* driver probing/setup */
13990cf8 1017 IDE_DBG_PROBE = BIT(4),
e1c7c464
BP
1018};
1019
1020/* DRV_NAME has to be defined in the driver before using the macro below */
088b1b88
BP
1021#define __ide_debug_log(lvl, fmt, args...) \
1022{ \
1023 if (unlikely(drive->debug_mask & lvl)) \
1024 printk(KERN_INFO DRV_NAME ": %s: " fmt "\n", \
1025 __func__, ## args); \
e1c7c464
BP
1026}
1027
1da177e4 1028/*
0d346ba0 1029 * Power Management state machine (rq->pm->pm_step).
1da177e4 1030 *
0d346ba0 1031 * For each step, the core calls ide_start_power_step() first.
1da177e4
LT
1032 * This can return:
1033 * - ide_stopped : In this case, the core calls us back again unless
1034 * step have been set to ide_power_state_completed.
1035 * - ide_started : In this case, the channel is left busy until an
1036 * async event (interrupt) occurs.
0d346ba0 1037 * Typically, ide_start_power_step() will issue a taskfile request with
1da177e4
LT
1038 * do_rw_taskfile().
1039 *
0d346ba0 1040 * Upon reception of the interrupt, the core will call ide_complete_power_step()
1da177e4
LT
1041 * with the error code if any. This routine should update the step value
1042 * and return. It should not start a new request. The core will call
0d346ba0
BZ
1043 * ide_start_power_step() for the new step value, unless step have been
1044 * set to IDE_PM_COMPLETED.
1da177e4 1045 */
1da177e4 1046enum {
0d346ba0
BZ
1047 IDE_PM_START_SUSPEND,
1048 IDE_PM_FLUSH_CACHE = IDE_PM_START_SUSPEND,
1049 IDE_PM_STANDBY,
1050
1051 IDE_PM_START_RESUME,
1052 IDE_PM_RESTORE_PIO = IDE_PM_START_RESUME,
1053 IDE_PM_IDLE,
1054 IDE_PM_RESTORE_DMA,
1055
1056 IDE_PM_COMPLETED,
1da177e4
LT
1057};
1058
e2984c62
BZ
1059int generic_ide_suspend(struct device *, pm_message_t);
1060int generic_ide_resume(struct device *);
1061
1062void ide_complete_power_step(ide_drive_t *, struct request *);
1063ide_startstop_t ide_start_power_step(ide_drive_t *, struct request *);
3616b653 1064void ide_complete_pm_rq(ide_drive_t *, struct request *);
e2984c62
BZ
1065void ide_check_pm_state(ide_drive_t *, struct request *);
1066
1da177e4
LT
1067/*
1068 * Subdrivers support.
4ef3b8f4
LR
1069 *
1070 * The gendriver.owner field should be set to the module owner of this driver.
1071 * The gendriver.name field should be set to the name of this driver
1da177e4 1072 */
7f3c868b 1073struct ide_driver {
1da177e4 1074 const char *version;
1da177e4 1075 ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t);
1da177e4 1076 struct device_driver gen_driver;
4031bbe4
RK
1077 int (*probe)(ide_drive_t *);
1078 void (*remove)(ide_drive_t *);
0d2157f7 1079 void (*resume)(ide_drive_t *);
4031bbe4 1080 void (*shutdown)(ide_drive_t *);
7662d046 1081#ifdef CONFIG_IDE_PROC_FS
79cb3803
BZ
1082 ide_proc_entry_t * (*proc_entries)(ide_drive_t *);
1083 const struct ide_proc_devset * (*proc_devsets)(ide_drive_t *);
7662d046
BZ
1084#endif
1085};
1da177e4 1086
7f3c868b 1087#define to_ide_driver(drv) container_of(drv, struct ide_driver, gen_driver)
4031bbe4 1088
08da591e
BZ
1089int ide_device_get(ide_drive_t *);
1090void ide_device_put(ide_drive_t *);
1091
aa768773
BZ
1092struct ide_ioctl_devset {
1093 unsigned int get_ioctl;
1094 unsigned int set_ioctl;
92f1f8fd 1095 const struct ide_devset *setting;
aa768773
BZ
1096};
1097
1098int ide_setting_ioctl(ide_drive_t *, struct block_device *, unsigned int,
1099 unsigned long, const struct ide_ioctl_devset *);
1100
1bddd9e6 1101int generic_ide_ioctl(ide_drive_t *, struct block_device *, unsigned, unsigned long);
1da177e4 1102
ebae41a5
BZ
1103extern int ide_vlb_clk;
1104extern int ide_pci_clk;
1105
2a842aca 1106int ide_end_rq(ide_drive_t *, struct request *, blk_status_t, unsigned int);
327fa1c2 1107void ide_kill_rq(ide_drive_t *, struct request *);
60033520 1108void ide_insert_request_head(ide_drive_t *, struct request *);
327fa1c2 1109
60c0cd02
BZ
1110void __ide_set_handler(ide_drive_t *, ide_handler_t *, unsigned int);
1111void ide_set_handler(ide_drive_t *, ide_handler_t *, unsigned int);
1da177e4 1112
35b5d0be
BZ
1113void ide_execute_command(ide_drive_t *, struct ide_cmd *, ide_handler_t *,
1114 unsigned int);
1fc14258 1115
9f87abe8
BZ
1116void ide_pad_transfer(ide_drive_t *, int, int);
1117
9892ec54 1118ide_startstop_t ide_error(ide_drive_t *, const char *, u8);
1da177e4 1119
4dde4492 1120void ide_fix_driveid(u16 *);
01745112 1121
1da177e4
LT
1122extern void ide_fixstring(u8 *, const int, const int);
1123
28ee9bc5 1124int ide_busy_sleep(ide_drive_t *, unsigned long, int);
b163f46d 1125
fa56d4cb 1126int __ide_wait_stat(ide_drive_t *, u8, u8, unsigned long, u8 *);
74af21cf 1127int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long);
1da177e4 1128
c4e66c36 1129ide_startstop_t ide_do_park_unpark(ide_drive_t *, struct request *);
11938c92 1130ide_startstop_t ide_do_devset(ide_drive_t *, struct request *);
c4e66c36 1131
1da177e4
LT
1132extern ide_startstop_t ide_do_reset (ide_drive_t *);
1133
92f1f8fd
EO
1134extern int ide_devset_execute(ide_drive_t *drive,
1135 const struct ide_devset *setting, int arg);
1136
22aa4b32 1137void ide_complete_cmd(ide_drive_t *, struct ide_cmd *, u8, u8);
2a842aca 1138int ide_complete_rq(ide_drive_t *, blk_status_t, unsigned int);
1da177e4 1139
3153c26b 1140void ide_tf_readback(ide_drive_t *drive, struct ide_cmd *cmd);
745483f1 1141void ide_tf_dump(const char *, struct ide_cmd *);
1da177e4 1142
374e042c
BZ
1143void ide_exec_command(ide_hwif_t *, u8);
1144u8 ide_read_status(ide_hwif_t *);
1145u8 ide_read_altstatus(ide_hwif_t *);
ecf3a31d 1146void ide_write_devctl(ide_hwif_t *, u8);
374e042c 1147
abb596b2 1148void ide_dev_select(ide_drive_t *);
c9ff9e7b 1149void ide_tf_load(ide_drive_t *, struct ide_taskfile *, u8);
3153c26b 1150void ide_tf_read(ide_drive_t *, struct ide_taskfile *, u8);
374e042c 1151
adb1af98
BZ
1152void ide_input_data(ide_drive_t *, struct ide_cmd *, void *, unsigned int);
1153void ide_output_data(ide_drive_t *, struct ide_cmd *, void *, unsigned int);
374e042c 1154
ed4af48f 1155void SELECT_MASK(ide_drive_t *, int);
1da177e4 1156
92eb4380 1157u8 ide_read_error(ide_drive_t *);
1823649b 1158void ide_read_bcount_and_ireason(ide_drive_t *, u16 *, u8 *);
92eb4380 1159
103f7033
BP
1160int ide_check_ireason(ide_drive_t *, struct request *, int, int, int);
1161
51509eec
BZ
1162int ide_check_atapi_device(ide_drive_t *, const char *);
1163
7bf7420a
BZ
1164void ide_init_pc(struct ide_atapi_pc *);
1165
4abdc6ee
EO
1166/* Disk head parking */
1167extern wait_queue_head_t ide_park_wq;
1168ssize_t ide_park_show(struct device *dev, struct device_attribute *attr,
1169 char *buf);
1170ssize_t ide_park_store(struct device *dev, struct device_attribute *attr,
1171 const char *buf, size_t len);
1172
7645c151
BZ
1173/*
1174 * Special requests for ide-tape block device strategy routine.
1175 *
1176 * In order to service a character device command, we add special requests to
1177 * the tail of our block device request queue and wait for their completion.
1178 */
1179enum {
13990cf8
AS
1180 REQ_IDETAPE_PC1 = BIT(0), /* packet command (first stage) */
1181 REQ_IDETAPE_PC2 = BIT(1), /* packet command (second stage) */
1182 REQ_IDETAPE_READ = BIT(2),
1183 REQ_IDETAPE_WRITE = BIT(3),
7645c151
BZ
1184};
1185
5a0e43b5 1186int ide_queue_pc_tail(ide_drive_t *, struct gendisk *, struct ide_atapi_pc *,
b13345f3 1187 void *, unsigned int);
7645c151 1188
de699ad5 1189int ide_do_test_unit_ready(ide_drive_t *, struct gendisk *);
0c8a6c7a 1190int ide_do_start_stop(ide_drive_t *, struct gendisk *, int);
0578042d 1191int ide_set_media_lock(ide_drive_t *, struct gendisk *, int);
6b0da28b 1192void ide_create_request_sense_cmd(ide_drive_t *, struct ide_atapi_pc *);
6b544fcc 1193void ide_retry_pc(ide_drive_t *drive);
0578042d 1194
a1df5169 1195void ide_prep_sense(ide_drive_t *drive, struct request *rq);
5c4be572 1196int ide_queue_sense_rq(ide_drive_t *drive, void *special);
a1df5169 1197
4cad085e 1198int ide_cd_expiry(ide_drive_t *);
844b9468 1199
392de1d5
BP
1200int ide_cd_get_xferlen(struct request *);
1201
b788ee9c 1202ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_cmd *);
594c16d8 1203
22aa4b32 1204ide_startstop_t do_rw_taskfile(ide_drive_t *, struct ide_cmd *);
1da177e4 1205
a08915ba
BZ
1206void ide_pio_bytes(ide_drive_t *, struct ide_cmd *, unsigned int, unsigned int);
1207
adb1af98 1208void ide_finish_cmd(ide_drive_t *, struct ide_cmd *, u8);
4d7a984b 1209
22aa4b32
BZ
1210int ide_raw_taskfile(ide_drive_t *, struct ide_cmd *, u8 *, u16);
1211int ide_no_data_taskfile(ide_drive_t *, struct ide_cmd *);
9a3c49be 1212
22aa4b32 1213int ide_taskfile_ioctl(ide_drive_t *, unsigned long);
1da177e4 1214
fa56d4cb 1215int ide_dev_read_id(ide_drive_t *, u8, u16 *, int);
2ebe1d9e 1216
1da177e4 1217extern int ide_driveid_update(ide_drive_t *);
1da177e4
LT
1218extern int ide_config_drive_speed(ide_drive_t *, u8);
1219extern u8 eighty_ninty_three (ide_drive_t *);
1da177e4
LT
1220extern int taskfile_lib_get_identify(ide_drive_t *drive, u8 *);
1221
1222extern int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout);
1223
1da177e4
LT
1224extern void ide_stall_queue(ide_drive_t *drive, unsigned long timeout);
1225
10738ba8 1226extern void ide_timer_expiry(struct timer_list *t);
7d12e780 1227extern irqreturn_t ide_intr(int irq, void *dev_id);
60033520 1228extern blk_status_t ide_queue_rq(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);
9a6d5488 1229extern blk_status_t ide_issue_rq(ide_drive_t *, struct request *, bool);
6072f749 1230extern void ide_requeue_and_plug(ide_drive_t *drive, struct request *rq);
1da177e4
LT
1231
1232void ide_init_disk(struct gendisk *, ide_drive_t *);
1233
6d208b39 1234#ifdef CONFIG_IDEPCI_PCIBUS_ORDER
725522b5
GKH
1235extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *owner, const char *mod_name);
1236#define ide_pci_register_driver(d) __ide_pci_register_driver(d, THIS_MODULE, KBUILD_MODNAME)
6d208b39
BZ
1237#else
1238#define ide_pci_register_driver(d) pci_register_driver(d)
1239#endif
1240
6636487e
BZ
1241static inline int ide_pci_is_in_compatibility_mode(struct pci_dev *dev)
1242{
1243 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5)
1244 return 1;
1245 return 0;
1246}
1247
86ccf37c 1248void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *,
9f36d314 1249 struct ide_hw *, struct ide_hw **);
85620436 1250void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *);
1da177e4 1251
8e882ba1 1252#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
b123f56e
BZ
1253int ide_pci_set_master(struct pci_dev *, const char *);
1254unsigned long ide_pci_dma_base(ide_hwif_t *, const struct ide_port_info *);
ebb00fb5 1255int ide_pci_check_simplex(ide_hwif_t *, const struct ide_port_info *);
b123f56e 1256int ide_hwif_setup_dma(ide_hwif_t *, const struct ide_port_info *);
c413b9b9 1257#else
b123f56e
BZ
1258static inline int ide_hwif_setup_dma(ide_hwif_t *hwif,
1259 const struct ide_port_info *d)
1260{
1261 return -EINVAL;
1262}
c413b9b9
BZ
1263#endif
1264
c0ae5023 1265struct ide_pci_enablebit {
1da177e4
LT
1266 u8 reg; /* byte pci reg holding the enable-bit */
1267 u8 mask; /* mask to isolate the enable-bit */
1268 u8 val; /* value of masked reg when "enabled" */
c0ae5023 1269};
1da177e4
LT
1270
1271enum {
1272 /* Uses ISA control ports not PCI ones. */
13990cf8 1273 IDE_HFLAG_ISA_PORTS = BIT(0),
6a824c92 1274 /* single port device */
13990cf8 1275 IDE_HFLAG_SINGLE = BIT(1),
6a824c92 1276 /* don't use legacy PIO blacklist */
13990cf8 1277 IDE_HFLAG_PIO_NO_BLACKLIST = BIT(2),
e277f91f 1278 /* set for the second port of QD65xx */
13990cf8 1279 IDE_HFLAG_QD_2ND_PORT = BIT(3),
26bcb879 1280 /* use PIO8/9 for prefetch off/on */
13990cf8 1281 IDE_HFLAG_ABUSE_PREFETCH = BIT(4),
26bcb879 1282 /* use PIO6/7 for fast-devsel off/on */
13990cf8 1283 IDE_HFLAG_ABUSE_FAST_DEVSEL = BIT(5),
26bcb879 1284 /* use 100-102 and 200-202 PIO values to set DMA modes */
13990cf8 1285 IDE_HFLAG_ABUSE_DMA_MODES = BIT(6),
aedea591
BZ
1286 /*
1287 * keep DMA setting when programming PIO mode, may be used only
1288 * for hosts which have separate PIO and DMA timings (ie. PMAC)
1289 */
13990cf8 1290 IDE_HFLAG_SET_PIO_MODE_KEEP_DMA = BIT(7),
88b2b32b 1291 /* program host for the transfer mode after programming device */
13990cf8 1292 IDE_HFLAG_POST_SET_MODE = BIT(8),
88b2b32b 1293 /* don't program host/device for the transfer mode ("smart" hosts) */
13990cf8 1294 IDE_HFLAG_NO_SET_MODE = BIT(9),
0ae2e178 1295 /* trust BIOS for programming chipset/device for DMA */
13990cf8 1296 IDE_HFLAG_TRUST_BIOS_FOR_DMA = BIT(10),
cafa027b 1297 /* host is CS5510/CS5520 */
13990cf8 1298 IDE_HFLAG_CS5520 = BIT(11),
33c1002e 1299 /* ATAPI DMA is unsupported */
13990cf8 1300 IDE_HFLAG_NO_ATAPI_DMA = BIT(12),
5e71d9c5 1301 /* set if host is a "non-bootable" controller */
13990cf8 1302 IDE_HFLAG_NON_BOOTABLE = BIT(13),
47b68788 1303 /* host doesn't support DMA */
13990cf8 1304 IDE_HFLAG_NO_DMA = BIT(14),
47b68788 1305 /* check if host is PCI IDE device before allowing DMA */
13990cf8 1306 IDE_HFLAG_NO_AUTODMA = BIT(15),
c5dd43ec 1307 /* host uses MMIO */
13990cf8 1308 IDE_HFLAG_MMIO = BIT(16),
238e4f14 1309 /* no LBA48 */
13990cf8 1310 IDE_HFLAG_NO_LBA48 = BIT(17),
238e4f14 1311 /* no LBA48 DMA */
13990cf8 1312 IDE_HFLAG_NO_LBA48_DMA = BIT(18),
ed67b923 1313 /* data FIFO is cleared by an error */
13990cf8 1314 IDE_HFLAG_ERROR_STOPS_FIFO = BIT(19),
1c51361a 1315 /* serialize ports */
13990cf8 1316 IDE_HFLAG_SERIALIZE = BIT(20),
2787cb8a 1317 /* host is DTC2278 */
13990cf8 1318 IDE_HFLAG_DTC2278 = BIT(21),
c094ea07 1319 /* 4 devices on a single set of I/O ports */
13990cf8 1320 IDE_HFLAG_4DRIVES = BIT(22),
1f66019b 1321 /* host is TRM290 */
13990cf8 1322 IDE_HFLAG_TRM290 = BIT(23),
caea7602 1323 /* use 32-bit I/O ops */
13990cf8 1324 IDE_HFLAG_IO_32BIT = BIT(24),
caea7602 1325 /* unmask IRQs */
13990cf8
AS
1326 IDE_HFLAG_UNMASK_IRQS = BIT(25),
1327 IDE_HFLAG_BROKEN_ALTSTATUS = BIT(26),
1fd18905 1328 /* serialize ports if DMA is possible (for sl82c105) */
13990cf8 1329 IDE_HFLAG_SERIALIZE_DMA = BIT(27),
8ac2b42a 1330 /* force host out of "simplex" mode */
13990cf8 1331 IDE_HFLAG_CLEAR_SIMPLEX = BIT(28),
4166c199 1332 /* DSC overlap is unsupported */
13990cf8 1333 IDE_HFLAG_NO_DSC = BIT(29),
807b90d0 1334 /* never use 32-bit I/O ops */
13990cf8 1335 IDE_HFLAG_NO_IO_32BIT = BIT(30),
807b90d0 1336 /* never unmask IRQs */
13990cf8 1337 IDE_HFLAG_NO_UNMASK_IRQS = BIT(31),
1da177e4
LT
1338};
1339
7cab14a7 1340#ifdef CONFIG_BLK_DEV_OFFBOARD
7cab14a7 1341# define IDE_HFLAG_OFF_BOARD 0
5e71d9c5
BZ
1342#else
1343# define IDE_HFLAG_OFF_BOARD IDE_HFLAG_NON_BOOTABLE
7cab14a7
BZ
1344#endif
1345
039788e1 1346struct ide_port_info {
1da177e4 1347 char *name;
e354c1d8 1348
2ed0ef54 1349 int (*init_chipset)(struct pci_dev *);
e354c1d8
BZ
1350
1351 void (*get_lock)(irq_handler_t, void *);
1352 void (*release_lock)(void);
1353
1da177e4
LT
1354 void (*init_iops)(ide_hwif_t *);
1355 void (*init_hwif)(ide_hwif_t *);
b123f56e
BZ
1356 int (*init_dma)(ide_hwif_t *,
1357 const struct ide_port_info *);
ac95beed 1358
374e042c 1359 const struct ide_tp_ops *tp_ops;
ac95beed 1360 const struct ide_port_ops *port_ops;
f37afdac 1361 const struct ide_dma_ops *dma_ops;
ac95beed 1362
c0ae5023
BZ
1363 struct ide_pci_enablebit enablebits[2];
1364
528a572d 1365 hwif_chipset_t chipset;
6b492496
BZ
1366
1367 u16 max_sectors; /* if < than the default one */
1368
9ffcf364 1369 u32 host_flags;
255115fb
BZ
1370
1371 int irq_flags;
1372
4099d143 1373 u8 pio_mask;
5f8b6c34
BZ
1374 u8 swdma_mask;
1375 u8 mwdma_mask;
18137207 1376 u8 udma_mask;
039788e1 1377};
1da177e4 1378
a7928c15
CH
1379/*
1380 * State information carried for REQ_TYPE_ATA_PM_SUSPEND and REQ_TYPE_ATA_PM_RESUME
1381 * requests.
1382 */
1383struct ide_pm_state {
1384 /* PM state machine step value, currently driver specific */
1385 int pm_step;
1386 /* requested PM state value (S1, S2, S3, S4, ...) */
1387 u32 pm_state;
1388 void* data; /* for driver use */
1389};
1390
1391
6cdf6eb3
BZ
1392int ide_pci_init_one(struct pci_dev *, const struct ide_port_info *, void *);
1393int ide_pci_init_two(struct pci_dev *, struct pci_dev *,
1394 const struct ide_port_info *, void *);
ef0b0427 1395void ide_pci_remove(struct pci_dev *);
1da177e4 1396
feb22b7f
BZ
1397#ifdef CONFIG_PM
1398int ide_pci_suspend(struct pci_dev *, pm_message_t);
1399int ide_pci_resume(struct pci_dev *);
1400#else
1401#define ide_pci_suspend NULL
1402#define ide_pci_resume NULL
1403#endif
1404
22981694 1405void ide_map_sg(ide_drive_t *, struct ide_cmd *);
bf717c0a 1406void ide_init_sg_cmd(struct ide_cmd *, unsigned int);
1da177e4
LT
1407
1408#define BAD_DMA_DRIVE 0
1409#define GOOD_DMA_DRIVE 1
1410
65e5f2e3
JC
1411struct drive_list_entry {
1412 const char *id_model;
1413 const char *id_firmware;
1414};
1415
4dde4492 1416int ide_in_drive_list(u16 *, const struct drive_list_entry *);
a5b7e70d
BZ
1417
1418#ifdef CONFIG_BLK_DEV_IDEDMA
2dbe7e91 1419int ide_dma_good_drive(ide_drive_t *);
1da177e4 1420int __ide_dma_bad_drive(ide_drive_t *);
7670df73
BZ
1421
1422u8 ide_find_dma_mode(ide_drive_t *, u8);
1423
1424static inline u8 ide_max_dma_mode(ide_drive_t *drive)
1425{
1426 return ide_find_dma_mode(drive, XFER_UDMA_6);
1427}
1428
4a546e04 1429void ide_dma_off_quietly(ide_drive_t *);
7469aaf6 1430void ide_dma_off(ide_drive_t *);
4a546e04 1431void ide_dma_on(ide_drive_t *);
3608b5d7 1432int ide_set_dma(ide_drive_t *);
578cfa0d 1433void ide_check_dma_crc(ide_drive_t *);
1da177e4
LT
1434ide_startstop_t ide_dma_intr(ide_drive_t *);
1435
2bbd57ca
BZ
1436int ide_allocate_dma_engine(ide_hwif_t *);
1437void ide_release_dma_engine(ide_hwif_t *);
1438
5ae5412d 1439int ide_dma_prepare(ide_drive_t *, struct ide_cmd *);
f094d4d8 1440void ide_dma_unmap_sg(ide_drive_t *, struct ide_cmd *);
062f9f02 1441
8e882ba1 1442#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
2dbe7e91 1443int config_drive_for_dma(ide_drive_t *);
22981694 1444int ide_build_dmatable(ide_drive_t *, struct ide_cmd *);
15ce926a 1445void ide_dma_host_set(ide_drive_t *, int);
22981694 1446int ide_dma_setup(ide_drive_t *, struct ide_cmd *);
1da177e4 1447extern void ide_dma_start(ide_drive_t *);
653bcf52 1448int ide_dma_end(ide_drive_t *);
f37afdac 1449int ide_dma_test_irq(ide_drive_t *);
22117d6e 1450int ide_dma_sff_timer_expiry(ide_drive_t *);
592b5315 1451u8 ide_dma_sff_read_status(ide_hwif_t *);
71fc9fcc 1452extern const struct ide_dma_ops sff_dma_ops;
2dbe7e91
BZ
1453#else
1454static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
8e882ba1 1455#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
1da177e4 1456
de23ec9c 1457void ide_dma_lost_irq(ide_drive_t *);
65ca5377 1458ide_startstop_t ide_dma_timeout_retry(ide_drive_t *, int);
de23ec9c 1459
1da177e4 1460#else
7670df73 1461static inline u8 ide_find_dma_mode(ide_drive_t *drive, u8 speed) { return 0; }
2d5eaa6d 1462static inline u8 ide_max_dma_mode(ide_drive_t *drive) { return 0; }
4a546e04 1463static inline void ide_dma_off_quietly(ide_drive_t *drive) { ; }
7469aaf6 1464static inline void ide_dma_off(ide_drive_t *drive) { ; }
4a546e04 1465static inline void ide_dma_on(ide_drive_t *drive) { ; }
1da177e4 1466static inline void ide_dma_verbose(ide_drive_t *drive) { ; }
3608b5d7 1467static inline int ide_set_dma(ide_drive_t *drive) { return 1; }
578cfa0d 1468static inline void ide_check_dma_crc(ide_drive_t *drive) { ; }
22117d6e 1469static inline ide_startstop_t ide_dma_intr(ide_drive_t *drive) { return ide_stopped; }
65ca5377 1470static inline ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error) { return ide_stopped; }
0d1bad21 1471static inline void ide_release_dma_engine(ide_hwif_t *hwif) { ; }
5ae5412d
BZ
1472static inline int ide_dma_prepare(ide_drive_t *drive,
1473 struct ide_cmd *cmd) { return 1; }
f094d4d8
BZ
1474static inline void ide_dma_unmap_sg(ide_drive_t *drive,
1475 struct ide_cmd *cmd) { ; }
2bbd57ca 1476#endif /* CONFIG_BLK_DEV_IDEDMA */
1da177e4 1477
e3a59b4d 1478#ifdef CONFIG_BLK_DEV_IDEACPI
8b803bd1 1479int ide_acpi_init(void);
2bf427b2 1480bool ide_port_acpi(ide_hwif_t *hwif);
e3a59b4d
HR
1481extern int ide_acpi_exec_tfs(ide_drive_t *drive);
1482extern void ide_acpi_get_timing(ide_hwif_t *hwif);
1483extern void ide_acpi_push_timing(ide_hwif_t *hwif);
8b803bd1 1484void ide_acpi_init_port(ide_hwif_t *);
eafd88a3 1485void ide_acpi_port_init_devices(ide_hwif_t *);
5e32132b 1486extern void ide_acpi_set_state(ide_hwif_t *hwif, int on);
e3a59b4d 1487#else
8b803bd1 1488static inline int ide_acpi_init(void) { return 0; }
2bf427b2 1489static inline bool ide_port_acpi(ide_hwif_t *hwif) { return 0; }
e3a59b4d
HR
1490static inline int ide_acpi_exec_tfs(ide_drive_t *drive) { return 0; }
1491static inline void ide_acpi_get_timing(ide_hwif_t *hwif) { ; }
1492static inline void ide_acpi_push_timing(ide_hwif_t *hwif) { ; }
8b803bd1 1493static inline void ide_acpi_init_port(ide_hwif_t *hwif) { ; }
eafd88a3 1494static inline void ide_acpi_port_init_devices(ide_hwif_t *hwif) { ; }
5e32132b 1495static inline void ide_acpi_set_state(ide_hwif_t *hwif, int on) {}
e3a59b4d
HR
1496#endif
1497
1da177e4
LT
1498void ide_register_region(struct gendisk *);
1499void ide_unregister_region(struct gendisk *);
1500
8bc1e5aa 1501void ide_check_nien_quirk_list(ide_drive_t *);
f01393e4 1502void ide_undecoded_slave(ide_drive_t *);
1da177e4 1503
9fd91d95 1504void ide_port_apply_params(ide_hwif_t *);
ebdab07d 1505int ide_sysfs_register_port(ide_hwif_t *);
9fd91d95 1506
9f36d314 1507struct ide_host *ide_host_alloc(const struct ide_port_info *, struct ide_hw **,
dca39830 1508 unsigned int);
8a69580e 1509void ide_host_free(struct ide_host *);
48c3c107 1510int ide_host_register(struct ide_host *, const struct ide_port_info *,
9f36d314
BZ
1511 struct ide_hw **);
1512int ide_host_add(const struct ide_port_info *, struct ide_hw **, unsigned int,
6f904d01 1513 struct ide_host **);
48c3c107 1514void ide_host_remove(struct ide_host *);
0bfeee7d 1515int ide_legacy_device_add(const struct ide_port_info *, unsigned long);
2dde7861
BZ
1516void ide_port_unregister_devices(ide_hwif_t *);
1517void ide_port_scan(ide_hwif_t *);
1da177e4
LT
1518
1519static inline void *ide_get_hwifdata (ide_hwif_t * hwif)
1520{
1521 return hwif->hwif_data;
1522}
1523
1524static inline void ide_set_hwifdata (ide_hwif_t * hwif, void *data)
1525{
1526 hwif->hwif_data = data;
1527}
1528
745483f1 1529u64 ide_get_lba_addr(struct ide_cmd *, int);
1da177e4
LT
1530u8 ide_dump_status(ide_drive_t *, const char *, u8);
1531
3be53f3f
BZ
1532struct ide_timing {
1533 u8 mode;
1534 u8 setup; /* t1 */
1535 u16 act8b; /* t2 for 8-bit io */
1536 u16 rec8b; /* t2i for 8-bit io */
1537 u16 cyc8b; /* t0 for 8-bit io */
1538 u16 active; /* t2 or tD */
1539 u16 recover; /* t2i or tK */
1540 u16 cycle; /* t0 */
1541 u16 udma; /* t2CYCTYP/2 */
1542};
1543
1544enum {
13990cf8
AS
1545 IDE_TIMING_SETUP = BIT(0),
1546 IDE_TIMING_ACT8B = BIT(1),
1547 IDE_TIMING_REC8B = BIT(2),
1548 IDE_TIMING_CYC8B = BIT(3),
3be53f3f
BZ
1549 IDE_TIMING_8BIT = IDE_TIMING_ACT8B | IDE_TIMING_REC8B |
1550 IDE_TIMING_CYC8B,
13990cf8
AS
1551 IDE_TIMING_ACTIVE = BIT(4),
1552 IDE_TIMING_RECOVER = BIT(5),
1553 IDE_TIMING_CYCLE = BIT(6),
1554 IDE_TIMING_UDMA = BIT(7),
3be53f3f
BZ
1555 IDE_TIMING_ALL = IDE_TIMING_SETUP | IDE_TIMING_8BIT |
1556 IDE_TIMING_ACTIVE | IDE_TIMING_RECOVER |
1557 IDE_TIMING_CYCLE | IDE_TIMING_UDMA,
1558};
1559
f06ab340 1560struct ide_timing *ide_timing_find_mode(u8);
c9d6c1a2 1561u16 ide_pio_cycle_time(ide_drive_t *, u8);
f06ab340
BZ
1562void ide_timing_merge(struct ide_timing *, struct ide_timing *,
1563 struct ide_timing *, unsigned int);
1564int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int);
1565
7eeaaaa5 1566#ifdef CONFIG_IDE_XFER_MODE
9ad54093 1567int ide_scan_pio_blacklist(char *);
7eeaaaa5 1568const char *ide_xfer_verbose(u8);
c9ef59ff 1569int ide_pio_need_iordy(ide_drive_t *, const u8);
88b2b32b
BZ
1570int ide_set_pio_mode(ide_drive_t *, u8);
1571int ide_set_dma_mode(ide_drive_t *, u8);
26bcb879 1572void ide_set_pio(ide_drive_t *, u8);
7eeaaaa5
BZ
1573int ide_set_xfer_rate(ide_drive_t *, u8);
1574#else
1575static inline void ide_set_pio(ide_drive_t *drive, u8 pio) { ; }
1576static inline int ide_set_xfer_rate(ide_drive_t *drive, u8 rate) { return -1; }
1577#endif
26bcb879
BZ
1578
1579static inline void ide_set_max_pio(ide_drive_t *drive)
1580{
1581 ide_set_pio(drive, 255);
1582}
1da177e4 1583
ebdab07d
BZ
1584char *ide_media_string(ide_drive_t *);
1585
fb3fed79 1586extern const struct attribute_group *ide_dev_groups[];
1da177e4 1587extern struct bus_type ide_bus_type;
f74c9141 1588extern struct class *ide_port_class;
1da177e4 1589
7b9f25b5
BZ
1590static inline void ide_dump_identify(u8 *id)
1591{
1592 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 2, id, 512, 0);
1593}
1594
86b37860
CL
1595static inline int hwif_to_node(ide_hwif_t *hwif)
1596{
96f80219 1597 return hwif->dev ? dev_to_node(hwif->dev) : -1;
86b37860
CL
1598}
1599
7e59ea21 1600static inline ide_drive_t *ide_get_pair_dev(ide_drive_t *drive)
1b678347 1601{
5e7f3a46 1602 ide_drive_t *peer = drive->hwif->devices[(drive->dn ^ 1) & 1];
1b678347 1603
97100fc8 1604 return (peer->dev_flags & IDE_DFLAG_PRESENT) ? peer : NULL;
1b678347 1605}
2bd24a1c 1606
5bfb151f
JR
1607static inline void *ide_get_drivedata(ide_drive_t *drive)
1608{
1609 return drive->drive_data;
1610}
1611
1612static inline void ide_set_drivedata(ide_drive_t *drive, void *data)
1613{
1614 drive->drive_data = data;
1615}
1616
2bd24a1c
BZ
1617#define ide_port_for_each_dev(i, dev, port) \
1618 for ((i) = 0; ((dev) = (port)->devices[i]) || (i) < MAX_DRIVES; (i)++)
1619
7ed5b157
BZ
1620#define ide_port_for_each_present_dev(i, dev, port) \
1621 for ((i) = 0; ((dev) = (port)->devices[i]) || (i) < MAX_DRIVES; (i)++) \
1622 if ((dev)->dev_flags & IDE_DFLAG_PRESENT)
1623
2bd24a1c
BZ
1624#define ide_host_for_each_port(i, port, host) \
1625 for ((i) = 0; ((port) = (host)->ports[i]) || (i) < MAX_HOST_PORTS; (i)++)
1626
b42171ef 1627
1da177e4 1628#endif /* _IDE_H */