[mirror_ubuntu-bionic-kernel.git] / include / linux / intel-iommu.h

/*
 * Copyright © 2006-2015, Intel Corporation.
 *
 * Authors: Ashok Raj <ashok.raj@intel.com>
 *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
 *          David Woodhouse <David.Woodhouse@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 */

#ifndef _INTEL_IOMMU_H_
#define _INTEL_IOMMU_H_

#include <linux/types.h>
#include <linux/iova.h>
#include <linux/io.h>
#include <linux/idr.h>
#include <linux/dma_remapping.h>
#include <linux/mmu_notifier.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/io-64-nonatomic-lo-hi.h>

#include <asm/cacheflush.h>
#include <asm/iommu.h>

/*
 * Intel IOMMU register specification per version 1.0 public spec.
 */

#define	DMAR_VER_REG	0x0	/* Arch version supported by this IOMMU */
#define	DMAR_CAP_REG	0x8	/* Hardware supported capabilities */
#define	DMAR_ECAP_REG	0x10	/* Extended capabilities supported */
#define	DMAR_GCMD_REG	0x18	/* Global command register */
#define	DMAR_GSTS_REG	0x1c	/* Global status register */
#define	DMAR_RTADDR_REG	0x20	/* Root entry table */
#define	DMAR_CCMD_REG	0x28	/* Context command reg */
#define	DMAR_FSTS_REG	0x34	/* Fault Status register */
#define	DMAR_FECTL_REG	0x38	/* Fault control register */
#define	DMAR_FEDATA_REG	0x3c	/* Fault event interrupt data register */
#define	DMAR_FEADDR_REG	0x40	/* Fault event interrupt addr register */
#define	DMAR_FEUADDR_REG 0x44	/* Upper address register */
#define	DMAR_AFLOG_REG	0x58	/* Advanced Fault control */
#define	DMAR_PMEN_REG	0x64	/* Enable Protected Memory Region */
#define	DMAR_PLMBASE_REG 0x68	/* PMRR Low addr */
#define	DMAR_PLMLIMIT_REG 0x6c	/* PMRR low limit */
#define	DMAR_PHMBASE_REG 0x70	/* pmrr high base addr */
#define	DMAR_PHMLIMIT_REG 0x78	/* pmrr high limit */
#define DMAR_IQH_REG	0x80	/* Invalidation queue head register */
#define DMAR_IQT_REG	0x88	/* Invalidation queue tail register */
#define DMAR_IQ_SHIFT	4	/* Invalidation queue head/tail shift */
#define DMAR_IQA_REG	0x90	/* Invalidation queue addr register */
#define DMAR_ICS_REG	0x9c	/* Invalidation complete status register */
#define DMAR_IRTA_REG	0xb8    /* Interrupt remapping table addr register */
#define DMAR_PQH_REG	0xc0	/* Page request queue head register */
#define DMAR_PQT_REG	0xc8	/* Page request queue tail register */
#define DMAR_PQA_REG	0xd0	/* Page request queue address register */
#define DMAR_PRS_REG	0xdc	/* Page request status register */
#define DMAR_PECTL_REG	0xe0	/* Page request event control register */
#define	DMAR_PEDATA_REG	0xe4	/* Page request event interrupt data register */
#define	DMAR_PEADDR_REG	0xe8	/* Page request event interrupt addr register */
#define	DMAR_PEUADDR_REG 0xec	/* Page request event Upper address register */

#define OFFSET_STRIDE		(9)

#define dmar_readq(a) readq(a)
#define dmar_writeq(a,v) writeq(v,a)

#define DMAR_VER_MAJOR(v)		(((v) & 0xf0) >> 4)
#define DMAR_VER_MINOR(v)		((v) & 0x0f)

/*
 * Decoding Capability Register
 */
#define cap_pi_support(c)	(((c) >> 59) & 1)
#define cap_read_drain(c)	(((c) >> 55) & 1)
#define cap_write_drain(c)	(((c) >> 54) & 1)
#define cap_max_amask_val(c)	(((c) >> 48) & 0x3f)
#define cap_num_fault_regs(c)	((((c) >> 40) & 0xff) + 1)
#define cap_pgsel_inv(c)	(((c) >> 39) & 1)

#define cap_super_page_val(c)	(((c) >> 34) & 0xf)
#define cap_super_offset(c)	(((find_first_bit(&cap_super_page_val(c), 4)) \
					* OFFSET_STRIDE) + 21)

#define cap_fault_reg_offset(c)	((((c) >> 24) & 0x3ff) * 16)
#define cap_max_fault_reg_offset(c) \
	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)

#define cap_zlr(c)		(((c) >> 22) & 1)
#define cap_isoch(c)		(((c) >> 23) & 1)
#define cap_mgaw(c)		((((c) >> 16) & 0x3f) + 1)
#define cap_sagaw(c)		(((c) >> 8) & 0x1f)
#define cap_caching_mode(c)	(((c) >> 7) & 1)
#define cap_phmr(c)		(((c) >> 6) & 1)
#define cap_plmr(c)		(((c) >> 5) & 1)
#define cap_rwbf(c)		(((c) >> 4) & 1)
#define cap_afl(c)		(((c) >> 3) & 1)
#define cap_ndoms(c)		(((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
/*
 * Extended Capability Register
 */

#define ecap_pasid(e)		((e >> 40) & 0x1)
#define ecap_pss(e)		((e >> 35) & 0x1f)
#define ecap_eafs(e)		((e >> 34) & 0x1)
#define ecap_nwfs(e)		((e >> 33) & 0x1)
#define ecap_srs(e)		((e >> 31) & 0x1)
#define ecap_ers(e)		((e >> 30) & 0x1)
#define ecap_prs(e)		((e >> 29) & 0x1)
#define ecap_broken_pasid(e)	((e >> 28) & 0x1)
#define ecap_dis(e)		((e >> 27) & 0x1)
#define ecap_nest(e)		((e >> 26) & 0x1)
#define ecap_mts(e)		((e >> 25) & 0x1)
#define ecap_ecs(e)		((e >> 24) & 0x1)
#define ecap_iotlb_offset(e) 	((((e) >> 8) & 0x3ff) * 16)
#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
#define ecap_coherent(e)	((e) & 0x1)
#define ecap_qis(e)		((e) & 0x2)
#define ecap_pass_through(e)	((e >> 6) & 0x1)
#define ecap_eim_support(e)	((e >> 4) & 0x1)
#define ecap_ir_support(e)	((e >> 3) & 0x1)
#define ecap_dev_iotlb_support(e)	(((e) >> 2) & 0x1)
#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
#define ecap_sc_support(e)	((e >> 7) & 0x1) /* Snooping Control */

/* IOTLB_REG */
#define DMA_TLB_FLUSH_GRANU_OFFSET  60
#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
#define DMA_TLB_DID(id)	(((u64)((id) & 0xffff)) << 32)
#define DMA_TLB_IVT (((u64)1) << 63)
#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
#define DMA_TLB_MAX_SIZE (0x3f)

/* INVALID_DESC */
#define DMA_CCMD_INVL_GRANU_OFFSET  61
#define DMA_ID_TLB_GLOBAL_FLUSH	(((u64)1) << 4)
#define DMA_ID_TLB_DSI_FLUSH	(((u64)2) << 4)
#define DMA_ID_TLB_PSI_FLUSH	(((u64)3) << 4)
#define DMA_ID_TLB_READ_DRAIN	(((u64)1) << 7)
#define DMA_ID_TLB_WRITE_DRAIN	(((u64)1) << 6)
#define DMA_ID_TLB_DID(id)	(((u64)((id & 0xffff) << 16)))
#define DMA_ID_TLB_IH_NONLEAF	(((u64)1) << 6)
#define DMA_ID_TLB_ADDR(addr)	(addr)
#define DMA_ID_TLB_ADDR_MASK(mask)	(mask)

/* PMEN_REG */
#define DMA_PMEN_EPM (((u32)1)<<31)
#define DMA_PMEN_PRS (((u32)1)<<0)

/* GCMD_REG */
#define DMA_GCMD_TE (((u32)1) << 31)
#define DMA_GCMD_SRTP (((u32)1) << 30)
#define DMA_GCMD_SFL (((u32)1) << 29)
#define DMA_GCMD_EAFL (((u32)1) << 28)
#define DMA_GCMD_WBF (((u32)1) << 27)
#define DMA_GCMD_QIE (((u32)1) << 26)
#define DMA_GCMD_SIRTP (((u32)1) << 24)
#define DMA_GCMD_IRE (((u32) 1) << 25)
#define DMA_GCMD_CFI (((u32) 1) << 23)

/* GSTS_REG */
#define DMA_GSTS_TES (((u32)1) << 31)
#define DMA_GSTS_RTPS (((u32)1) << 30)
#define DMA_GSTS_FLS (((u32)1) << 29)
#define DMA_GSTS_AFLS (((u32)1) << 28)
#define DMA_GSTS_WBFS (((u32)1) << 27)
#define DMA_GSTS_QIES (((u32)1) << 26)
#define DMA_GSTS_IRTPS (((u32)1) << 24)
#define DMA_GSTS_IRES (((u32)1) << 25)
#define DMA_GSTS_CFIS (((u32)1) << 23)

/* DMA_RTADDR_REG */
#define DMA_RTADDR_RTT (((u64)1) << 11)

/* CCMD_REG */
#define DMA_CCMD_ICC (((u64)1) << 63)
#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
#define DMA_CCMD_MASK_NOBIT 0
#define DMA_CCMD_MASK_1BIT 1
#define DMA_CCMD_MASK_2BIT 2
#define DMA_CCMD_MASK_3BIT 3
#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))

/* FECTL_REG */
#define DMA_FECTL_IM (((u32)1) << 31)

/* FSTS_REG */
#define DMA_FSTS_PPF ((u32)2)
#define DMA_FSTS_PFO ((u32)1)
#define DMA_FSTS_IQE (1 << 4)
#define DMA_FSTS_ICE (1 << 5)
#define DMA_FSTS_ITE (1 << 6)
#define DMA_FSTS_PRO (1 << 7)
#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)

/* FRCD_REG, 32 bits access */
#define DMA_FRCD_F (((u32)1) << 31)
#define dma_frcd_type(d) ((d >> 30) & 1)
#define dma_frcd_fault_reason(c) (c & 0xff)
#define dma_frcd_source_id(c) (c & 0xffff)
/* low 64 bit */
#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))

/* PRS_REG */
#define DMA_PRS_PPR	((u32)1)

#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)			\
do {									\
	cycles_t start_time = get_cycles();				\
	while (1) {							\
		sts = op(iommu->reg + offset);				\
		if (cond)						\
			break;						\
		if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
			panic("DMAR hardware is malfunctioning\n");	\
		cpu_relax();						\
	}								\
} while (0)

#define QI_LENGTH	256	/* queue length */

enum {
	QI_FREE,
	QI_IN_USE,
	QI_DONE,
	QI_ABORT
};

#define QI_CC_TYPE		0x1
#define QI_IOTLB_TYPE		0x2
#define QI_DIOTLB_TYPE		0x3
#define QI_IEC_TYPE		0x4
#define QI_IWD_TYPE		0x5
#define QI_EIOTLB_TYPE		0x6
#define QI_PC_TYPE		0x7
#define QI_DEIOTLB_TYPE		0x8
#define QI_PGRP_RESP_TYPE	0x9
#define QI_PSTRM_RESP_TYPE	0xa

#define QI_IEC_SELECTIVE	(((u64)1) << 4)
#define QI_IEC_IIDEX(idx)	(((u64)(idx & 0xffff) << 32))
#define QI_IEC_IM(m)		(((u64)(m & 0x1f) << 27))

#define QI_IWD_STATUS_DATA(d)	(((u64)d) << 32)
#define QI_IWD_STATUS_WRITE	(((u64)1) << 5)

#define QI_IOTLB_DID(did) 	(((u64)did) << 16)
#define QI_IOTLB_DR(dr) 	(((u64)dr) << 7)
#define QI_IOTLB_DW(dw) 	(((u64)dw) << 6)
#define QI_IOTLB_GRAN(gran) 	(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
#define QI_IOTLB_ADDR(addr)	(((u64)addr) & VTD_PAGE_MASK)
#define QI_IOTLB_IH(ih)		(((u64)ih) << 6)
#define QI_IOTLB_AM(am)		(((u8)am))

#define QI_CC_FM(fm)		(((u64)fm) << 48)
#define QI_CC_SID(sid)		(((u64)sid) << 32)
#define QI_CC_DID(did)		(((u64)did) << 16)
#define QI_CC_GRAN(gran)	(((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))

#define QI_DEV_IOTLB_SID(sid)	((u64)((sid) & 0xffff) << 32)
#define QI_DEV_IOTLB_QDEP(qdep)	(((qdep) & 0x1f) << 16)
#define QI_DEV_IOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)
#define QI_DEV_IOTLB_SIZE	1
#define QI_DEV_IOTLB_MAX_INVS	32

#define QI_PC_PASID(pasid)	(((u64)pasid) << 32)
#define QI_PC_DID(did)		(((u64)did) << 16)
#define QI_PC_GRAN(gran)	(((u64)gran) << 4)

#define QI_PC_ALL_PASIDS	(QI_PC_TYPE | QI_PC_GRAN(0))
#define QI_PC_PASID_SEL		(QI_PC_TYPE | QI_PC_GRAN(1))

#define QI_EIOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)
#define QI_EIOTLB_GL(gl)	(((u64)gl) << 7)
#define QI_EIOTLB_IH(ih)	(((u64)ih) << 6)
#define QI_EIOTLB_AM(am)	(((u64)am))
#define QI_EIOTLB_PASID(pasid) 	(((u64)pasid) << 32)
#define QI_EIOTLB_DID(did)	(((u64)did) << 16)
#define QI_EIOTLB_GRAN(gran) 	(((u64)gran) << 4)

#define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)
#define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)
#define QI_DEV_EIOTLB_GLOB(g)	((u64)g)
#define QI_DEV_EIOTLB_PASID(p)	(((u64)p) << 32)
#define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)
#define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
#define QI_DEV_EIOTLB_MAX_INVS	32

#define QI_PGRP_IDX(idx)	(((u64)(idx)) << 55)
#define QI_PGRP_PRIV(priv)	(((u64)(priv)) << 32)
#define QI_PGRP_RESP_CODE(res)	((u64)(res))
#define QI_PGRP_PASID(pasid)	(((u64)(pasid)) << 32)
#define QI_PGRP_DID(did)	(((u64)(did)) << 16)
#define QI_PGRP_PASID_P(p)	(((u64)(p)) << 4)

#define QI_PSTRM_ADDR(addr)	(((u64)(addr)) & VTD_PAGE_MASK)
#define QI_PSTRM_DEVFN(devfn)	(((u64)(devfn)) << 4)
#define QI_PSTRM_RESP_CODE(res)	((u64)(res))
#define QI_PSTRM_IDX(idx)	(((u64)(idx)) << 55)
#define QI_PSTRM_PRIV(priv)	(((u64)(priv)) << 32)
#define QI_PSTRM_BUS(bus)	(((u64)(bus)) << 24)
#define QI_PSTRM_PASID(pasid)	(((u64)(pasid)) << 4)

#define QI_RESP_SUCCESS		0x0
#define QI_RESP_INVALID		0x1
#define QI_RESP_FAILURE		0xf

#define QI_GRAN_ALL_ALL			0
#define QI_GRAN_NONG_ALL		1
#define QI_GRAN_NONG_PASID		2
#define QI_GRAN_PSI_PASID		3

struct qi_desc {
	u64 low, high;
};

struct q_inval {
	raw_spinlock_t  q_lock;
	struct qi_desc  *desc;          /* invalidation queue */
	int             *desc_status;   /* desc status */
	int             free_head;      /* first free entry */
	int             free_tail;      /* last free entry */
	int             free_cnt;
};

#ifdef CONFIG_IRQ_REMAP
/* 1MB - maximum possible interrupt remapping table size */
#define INTR_REMAP_PAGE_ORDER	8
#define INTR_REMAP_TABLE_REG_SIZE	0xf
#define INTR_REMAP_TABLE_REG_SIZE_MASK  0xf

#define INTR_REMAP_TABLE_ENTRIES	65536

struct irq_domain;

struct ir_table {
	struct irte *base;
	unsigned long *bitmap;
};
#endif

struct iommu_flush {
	void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
			      u8 fm, u64 type);
	void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
			    unsigned int size_order, u64 type);
};

enum {
	SR_DMAR_FECTL_REG,
	SR_DMAR_FEDATA_REG,
	SR_DMAR_FEADDR_REG,
	SR_DMAR_FEUADDR_REG,
	MAX_SR_DMAR_REGS
};

#define VTD_FLAG_TRANS_PRE_ENABLED	(1 << 0)
#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED	(1 << 1)

struct pasid_entry;
struct pasid_state_entry;
struct page_req_dsc;

struct intel_iommu {
	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
	u64 		reg_phys; /* physical address of hw register set */
	u64		reg_size; /* size of hw register set */
	u64		cap;
	u64		ecap;
	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
	raw_spinlock_t	register_lock; /* protect register handling */
	int		seq_id;	/* sequence id of the iommu */
	int		agaw; /* agaw of this iommu */
	int		msagaw; /* max sagaw of this iommu */
	unsigned int 	irq, pr_irq;
	u16		segment;     /* PCI segment# */
	unsigned char 	name[13];    /* Device Name */

#ifdef CONFIG_INTEL_IOMMU
	unsigned long 	*domain_ids; /* bitmap of domains */
	struct dmar_domain ***domains; /* ptr to domains */
	spinlock_t	lock; /* protect context, domain ids */
	struct root_entry *root_entry; /* virtual address */

	struct iommu_flush flush;
#endif
#ifdef CONFIG_INTEL_IOMMU_SVM
	/* These are large and need to be contiguous, so we allocate just
	 * one for now. We'll maybe want to rethink that if we truly give
	 * devices away to userspace processes (e.g. for DPDK) and don't
	 * want to trust that userspace will use *only* the PASID it was
	 * told to. But while it's all driver-arbitrated, we're fine. */
	struct pasid_entry *pasid_table;
	struct pasid_state_entry *pasid_state_table;
	struct page_req_dsc *prq;
	unsigned char prq_name[16];    /* Name for PRQ interrupt */
	struct idr pasid_idr;
	u32 pasid_max;
#endif
	struct q_inval  *qi;            /* Queued invalidation info */
	u32 *iommu_state; /* Store iommu states between suspend and resume.*/

#ifdef CONFIG_IRQ_REMAP
	struct ir_table *ir_table;	/* Interrupt remapping info */
	struct irq_domain *ir_domain;
	struct irq_domain *ir_msi_domain;
#endif
	struct iommu_device iommu;  /* IOMMU core code handle */
	int		node;
	u32		flags;      /* Software defined flags */
};

static inline void __iommu_flush_cache(
	struct intel_iommu *iommu, void *addr, int size)
{
	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(addr, size);
}

extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);

extern int dmar_enable_qi(struct intel_iommu *iommu);
extern void dmar_disable_qi(struct intel_iommu *iommu);
extern int dmar_reenable_qi(struct intel_iommu *iommu);
extern void qi_global_iec(struct intel_iommu *iommu);

extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
			     u8 fm, u64 type);
extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
			  unsigned int size_order, u64 type);
extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
			       u64 addr, unsigned mask);

extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);

extern int dmar_ir_support(void);

#ifdef CONFIG_INTEL_IOMMU_SVM
extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
extern int intel_svm_enable_prq(struct intel_iommu *iommu);
extern int intel_svm_finish_prq(struct intel_iommu *iommu);

struct svm_dev_ops;

struct intel_svm_dev {
	struct list_head list;
	struct rcu_head rcu;
	struct device *dev;
	struct svm_dev_ops *ops;
	int users;
	u16 did;
	u16 dev_iotlb:1;
	u16 sid, qdep;
};

struct intel_svm {
	struct mmu_notifier notifier;
	struct mm_struct *mm;
	struct intel_iommu *iommu;
	int flags;
	int pasid;
	struct list_head devs;
};

extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
#endif

extern const struct attribute_group *intel_iommu_groups[];

#endif
Commit	Line	Data
ba395927	1	/*
2f26e0a9 DW	2	* Copyright © 2006-2015, Intel Corporation.
	3	*
	4	* Authors: Ashok Raj <ashok.raj@intel.com>
	5	* Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
	6	* David Woodhouse <David.Woodhouse@intel.com>
ba395927 KA	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	19	* Place - Suite 330, Boston, MA 02111-1307 USA.
ba395927 KA	20	*/
	21
	22	#ifndef _INTEL_IOMMU_H_
	23	#define _INTEL_IOMMU_H_
	24
	25	#include <linux/types.h>
38717946	26	#include <linux/iova.h>
ba395927	27	#include <linux/io.h>
2f26e0a9	28	#include <linux/idr.h>
38717946	29	#include <linux/dma_remapping.h>
2f26e0a9 DW	30	#include <linux/mmu_notifier.h>
2f26e0a9 DW	31	#include <linux/list.h>
b0119e87	32	#include <linux/iommu.h>
61012985 AS	33	#include <linux/io-64-nonatomic-lo-hi.h>
61012985 AS	34
fe962e90	35	#include <asm/cacheflush.h>
5b6985ce	36	#include <asm/iommu.h>
f661197e	37
ba395927 KA	38	/*
	39	* Intel IOMMU register specification per version 1.0 public spec.
	40	*/
	41
	42	#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
	43	#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
	44	#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
	45	#define DMAR_GCMD_REG 0x18 /* Global command register */
	46	#define DMAR_GSTS_REG 0x1c /* Global status register */
	47	#define DMAR_RTADDR_REG 0x20 /* Root entry table */
	48	#define DMAR_CCMD_REG 0x28 /* Context command reg */
	49	#define DMAR_FSTS_REG 0x34 /* Fault Status register */
	50	#define DMAR_FECTL_REG 0x38 /* Fault control register */
	51	#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
	52	#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
	53	#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
	54	#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
	55	#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
	56	#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
	57	#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
	58	#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
	59	#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
fe962e90 SS	60	#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
fe962e90 SS	61	#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
6ba6c3a4	62	#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
fe962e90	63	#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
82aeef0b	64	#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
2ae21010	65	#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
1208225c DW	66	#define DMAR_PQH_REG 0xc0 /* Page request queue head register */
	67	#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
	68	#define DMAR_PQA_REG 0xd0 /* Page request queue address register */
	69	#define DMAR_PRS_REG 0xdc /* Page request status register */
	70	#define DMAR_PECTL_REG 0xe0 /* Page request event control register */
	71	#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
	72	#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
	73	#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
ba395927 KA	74
ba395927 KA	75	#define OFFSET_STRIDE (9)
50d3fb56	76
50d3fb56 DW	77	#define dmar_readq(a) readq(a)
50d3fb56 DW	78	#define dmar_writeq(a,v) writeq(v,a)
ba395927 KA	79
	80	#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
	81	#define DMAR_VER_MINOR(v) ((v) & 0x0f)
	82
	83	/*
	84	* Decoding Capability Register
	85	*/
07c09787	86	#define cap_pi_support(c) (((c) >> 59) & 1)
ba395927 KA	87	#define cap_read_drain(c) (((c) >> 55) & 1)
	88	#define cap_write_drain(c) (((c) >> 54) & 1)
	89	#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
	90	#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
	91	#define cap_pgsel_inv(c) (((c) >> 39) & 1)
	92
	93	#define cap_super_page_val(c) (((c) >> 34) & 0xf)
	94	#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
	95	* OFFSET_STRIDE) + 21)
	96
	97	#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
	98	#define cap_max_fault_reg_offset(c) \
	99	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
	100
	101	#define cap_zlr(c) (((c) >> 22) & 1)
	102	#define cap_isoch(c) (((c) >> 23) & 1)
	103	#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
	104	#define cap_sagaw(c) (((c) >> 8) & 0x1f)
	105	#define cap_caching_mode(c) (((c) >> 7) & 1)
	106	#define cap_phmr(c) (((c) >> 6) & 1)
	107	#define cap_plmr(c) (((c) >> 5) & 1)
	108	#define cap_rwbf(c) (((c) >> 4) & 1)
	109	#define cap_afl(c) (((c) >> 3) & 1)
	110	#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
	111	/*
	112	* Extended Capability Register
	113	*/
	114
bd00c606	115	#define ecap_pasid(e) ((e >> 40) & 0x1)
4423f5e7 DW	116	#define ecap_pss(e) ((e >> 35) & 0x1f)
	117	#define ecap_eafs(e) ((e >> 34) & 0x1)
	118	#define ecap_nwfs(e) ((e >> 33) & 0x1)
	119	#define ecap_srs(e) ((e >> 31) & 0x1)
	120	#define ecap_ers(e) ((e >> 30) & 0x1)
	121	#define ecap_prs(e) ((e >> 29) & 0x1)
ae853ddb	122	#define ecap_broken_pasid(e) ((e >> 28) & 0x1)
4423f5e7 DW	123	#define ecap_dis(e) ((e >> 27) & 0x1)
	124	#define ecap_nest(e) ((e >> 26) & 0x1)
	125	#define ecap_mts(e) ((e >> 25) & 0x1)
	126	#define ecap_ecs(e) ((e >> 24) & 0x1)
ba395927	127	#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
44caf2f3	128	#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
ba395927	129	#define ecap_coherent(e) ((e) & 0x1)
fe962e90	130	#define ecap_qis(e) ((e) & 0x2)
4ed0d3e6	131	#define ecap_pass_through(e) ((e >> 6) & 0x1)
ad3ad3f6 SS	132	#define ecap_eim_support(e) ((e >> 4) & 0x1)
ad3ad3f6 SS	133	#define ecap_ir_support(e) ((e >> 3) & 0x1)
93a23a72	134	#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
b6fcb33a	135	#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
58c610bd	136	#define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
ba395927 KA	137
ba395927 KA	138	/* IOTLB_REG */
3481f210	139	#define DMA_TLB_FLUSH_GRANU_OFFSET 60
ba395927 KA	140	#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
	141	#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
	142	#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
aaa59306 CT	143	#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
aaa59306 CT	144	#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
ba395927 KA	145	#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
	146	#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
	147	#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
	148	#define DMA_TLB_IVT (((u64)1) << 63)
	149	#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
	150	#define DMA_TLB_MAX_SIZE (0x3f)
	151
fe962e90	152	/* INVALID_DESC */
3481f210	153	#define DMA_CCMD_INVL_GRANU_OFFSET 61
aaa59306 CT	154	#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
	155	#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
	156	#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
fe962e90 SS	157	#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
	158	#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
	159	#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
	160	#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
	161	#define DMA_ID_TLB_ADDR(addr) (addr)
	162	#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
	163
f8bab735	164	/* PMEN_REG */
	165	#define DMA_PMEN_EPM (((u32)1)<<31)
	166	#define DMA_PMEN_PRS (((u32)1)<<0)
	167
ba395927 KA	168	/* GCMD_REG */
	169	#define DMA_GCMD_TE (((u32)1) << 31)
	170	#define DMA_GCMD_SRTP (((u32)1) << 30)
	171	#define DMA_GCMD_SFL (((u32)1) << 29)
	172	#define DMA_GCMD_EAFL (((u32)1) << 28)
	173	#define DMA_GCMD_WBF (((u32)1) << 27)
2ae21010 SS	174	#define DMA_GCMD_QIE (((u32)1) << 26)
	175	#define DMA_GCMD_SIRTP (((u32)1) << 24)
	176	#define DMA_GCMD_IRE (((u32) 1) << 25)
161fde08	177	#define DMA_GCMD_CFI (((u32) 1) << 23)
ba395927 KA	178
	179	/* GSTS_REG */
	180	#define DMA_GSTS_TES (((u32)1) << 31)
	181	#define DMA_GSTS_RTPS (((u32)1) << 30)
	182	#define DMA_GSTS_FLS (((u32)1) << 29)
	183	#define DMA_GSTS_AFLS (((u32)1) << 28)
	184	#define DMA_GSTS_WBFS (((u32)1) << 27)
2ae21010 SS	185	#define DMA_GSTS_QIES (((u32)1) << 26)
	186	#define DMA_GSTS_IRTPS (((u32)1) << 24)
	187	#define DMA_GSTS_IRES (((u32)1) << 25)
161fde08	188	#define DMA_GSTS_CFIS (((u32)1) << 23)
ba395927	189
4423f5e7 DW	190	/* DMA_RTADDR_REG */
	191	#define DMA_RTADDR_RTT (((u64)1) << 11)
	192
ba395927 KA	193	/* CCMD_REG */
	194	#define DMA_CCMD_ICC (((u64)1) << 63)
	195	#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
	196	#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
	197	#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
	198	#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
	199	#define DMA_CCMD_MASK_NOBIT 0
	200	#define DMA_CCMD_MASK_1BIT 1
	201	#define DMA_CCMD_MASK_2BIT 2
	202	#define DMA_CCMD_MASK_3BIT 3
	203	#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
	204	#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
	205
	206	/* FECTL_REG */
	207	#define DMA_FECTL_IM (((u32)1) << 31)
	208
	209	/* FSTS_REG */
	210	#define DMA_FSTS_PPF ((u32)2)
	211	#define DMA_FSTS_PFO ((u32)1)
704126ad	212	#define DMA_FSTS_IQE (1 << 4)
6ba6c3a4 YZ	213	#define DMA_FSTS_ICE (1 << 5)
6ba6c3a4 YZ	214	#define DMA_FSTS_ITE (1 << 6)
973b5464	215	#define DMA_FSTS_PRO (1 << 7)
ba395927 KA	216	#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
	217
	218	/* FRCD_REG, 32 bits access */
	219	#define DMA_FRCD_F (((u32)1) << 31)
	220	#define dma_frcd_type(d) ((d >> 30) & 1)
	221	#define dma_frcd_fault_reason(c) (c & 0xff)
	222	#define dma_frcd_source_id(c) (c & 0xffff)
5b6985ce FY	223	/* low 64 bit */
	224	#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
	225
46924008 DW	226	/* PRS_REG */
	227	#define DMA_PRS_PPR ((u32)1)
	228
5b6985ce FY	229	#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
	230	do { \
	231	cycles_t start_time = get_cycles(); \
	232	while (1) { \
	233	sts = op(iommu->reg + offset); \
	234	if (cond) \
	235	break; \
cf1337f0	236	if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
5b6985ce FY	237	panic("DMAR hardware is malfunctioning\n"); \
	238	cpu_relax(); \
	239	} \
	240	} while (0)
cf1337f0	241
fe962e90 SS	242	#define QI_LENGTH 256 /* queue length */
	243
	244	enum {
	245	QI_FREE,
	246	QI_IN_USE,
6ba6c3a4 YZ	247	QI_DONE,
6ba6c3a4 YZ	248	QI_ABORT
fe962e90 SS	249	};
	250
	251	#define QI_CC_TYPE 0x1
	252	#define QI_IOTLB_TYPE 0x2
	253	#define QI_DIOTLB_TYPE 0x3
	254	#define QI_IEC_TYPE 0x4
	255	#define QI_IWD_TYPE 0x5
2f26e0a9 DW	256	#define QI_EIOTLB_TYPE 0x6
	257	#define QI_PC_TYPE 0x7
	258	#define QI_DEIOTLB_TYPE 0x8
a222a7f0 DW	259	#define QI_PGRP_RESP_TYPE 0x9
a222a7f0 DW	260	#define QI_PSTRM_RESP_TYPE 0xa
fe962e90 SS	261
	262	#define QI_IEC_SELECTIVE (((u64)1) << 4)
	263	#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
	264	#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
	265
	266	#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
	267	#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
	268
3481f210 YS	269	#define QI_IOTLB_DID(did) (((u64)did) << 16)
	270	#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
	271	#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
	272	#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
5b6985ce	273	#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
3481f210 YS	274	#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
	275	#define QI_IOTLB_AM(am) (((u8)am))
	276
	277	#define QI_CC_FM(fm) (((u64)fm) << 48)
	278	#define QI_CC_SID(sid) (((u64)sid) << 32)
	279	#define QI_CC_DID(did) (((u64)did) << 16)
	280	#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
	281
6ba6c3a4 YZ	282	#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
	283	#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
	284	#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
	285	#define QI_DEV_IOTLB_SIZE 1
	286	#define QI_DEV_IOTLB_MAX_INVS 32
	287
2f26e0a9 DW	288	#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
	289	#define QI_PC_DID(did) (((u64)did) << 16)
	290	#define QI_PC_GRAN(gran) (((u64)gran) << 4)
	291
	292	#define QI_PC_ALL_PASIDS (QI_PC_TYPE \| QI_PC_GRAN(0))
	293	#define QI_PC_PASID_SEL (QI_PC_TYPE \| QI_PC_GRAN(1))
	294
	295	#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
	296	#define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
	297	#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
	298	#define QI_EIOTLB_AM(am) (((u64)am))
	299	#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
	300	#define QI_EIOTLB_DID(did) (((u64)did) << 16)
	301	#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
	302
	303	#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
	304	#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
	305	#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
	306	#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
aaa59306 CT	307	#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
aaa59306 CT	308	#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
2f26e0a9 DW	309	#define QI_DEV_EIOTLB_MAX_INVS 32
2f26e0a9 DW	310
a222a7f0 DW	311	#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
	312	#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
	313	#define QI_PGRP_RESP_CODE(res) ((u64)(res))
	314	#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
	315	#define QI_PGRP_DID(did) (((u64)(did)) << 16)
	316	#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
	317
	318	#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
	319	#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
	320	#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
	321	#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
	322	#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
	323	#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
	324	#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
	325
	326	#define QI_RESP_SUCCESS 0x0
	327	#define QI_RESP_INVALID 0x1
	328	#define QI_RESP_FAILURE 0xf
	329
2f26e0a9 DW	330	#define QI_GRAN_ALL_ALL 0
	331	#define QI_GRAN_NONG_ALL 1
	332	#define QI_GRAN_NONG_PASID 2
	333	#define QI_GRAN_PSI_PASID 3
	334
fe962e90 SS	335	struct qi_desc {
	336	u64 low, high;
	337	};
	338
	339	struct q_inval {
3b8f4048	340	raw_spinlock_t q_lock;
fe962e90 SS	341	struct qi_desc desc; / invalidation queue */
	342	int desc_status; / desc status */
	343	int free_head; /* first free entry */
	344	int free_tail; /* last free entry */
	345	int free_cnt;
	346	};
	347
d3f13810	348	#ifdef CONFIG_IRQ_REMAP
2ae21010 SS	349	/* 1MB - maximum possible interrupt remapping table size */
	350	#define INTR_REMAP_PAGE_ORDER 8
	351	#define INTR_REMAP_TABLE_REG_SIZE 0xf
af3b358e	352	#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
2ae21010	353
b6fcb33a SS	354	#define INTR_REMAP_TABLE_ENTRIES 65536
b6fcb33a SS	355
b106ee63 JL	356	struct irq_domain;
b106ee63 JL	357
2ae21010 SS	358	struct ir_table {
2ae21010 SS	359	struct irte *base;
360eb3c5	360	unsigned long *bitmap;
2ae21010 SS	361	};
	362	#endif
	363
a77b67d4	364	struct iommu_flush {
4c25a2c1 DW	365	void (flush_context)(struct intel_iommu iommu, u16 did, u16 sid,
4c25a2c1 DW	366	u8 fm, u64 type);
1f0ef2aa DW	367	void (flush_iotlb)(struct intel_iommu iommu, u16 did, u64 addr,
1f0ef2aa DW	368	unsigned int size_order, u64 type);
a77b67d4 YS	369	};
a77b67d4 YS	370
f59c7b69 FY	371	enum {
	372	SR_DMAR_FECTL_REG,
	373	SR_DMAR_FEDATA_REG,
	374	SR_DMAR_FEADDR_REG,
	375	SR_DMAR_FEUADDR_REG,
	376	MAX_SR_DMAR_REGS
	377	};
	378
4158c2ec JR	379	#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
	380	#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
	381
8a94ade4 DW	382	struct pasid_entry;
8a94ade4 DW	383	struct pasid_state_entry;
a222a7f0	384	struct page_req_dsc;
8a94ade4	385
ba395927 KA	386	struct intel_iommu {
ba395927 KA	387	void __iomem reg; / Pointer to hardware regs, virtual addr */
6f5cf521 DD	388	u64 reg_phys; /* physical address of hw register set */
6f5cf521 DD	389	u64 reg_size; /* size of hw register set */
ba395927 KA	390	u64 cap;
ba395927 KA	391	u64 ecap;
ba395927	392	u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
1f5b3c3f	393	raw_spinlock_t register_lock; /* protect register handling */
c42d9f32	394	int seq_id; /* sequence id of the iommu */
1b573683	395	int agaw; /* agaw of this iommu */
4ed0d3e6	396	int msagaw; /* max sagaw of this iommu */
1208225c	397	unsigned int irq, pr_irq;
67ccac41	398	u16 segment; /* PCI segment# */
9d783ba0	399	unsigned char name[13]; /* Device Name */
e61d98d8	400
d3f13810	401	#ifdef CONFIG_INTEL_IOMMU
e61d98d8	402	unsigned long domain_ids; / bitmap of domains */
8bf47816	403	struct dmar_domain **domains; / ptr to domains */
e61d98d8	404	spinlock_t lock; /* protect context, domain ids */
ba395927 KA	405	struct root_entry root_entry; / virtual address */
ba395927 KA	406
a77b67d4	407	struct iommu_flush flush;
8a94ade4 DW	408	#endif
	409	#ifdef CONFIG_INTEL_IOMMU_SVM
	410	/* These are large and need to be contiguous, so we allocate just
	411	* one for now. We'll maybe want to rethink that if we truly give
	412	* devices away to userspace processes (e.g. for DPDK) and don't
	413	* want to trust that userspace will use only the PASID it was
	414	* told to. But while it's all driver-arbitrated, we're fine. */
	415	struct pasid_entry *pasid_table;
	416	struct pasid_state_entry *pasid_state_table;
a222a7f0 DW	417	struct page_req_dsc *prq;
a222a7f0 DW	418	unsigned char prq_name[16]; /* Name for PRQ interrupt */
2f26e0a9	419	struct idr pasid_idr;
91017044	420	u32 pasid_max;
e61d98d8	421	#endif
fe962e90	422	struct q_inval qi; / Queued invalidation info */
f59c7b69 FY	423	u32 iommu_state; / Store iommu states between suspend and resume.*/
f59c7b69 FY	424
d3f13810	425	#ifdef CONFIG_IRQ_REMAP
2ae21010	426	struct ir_table ir_table; / Interrupt remapping info */
b106ee63 JL	427	struct irq_domain *ir_domain;
b106ee63 JL	428	struct irq_domain *ir_msi_domain;
2ae21010	429	#endif
b0119e87	430	struct iommu_device iommu; /* IOMMU core code handle */
ee34b32d	431	int node;
4158c2ec	432	u32 flags; /* Software defined flags */
ba395927 KA	433	};
ba395927 KA	434
fe962e90 SS	435	static inline void __iommu_flush_cache(
	436	struct intel_iommu iommu, void addr, int size)
	437	{
	438	if (!ecap_coherent(iommu->ecap))
	439	clflush_cache_range(addr, size);
	440	}
	441
e61d98d8	442	extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
aa5d2b51	443	extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
e61d98d8	444
2ae21010	445	extern int dmar_enable_qi(struct intel_iommu *iommu);
eba67e5d	446	extern void dmar_disable_qi(struct intel_iommu *iommu);
f59c7b69	447	extern int dmar_reenable_qi(struct intel_iommu *iommu);
2ae21010	448	extern void qi_global_iec(struct intel_iommu *iommu);
e820482c	449
4c25a2c1 DW	450	extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
4c25a2c1 DW	451	u8 fm, u64 type);
1f0ef2aa DW	452	extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1f0ef2aa DW	453	unsigned int size_order, u64 type);
6ba6c3a4 YZ	454	extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
6ba6c3a4 YZ	455	u64 addr, unsigned mask);
3481f210	456
704126ad	457	extern int qi_submit_sync(struct qi_desc desc, struct intel_iommu iommu);
38717946	458
074835f0 YS	459	extern int dmar_ir_support(void);
074835f0 YS	460
2f26e0a9	461	#ifdef CONFIG_INTEL_IOMMU_SVM
8a94ade4 DW	462	extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
8a94ade4 DW	463	extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
a222a7f0 DW	464	extern int intel_svm_enable_prq(struct intel_iommu *iommu);
a222a7f0 DW	465	extern int intel_svm_finish_prq(struct intel_iommu *iommu);
8a94ade4	466
0204a496 DW	467	struct svm_dev_ops;
0204a496 DW	468
2f26e0a9 DW	469	struct intel_svm_dev {
	470	struct list_head list;
	471	struct rcu_head rcu;
	472	struct device *dev;
0204a496	473	struct svm_dev_ops *ops;
2f26e0a9 DW	474	int users;
	475	u16 did;
	476	u16 dev_iotlb:1;
	477	u16 sid, qdep;
	478	};
	479
	480	struct intel_svm {
	481	struct mmu_notifier notifier;
	482	struct mm_struct *mm;
	483	struct intel_iommu *iommu;
569e4f77	484	int flags;
2f26e0a9 DW	485	int pasid;
	486	struct list_head devs;
	487	};
	488
	489	extern int intel_iommu_enable_pasid(struct intel_iommu iommu, struct intel_svm_dev sdev);
	490	extern struct intel_iommu intel_svm_device_to_iommu(struct device dev);
	491	#endif
	492
a5459cfe AW	493	extern const struct attribute_group *intel_iommu_groups[];
a5459cfe AW	494
ba395927	495	#endif