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CommitLineData
4a77a6cf
JR		 1/*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __LINUX_IOMMU_H
20#define __LINUX_IOMMU_H
21
e8245c1b
JR		 22#include <linux/scatterlist.h>
23#include <linux/device.h>
24#include <linux/types.h>
74315ccc 25#include <linux/errno.h>
9a08d376 26#include <linux/err.h>
d0f60a44 27#include <linux/of.h>
74315ccc 28
ca13bb3d
WD		 29#define IOMMU_READ (1 << 0)
30#define IOMMU_WRITE (1 << 1)
31#define IOMMU_CACHE (1 << 2) /* DMA cache coherency */
a720b41c 32#define IOMMU_NOEXEC (1 << 3)
31e6850e 33#define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */
579b2a65 34/*
adf5e516
RM		 35 * Where the bus hardware includes a privilege level as part of its access type
36 * markings, and certain devices are capable of issuing transactions marked as
37 * either 'supervisor' or 'user', the IOMMU_PRIV flag requests that the other
38 * given permission flags only apply to accesses at the higher privilege level,
39 * and that unprivileged transactions should have as little access as possible.
40 * This would usually imply the same permissions as kernel mappings on the CPU,
41 * if the IOMMU page table format is equivalent.
579b2a65
MH		 42 */
43#define IOMMU_PRIV (1 << 5)
4a77a6cf 44
905d66c1 45struct iommu_ops;
d72e31c9 46struct iommu_group;
ff21776d 47struct bus_type;
4a77a6cf 48struct device;
4f3f8d9d 49struct iommu_domain;
ba1eabfa 50struct notifier_block;
4f3f8d9d
OBC		 51
52/* iommu fault flags */
53#define IOMMU_FAULT_READ 0x0
54#define IOMMU_FAULT_WRITE 0x1
55
56typedef int (*iommu_fault_handler_t)(struct iommu_domain *,
77ca2332 57 struct device *, unsigned long, int, void *);
4a77a6cf 58
0ff64f80
JR		 59struct iommu_domain_geometry {
60 dma_addr_t aperture_start; /* First address that can be mapped */
61 dma_addr_t aperture_end; /* Last address that can be mapped */
62 bool force_aperture; /* DMA only allowed in mappable range? */
63};
64
8539c7c1
JR		 65/* Domain feature flags */
66#define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */
67#define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
68 implementation */
69#define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */
70
71/*
72 * This are the possible domain-types
73 *
74 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
75 * devices
76 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
77 * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used
78 * for VMs
79 * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations.
80 * This flag allows IOMMU drivers to implement
81 * certain optimizations for these domains
82 */
83#define IOMMU_DOMAIN_BLOCKED (0U)
84#define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT)
85#define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING)
86#define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \
87 __IOMMU_DOMAIN_DMA_API)
88
4a77a6cf 89struct iommu_domain {
8539c7c1 90 unsigned type;
b22f6434 91 const struct iommu_ops *ops;
d16e0faa 92 unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */
4f3f8d9d 93 iommu_fault_handler_t handler;
77ca2332 94 void *handler_token;
0ff64f80 95 struct iommu_domain_geometry geometry;
0db2e5d1 96 void *iova_cookie;
4a77a6cf
JR		 97};
98
1aed0748
JR		 99enum iommu_cap {
100 IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA
101 transactions */
102 IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */
c4986649 103 IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */
1aed0748 104};
dbb9fd86 105
7cabf491
VS		 106/*
107 * Following constraints are specifc to FSL_PAMUV1:
108 * -aperture must be power of 2, and naturally aligned
109 * -number of windows must be power of 2, and address space size
110 * of each window is determined by aperture size / # of windows
111 * -the actual size of the mapped region of a window must be power
112 * of 2 starting with 4KB and physical address must be naturally
113 * aligned.
114 * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints.
115 * The caller can invoke iommu_domain_get_attr to check if the underlying
116 * iommu implementation supports these constraints.
117 */
118
0cd76dd1 119enum iommu_attr {
0ff64f80 120 DOMAIN_ATTR_GEOMETRY,
d2e12160 121 DOMAIN_ATTR_PAGING,
69356712 122 DOMAIN_ATTR_WINDOWS,
7cabf491
VS		 123 DOMAIN_ATTR_FSL_PAMU_STASH,
124 DOMAIN_ATTR_FSL_PAMU_ENABLE,
125 DOMAIN_ATTR_FSL_PAMUV1,
c02607aa 126 DOMAIN_ATTR_NESTING, /* two stages of translation */
a8b8a88a 127 DOMAIN_ATTR_MAX,
0cd76dd1
JR		 128};
129
d30ddcaa 130/* These are the possible reserved region types */
9d3a4de4
RM		 131enum iommu_resv_type {
132 /* Memory regions which must be mapped 1:1 at all times */
133 IOMMU_RESV_DIRECT,
134 /* Arbitrary "never map this or give it to a device" address ranges */
135 IOMMU_RESV_RESERVED,
136 /* Hardware MSI region (untranslated) */
137 IOMMU_RESV_MSI,
138 /* Software-managed MSI translation window */
139 IOMMU_RESV_SW_MSI,
140};
d30ddcaa 141
a1015c2b 142/**
e5b5234a 143 * struct iommu_resv_region - descriptor for a reserved memory region
a1015c2b
JR		 144 * @list: Linked list pointers
145 * @start: System physical start address of the region
146 * @length: Length of the region in bytes
147 * @prot: IOMMU Protection flags (READ/WRITE/...)
d30ddcaa 148 * @type: Type of the reserved region
a1015c2b 149 */
e5b5234a 150struct iommu_resv_region {
a1015c2b
JR		 151 struct list_head list;
152 phys_addr_t start;
153 size_t length;
154 int prot;
9d3a4de4 155 enum iommu_resv_type type;
a1015c2b
JR		 156};
157
39d4ebb9
JR		 158#ifdef CONFIG_IOMMU_API
159
7d3002cc
OBC		 160/**
161 * struct iommu_ops - iommu ops and capabilities
0d9bacb6
MD		 162 * @capable: check capability
163 * @domain_alloc: allocate iommu domain
164 * @domain_free: free iommu domain
7d3002cc
OBC		 165 * @attach_dev: attach device to an iommu domain
166 * @detach_dev: detach device from an iommu domain
167 * @map: map a physically contiguous memory region to an iommu domain
168 * @unmap: unmap a physically contiguous memory region from an iommu domain
315786eb 169 * @map_sg: map a scatter-gather list of physically contiguous memory chunks
50ce6312 170 * to an iommu domain
add02cfd
JR		 171 * @flush_tlb_all: Synchronously flush all hardware TLBs for this domain
172 * @tlb_range_add: Add a given iova range to the flush queue for this domain
173 * @tlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
174 * queue
7d3002cc 175 * @iova_to_phys: translate iova to physical address
d72e31c9
AW		 176 * @add_device: add device to iommu grouping
177 * @remove_device: remove device from iommu grouping
0d9bacb6 178 * @device_group: find iommu group for a particular device
0cd76dd1
JR		 179 * @domain_get_attr: Query domain attributes
180 * @domain_set_attr: Change domain attributes
e5b5234a
EA		 181 * @get_resv_regions: Request list of reserved regions for a device
182 * @put_resv_regions: Free list of reserved regions for a device
183 * @apply_resv_region: Temporary helper call-back for iova reserved ranges
0d9bacb6
MD		 184 * @domain_window_enable: Configure and enable a particular window for a domain
185 * @domain_window_disable: Disable a particular window for a domain
186 * @domain_set_windows: Set the number of windows for a domain
187 * @domain_get_windows: Return the number of windows for a domain
d0f60a44 188 * @of_xlate: add OF master IDs to iommu grouping
d16e0faa 189 * @pgsize_bitmap: bitmap of all possible supported page sizes
7d3002cc 190 */
4a77a6cf 191struct iommu_ops {
3c0e0ca0 192 bool (*capable)(enum iommu_cap);
938c4709
JR		 193
194 /* Domain allocation and freeing by the iommu driver */
8539c7c1 195 struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type);
938c4709
JR		 196 void (*domain_free)(struct iommu_domain *);
197
4a77a6cf
JR		 198 int (*attach_dev)(struct iommu_domain *domain, struct device *dev);
199 void (*detach_dev)(struct iommu_domain *domain, struct device *dev);
67651786 200 int (*map)(struct iommu_domain *domain, unsigned long iova,
5009065d
OBC		 201 phys_addr_t paddr, size_t size, int prot);
202 size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
203 size_t size);
315786eb
OH		 204 size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova,
205 struct scatterlist *sg, unsigned int nents, int prot);
add02cfd
JR		 206 void (*flush_iotlb_all)(struct iommu_domain *domain);
207 void (*iotlb_range_add)(struct iommu_domain *domain,
208 unsigned long iova, size_t size);
209 void (*iotlb_sync)(struct iommu_domain *domain);
bb5547ac 210 phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova);
d72e31c9
AW		 211 int (*add_device)(struct device *dev);
212 void (*remove_device)(struct device *dev);
46c6b2bc 213 struct iommu_group *(*device_group)(struct device *dev);
0cd76dd1
JR		 214 int (*domain_get_attr)(struct iommu_domain *domain,
215 enum iommu_attr attr, void *data);
216 int (*domain_set_attr)(struct iommu_domain *domain,
217 enum iommu_attr attr, void *data);
d7787d57 218
e5b5234a
EA		 219 /* Request/Free a list of reserved regions for a device */
220 void (*get_resv_regions)(struct device *dev, struct list_head *list);
221 void (*put_resv_regions)(struct device *dev, struct list_head *list);
222 void (*apply_resv_region)(struct device *dev,
223 struct iommu_domain *domain,
224 struct iommu_resv_region *region);
a1015c2b 225
d7787d57
JR		 226 /* Window handling functions */
227 int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr,
80f97f0f 228 phys_addr_t paddr, u64 size, int prot);
d7787d57 229 void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr);
0d9bacb6 230 /* Set the number of windows per domain */
69356712 231 int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count);
0d9bacb6 232 /* Get the number of windows per domain */
69356712 233 u32 (*domain_get_windows)(struct iommu_domain *domain);
d7787d57 234
d0f60a44 235 int (*of_xlate)(struct device *dev, struct of_phandle_args *args);
e01d1913 236 bool (*is_attach_deferred)(struct iommu_domain *domain, struct device *dev);
d0f60a44 237
7d3002cc 238 unsigned long pgsize_bitmap;
4a77a6cf
JR		 239};
240
b0119e87
JR		 241/**
242 * struct iommu_device - IOMMU core representation of one IOMMU hardware
243 * instance
244 * @list: Used by the iommu-core to keep a list of registered iommus
245 * @ops: iommu-ops for talking to this iommu
39ab9555 246 * @dev: struct device for sysfs handling
b0119e87
JR		 247 */
248struct iommu_device {
249 struct list_head list;
250 const struct iommu_ops *ops;
c73e1ac8 251 struct fwnode_handle *fwnode;
2926a2aa 252 struct device *dev;
b0119e87
JR		 253};
254
255int iommu_device_register(struct iommu_device *iommu);
256void iommu_device_unregister(struct iommu_device *iommu);
39ab9555
JR		 257int iommu_device_sysfs_add(struct iommu_device *iommu,
258 struct device *parent,
259 const struct attribute_group **groups,
260 const char *fmt, ...) __printf(4, 5);
261void iommu_device_sysfs_remove(struct iommu_device *iommu);
e3d10af1
JR		 262int iommu_device_link(struct iommu_device *iommu, struct device *link);
263void iommu_device_unlink(struct iommu_device *iommu, struct device *link);
b0119e87
JR		 264
265static inline void iommu_device_set_ops(struct iommu_device *iommu,
266 const struct iommu_ops *ops)
267{
268 iommu->ops = ops;
269}
270
c73e1ac8
JR		 271static inline void iommu_device_set_fwnode(struct iommu_device *iommu,
272 struct fwnode_handle *fwnode)
273{
274 iommu->fwnode = fwnode;
275}
276
2926a2aa
JR		 277static inline struct iommu_device *dev_to_iommu_device(struct device *dev)
278{
279 return (struct iommu_device *)dev_get_drvdata(dev);
280}
281
d72e31c9
AW		 282#define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */
283#define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */
284#define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */
285#define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */
286#define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */
287#define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */
288
b22f6434 289extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops);
a1b60c1c 290extern bool iommu_present(struct bus_type *bus);
3c0e0ca0 291extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap);
905d66c1 292extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);
aa16bea9 293extern struct iommu_group *iommu_group_get_by_id(int id);
4a77a6cf
JR		 294extern void iommu_domain_free(struct iommu_domain *domain);
295extern int iommu_attach_device(struct iommu_domain *domain,
296 struct device *dev);
297extern void iommu_detach_device(struct iommu_domain *domain,
298 struct device *dev);
2c1296d9 299extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev);
cefc53c7 300extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
7d3002cc
OBC		 301 phys_addr_t paddr, size_t size, int prot);
302extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
add02cfd
JR		 303 size_t size);
304extern size_t iommu_unmap_fast(struct iommu_domain *domain,
305 unsigned long iova, size_t size);
315786eb
OH		 306extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
307 struct scatterlist *sg,unsigned int nents,
308 int prot);
bb5547ac 309extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
4f3f8d9d 310extern void iommu_set_fault_handler(struct iommu_domain *domain,
77ca2332 311 iommu_fault_handler_t handler, void *token);
d72e31c9 312
e5b5234a
EA		 313extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);
314extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);
d290f1e7 315extern int iommu_request_dm_for_dev(struct device *dev);
2b20cbba 316extern struct iommu_resv_region *
9d3a4de4
RM		 317iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot,
318 enum iommu_resv_type type);
6c65fb31
EA		 319extern int iommu_get_group_resv_regions(struct iommu_group *group,
320 struct list_head *head);
a1015c2b 321
d72e31c9
AW		 322extern int iommu_attach_group(struct iommu_domain *domain,
323 struct iommu_group *group);
324extern void iommu_detach_group(struct iommu_domain *domain,
325 struct iommu_group *group);
326extern struct iommu_group *iommu_group_alloc(void);
327extern void *iommu_group_get_iommudata(struct iommu_group *group);
328extern void iommu_group_set_iommudata(struct iommu_group *group,
329 void *iommu_data,
330 void (*release)(void *iommu_data));
331extern int iommu_group_set_name(struct iommu_group *group, const char *name);
332extern int iommu_group_add_device(struct iommu_group *group,
333 struct device *dev);
334extern void iommu_group_remove_device(struct device *dev);
335extern int iommu_group_for_each_dev(struct iommu_group *group, void *data,
336 int (*fn)(struct device *, void *));
337extern struct iommu_group *iommu_group_get(struct device *dev);
13f59a78 338extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);
d72e31c9
AW		 339extern void iommu_group_put(struct iommu_group *group);
340extern int iommu_group_register_notifier(struct iommu_group *group,
341 struct notifier_block *nb);
342extern int iommu_group_unregister_notifier(struct iommu_group *group,
343 struct notifier_block *nb);
344extern int iommu_group_id(struct iommu_group *group);
104a1c13 345extern struct iommu_group *iommu_group_get_for_dev(struct device *dev);
6827ca83 346extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *);
4f3f8d9d 347
0cd76dd1
JR		 348extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr,
349 void *data);
350extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr,
351 void *data);
4f3f8d9d 352
d7787d57
JR		 353/* Window handling function prototypes */
354extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,
80f97f0f
VS		 355 phys_addr_t offset, u64 size,
356 int prot);
d7787d57 357extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr);
207c6e36
JR		 358
359extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev,
360 unsigned long iova, int flags);
4a77a6cf 361
add02cfd
JR		 362static inline void iommu_flush_tlb_all(struct iommu_domain *domain)
363{
364 if (domain->ops->flush_iotlb_all)
365 domain->ops->flush_iotlb_all(domain);
366}
367
368static inline void iommu_tlb_range_add(struct iommu_domain *domain,
369 unsigned long iova, size_t size)
370{
371 if (domain->ops->iotlb_range_add)
372 domain->ops->iotlb_range_add(domain, iova, size);
373}
374
375static inline void iommu_tlb_sync(struct iommu_domain *domain)
376{
377 if (domain->ops->iotlb_sync)
378 domain->ops->iotlb_sync(domain);
379}
380
315786eb
OH		 381static inline size_t iommu_map_sg(struct iommu_domain *domain,
382 unsigned long iova, struct scatterlist *sg,
383 unsigned int nents, int prot)
384{
385 return domain->ops->map_sg(domain, iova, sg, nents, prot);
386}
387
5e62292b
JR		 388/* PCI device grouping function */
389extern struct iommu_group *pci_device_group(struct device *dev);
6eab556a
JR		 390/* Generic device grouping function */
391extern struct iommu_group *generic_device_group(struct device *dev);
5e62292b 392
57f98d2f
RM		 393/**
394 * struct iommu_fwspec - per-device IOMMU instance data
395 * @ops: ops for this device's IOMMU
396 * @iommu_fwnode: firmware handle for this device's IOMMU
397 * @iommu_priv: IOMMU driver private data for this device
398 * @num_ids: number of associated device IDs
399 * @ids: IDs which this device may present to the IOMMU
400 */
401struct iommu_fwspec {
402 const struct iommu_ops *ops;
403 struct fwnode_handle *iommu_fwnode;
404 void *iommu_priv;
405 unsigned int num_ids;
406 u32 ids[1];
407};
408
409int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,
410 const struct iommu_ops *ops);
411void iommu_fwspec_free(struct device *dev);
412int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids);
534766df 413const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode);
57f98d2f 414
4a77a6cf
JR		 415#else /* CONFIG_IOMMU_API */
416
39d4ebb9 417struct iommu_ops {};
d72e31c9 418struct iommu_group {};
57f98d2f 419struct iommu_fwspec {};
b0119e87 420struct iommu_device {};
4a77a6cf 421
a1b60c1c 422static inline bool iommu_present(struct bus_type *bus)
4a77a6cf
JR		 423{
424 return false;
425}
426
3c0e0ca0
JR		 427static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)
428{
429 return false;
430}
431
905d66c1 432static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus)
4a77a6cf
JR		 433{
434 return NULL;
435}
436
b62dfd29
AK		 437static inline struct iommu_group *iommu_group_get_by_id(int id)
438{
439 return NULL;
440}
441
4a77a6cf
JR		 442static inline void iommu_domain_free(struct iommu_domain *domain)
443{
444}
445
446static inline int iommu_attach_device(struct iommu_domain *domain,
447 struct device *dev)
448{
449 return -ENODEV;
450}
451
452static inline void iommu_detach_device(struct iommu_domain *domain,
453 struct device *dev)
454{
455}
456
2c1296d9
JR		 457static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev)
458{
459 return NULL;
460}
461
cefc53c7 462static inline int iommu_map(struct iommu_domain *domain, unsigned long iova,
ebae3e83 463 phys_addr_t paddr, size_t size, int prot)
cefc53c7
JR		 464{
465 return -ENODEV;
466}
467
468static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova,
ebae3e83 469 size_t size)
cefc53c7
JR		 470{
471 return -ENODEV;
472}
473
add02cfd
JR		 474static inline int iommu_unmap_fast(struct iommu_domain *domain, unsigned long iova,
475 int gfp_order)
cefc53c7
JR		 476{
477 return -ENODEV;
478}
479
315786eb
OH		 480static inline size_t iommu_map_sg(struct iommu_domain *domain,
481 unsigned long iova, struct scatterlist *sg,
482 unsigned int nents, int prot)
483{
484 return -ENODEV;
485}
486
add02cfd
JR		 487static inline void iommu_flush_tlb_all(struct iommu_domain *domain)
488{
489}
490
491static inline void iommu_tlb_range_add(struct iommu_domain *domain,
492 unsigned long iova, size_t size)
493{
494}
495
496static inline void iommu_tlb_sync(struct iommu_domain *domain)
497{
498}
499
d7787d57
JR		 500static inline int iommu_domain_window_enable(struct iommu_domain *domain,
501 u32 wnd_nr, phys_addr_t paddr,
80f97f0f 502 u64 size, int prot)
d7787d57
JR		 503{
504 return -ENODEV;
505}
506
507static inline void iommu_domain_window_disable(struct iommu_domain *domain,
508 u32 wnd_nr)
509{
510}
511
bb5547ac 512static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
4a77a6cf
JR		 513{
514 return 0;
515}
516
4f3f8d9d 517static inline void iommu_set_fault_handler(struct iommu_domain *domain,
77ca2332 518 iommu_fault_handler_t handler, void *token)
4f3f8d9d
OBC		 519{
520}
521
e5b5234a 522static inline void iommu_get_resv_regions(struct device *dev,
a1015c2b
JR		 523 struct list_head *list)
524{
525}
526
e5b5234a 527static inline void iommu_put_resv_regions(struct device *dev,
a1015c2b
JR		 528 struct list_head *list)
529{
530}
531
6c65fb31
EA		 532static inline int iommu_get_group_resv_regions(struct iommu_group *group,
533 struct list_head *head)
534{
535 return -ENODEV;
536}
537
d290f1e7
JR		 538static inline int iommu_request_dm_for_dev(struct device *dev)
539{
540 return -ENODEV;
541}
542
bef83de5
AW		 543static inline int iommu_attach_group(struct iommu_domain *domain,
544 struct iommu_group *group)
d72e31c9
AW		 545{
546 return -ENODEV;
547}
548
bef83de5
AW		 549static inline void iommu_detach_group(struct iommu_domain *domain,
550 struct iommu_group *group)
d72e31c9
AW		 551{
552}
553
bef83de5 554static inline struct iommu_group *iommu_group_alloc(void)
d72e31c9
AW		 555{
556 return ERR_PTR(-ENODEV);
557}
558
bef83de5 559static inline void *iommu_group_get_iommudata(struct iommu_group *group)
d72e31c9
AW		 560{
561 return NULL;
562}
563
bef83de5
AW		 564static inline void iommu_group_set_iommudata(struct iommu_group *group,
565 void *iommu_data,
566 void (*release)(void *iommu_data))
d72e31c9
AW		 567{
568}
569
bef83de5
AW		 570static inline int iommu_group_set_name(struct iommu_group *group,
571 const char *name)
d72e31c9
AW		 572{
573 return -ENODEV;
574}
575
bef83de5
AW		 576static inline int iommu_group_add_device(struct iommu_group *group,
577 struct device *dev)
d72e31c9
AW		 578{
579 return -ENODEV;
580}
581
bef83de5 582static inline void iommu_group_remove_device(struct device *dev)
d72e31c9
AW		 583{
584}
585
bef83de5
AW		 586static inline int iommu_group_for_each_dev(struct iommu_group *group,
587 void *data,
588 int (*fn)(struct device *, void *))
d72e31c9
AW		 589{
590 return -ENODEV;
591}
592
bef83de5 593static inline struct iommu_group *iommu_group_get(struct device *dev)
d72e31c9
AW		 594{
595 return NULL;
596}
597
bef83de5 598static inline void iommu_group_put(struct iommu_group *group)
d72e31c9
AW		 599{
600}
601
bef83de5
AW		 602static inline int iommu_group_register_notifier(struct iommu_group *group,
603 struct notifier_block *nb)
1460432c
AW		 604{
605 return -ENODEV;
606}
607
bef83de5
AW		 608static inline int iommu_group_unregister_notifier(struct iommu_group *group,
609 struct notifier_block *nb)
d72e31c9
AW		 610{
611 return 0;
612}
613
bef83de5 614static inline int iommu_group_id(struct iommu_group *group)
d72e31c9
AW		 615{
616 return -ENODEV;
617}
1460432c 618
0cd76dd1
JR		 619static inline int iommu_domain_get_attr(struct iommu_domain *domain,
620 enum iommu_attr attr, void *data)
621{
622 return -EINVAL;
623}
624
625static inline int iommu_domain_set_attr(struct iommu_domain *domain,
626 enum iommu_attr attr, void *data)
627{
628 return -EINVAL;
629}
630
39ab9555 631static inline int iommu_device_register(struct iommu_device *iommu)
c61959ec 632{
39ab9555 633 return -ENODEV;
c61959ec
AW		 634}
635
39ab9555
JR		 636static inline void iommu_device_set_ops(struct iommu_device *iommu,
637 const struct iommu_ops *ops)
c61959ec 638{
c61959ec
AW		 639}
640
c73e1ac8
JR		 641static inline void iommu_device_set_fwnode(struct iommu_device *iommu,
642 struct fwnode_handle *fwnode)
c61959ec 643{
c61959ec
AW		 644}
645
2926a2aa
JR		 646static inline struct iommu_device *dev_to_iommu_device(struct device *dev)
647{
648 return NULL;
649}
650
39ab9555 651static inline void iommu_device_unregister(struct iommu_device *iommu)
c61959ec 652{
c61959ec
AW		 653}
654
39ab9555
JR		 655static inline int iommu_device_sysfs_add(struct iommu_device *iommu,
656 struct device *parent,
657 const struct attribute_group **groups,
658 const char *fmt, ...)
b0119e87 659{
39ab9555 660 return -ENODEV;
b0119e87
JR		 661}
662
39ab9555 663static inline void iommu_device_sysfs_remove(struct iommu_device *iommu)
c61959ec
AW		 664{
665}
666
e09f8ea5 667static inline int iommu_device_link(struct device *dev, struct device *link)
c61959ec
AW		 668{
669 return -EINVAL;
670}
671
e09f8ea5 672static inline void iommu_device_unlink(struct device *dev, struct device *link)
c61959ec
AW		 673{
674}
675
57f98d2f
RM		 676static inline int iommu_fwspec_init(struct device *dev,
677 struct fwnode_handle *iommu_fwnode,
678 const struct iommu_ops *ops)
679{
680 return -ENODEV;
681}
682
683static inline void iommu_fwspec_free(struct device *dev)
684{
685}
686
687static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids,
688 int num_ids)
689{
690 return -ENODEV;
691}
692
e4f10ffe 693static inline
534766df 694const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode)
e4f10ffe
LP		 695{
696 return NULL;
697}
698
4a77a6cf
JR		 699#endif /* CONFIG_IOMMU_API */
700
701#endif /* __LINUX_IOMMU_H */
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