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4a77a6cf JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_IOMMU_H | |
20 | #define __LINUX_IOMMU_H | |
21 | ||
e8245c1b JR |
22 | #include <linux/scatterlist.h> |
23 | #include <linux/device.h> | |
24 | #include <linux/types.h> | |
74315ccc | 25 | #include <linux/errno.h> |
9a08d376 | 26 | #include <linux/err.h> |
d0f60a44 | 27 | #include <linux/of.h> |
74315ccc | 28 | |
ca13bb3d WD |
29 | #define IOMMU_READ (1 << 0) |
30 | #define IOMMU_WRITE (1 << 1) | |
31 | #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ | |
a720b41c | 32 | #define IOMMU_NOEXEC (1 << 3) |
31e6850e | 33 | #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ |
579b2a65 | 34 | /* |
adf5e516 RM |
35 | * Where the bus hardware includes a privilege level as part of its access type |
36 | * markings, and certain devices are capable of issuing transactions marked as | |
37 | * either 'supervisor' or 'user', the IOMMU_PRIV flag requests that the other | |
38 | * given permission flags only apply to accesses at the higher privilege level, | |
39 | * and that unprivileged transactions should have as little access as possible. | |
40 | * This would usually imply the same permissions as kernel mappings on the CPU, | |
41 | * if the IOMMU page table format is equivalent. | |
579b2a65 MH |
42 | */ |
43 | #define IOMMU_PRIV (1 << 5) | |
4a77a6cf | 44 | |
905d66c1 | 45 | struct iommu_ops; |
d72e31c9 | 46 | struct iommu_group; |
ff21776d | 47 | struct bus_type; |
4a77a6cf | 48 | struct device; |
4f3f8d9d | 49 | struct iommu_domain; |
ba1eabfa | 50 | struct notifier_block; |
4f3f8d9d OBC |
51 | |
52 | /* iommu fault flags */ | |
53 | #define IOMMU_FAULT_READ 0x0 | |
54 | #define IOMMU_FAULT_WRITE 0x1 | |
55 | ||
56 | typedef int (*iommu_fault_handler_t)(struct iommu_domain *, | |
77ca2332 | 57 | struct device *, unsigned long, int, void *); |
4a77a6cf | 58 | |
0ff64f80 JR |
59 | struct iommu_domain_geometry { |
60 | dma_addr_t aperture_start; /* First address that can be mapped */ | |
61 | dma_addr_t aperture_end; /* Last address that can be mapped */ | |
62 | bool force_aperture; /* DMA only allowed in mappable range? */ | |
63 | }; | |
64 | ||
8539c7c1 JR |
65 | /* Domain feature flags */ |
66 | #define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */ | |
67 | #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API | |
68 | implementation */ | |
69 | #define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */ | |
70 | ||
71 | /* | |
72 | * This are the possible domain-types | |
73 | * | |
74 | * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate | |
75 | * devices | |
76 | * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses | |
77 | * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used | |
78 | * for VMs | |
79 | * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations. | |
80 | * This flag allows IOMMU drivers to implement | |
81 | * certain optimizations for these domains | |
82 | */ | |
83 | #define IOMMU_DOMAIN_BLOCKED (0U) | |
84 | #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) | |
85 | #define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING) | |
86 | #define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \ | |
87 | __IOMMU_DOMAIN_DMA_API) | |
88 | ||
4a77a6cf | 89 | struct iommu_domain { |
8539c7c1 | 90 | unsigned type; |
b22f6434 | 91 | const struct iommu_ops *ops; |
d16e0faa | 92 | unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */ |
4f3f8d9d | 93 | iommu_fault_handler_t handler; |
77ca2332 | 94 | void *handler_token; |
0ff64f80 | 95 | struct iommu_domain_geometry geometry; |
0db2e5d1 | 96 | void *iova_cookie; |
4a77a6cf JR |
97 | }; |
98 | ||
1aed0748 JR |
99 | enum iommu_cap { |
100 | IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA | |
101 | transactions */ | |
102 | IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ | |
c4986649 | 103 | IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ |
1aed0748 | 104 | }; |
dbb9fd86 | 105 | |
7cabf491 VS |
106 | /* |
107 | * Following constraints are specifc to FSL_PAMUV1: | |
108 | * -aperture must be power of 2, and naturally aligned | |
109 | * -number of windows must be power of 2, and address space size | |
110 | * of each window is determined by aperture size / # of windows | |
111 | * -the actual size of the mapped region of a window must be power | |
112 | * of 2 starting with 4KB and physical address must be naturally | |
113 | * aligned. | |
114 | * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. | |
115 | * The caller can invoke iommu_domain_get_attr to check if the underlying | |
116 | * iommu implementation supports these constraints. | |
117 | */ | |
118 | ||
0cd76dd1 | 119 | enum iommu_attr { |
0ff64f80 | 120 | DOMAIN_ATTR_GEOMETRY, |
d2e12160 | 121 | DOMAIN_ATTR_PAGING, |
69356712 | 122 | DOMAIN_ATTR_WINDOWS, |
7cabf491 VS |
123 | DOMAIN_ATTR_FSL_PAMU_STASH, |
124 | DOMAIN_ATTR_FSL_PAMU_ENABLE, | |
125 | DOMAIN_ATTR_FSL_PAMUV1, | |
c02607aa | 126 | DOMAIN_ATTR_NESTING, /* two stages of translation */ |
a8b8a88a | 127 | DOMAIN_ATTR_MAX, |
0cd76dd1 JR |
128 | }; |
129 | ||
d30ddcaa | 130 | /* These are the possible reserved region types */ |
9d3a4de4 RM |
131 | enum iommu_resv_type { |
132 | /* Memory regions which must be mapped 1:1 at all times */ | |
133 | IOMMU_RESV_DIRECT, | |
134 | /* Arbitrary "never map this or give it to a device" address ranges */ | |
135 | IOMMU_RESV_RESERVED, | |
136 | /* Hardware MSI region (untranslated) */ | |
137 | IOMMU_RESV_MSI, | |
138 | /* Software-managed MSI translation window */ | |
139 | IOMMU_RESV_SW_MSI, | |
140 | }; | |
d30ddcaa | 141 | |
a1015c2b | 142 | /** |
e5b5234a | 143 | * struct iommu_resv_region - descriptor for a reserved memory region |
a1015c2b JR |
144 | * @list: Linked list pointers |
145 | * @start: System physical start address of the region | |
146 | * @length: Length of the region in bytes | |
147 | * @prot: IOMMU Protection flags (READ/WRITE/...) | |
d30ddcaa | 148 | * @type: Type of the reserved region |
a1015c2b | 149 | */ |
e5b5234a | 150 | struct iommu_resv_region { |
a1015c2b JR |
151 | struct list_head list; |
152 | phys_addr_t start; | |
153 | size_t length; | |
154 | int prot; | |
9d3a4de4 | 155 | enum iommu_resv_type type; |
a1015c2b JR |
156 | }; |
157 | ||
39d4ebb9 JR |
158 | #ifdef CONFIG_IOMMU_API |
159 | ||
7d3002cc OBC |
160 | /** |
161 | * struct iommu_ops - iommu ops and capabilities | |
0d9bacb6 MD |
162 | * @capable: check capability |
163 | * @domain_alloc: allocate iommu domain | |
164 | * @domain_free: free iommu domain | |
7d3002cc OBC |
165 | * @attach_dev: attach device to an iommu domain |
166 | * @detach_dev: detach device from an iommu domain | |
167 | * @map: map a physically contiguous memory region to an iommu domain | |
168 | * @unmap: unmap a physically contiguous memory region from an iommu domain | |
315786eb OH |
169 | * @map_sg: map a scatter-gather list of physically contiguous memory chunks |
170 | * to an iommu domain | |
7d3002cc | 171 | * @iova_to_phys: translate iova to physical address |
d72e31c9 AW |
172 | * @add_device: add device to iommu grouping |
173 | * @remove_device: remove device from iommu grouping | |
0d9bacb6 | 174 | * @device_group: find iommu group for a particular device |
0cd76dd1 JR |
175 | * @domain_get_attr: Query domain attributes |
176 | * @domain_set_attr: Change domain attributes | |
e5b5234a EA |
177 | * @get_resv_regions: Request list of reserved regions for a device |
178 | * @put_resv_regions: Free list of reserved regions for a device | |
179 | * @apply_resv_region: Temporary helper call-back for iova reserved ranges | |
0d9bacb6 MD |
180 | * @domain_window_enable: Configure and enable a particular window for a domain |
181 | * @domain_window_disable: Disable a particular window for a domain | |
182 | * @domain_set_windows: Set the number of windows for a domain | |
183 | * @domain_get_windows: Return the number of windows for a domain | |
d0f60a44 | 184 | * @of_xlate: add OF master IDs to iommu grouping |
d16e0faa | 185 | * @pgsize_bitmap: bitmap of all possible supported page sizes |
7d3002cc | 186 | */ |
4a77a6cf | 187 | struct iommu_ops { |
3c0e0ca0 | 188 | bool (*capable)(enum iommu_cap); |
938c4709 JR |
189 | |
190 | /* Domain allocation and freeing by the iommu driver */ | |
8539c7c1 | 191 | struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); |
938c4709 JR |
192 | void (*domain_free)(struct iommu_domain *); |
193 | ||
4a77a6cf JR |
194 | int (*attach_dev)(struct iommu_domain *domain, struct device *dev); |
195 | void (*detach_dev)(struct iommu_domain *domain, struct device *dev); | |
67651786 | 196 | int (*map)(struct iommu_domain *domain, unsigned long iova, |
5009065d OBC |
197 | phys_addr_t paddr, size_t size, int prot); |
198 | size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, | |
199 | size_t size); | |
315786eb OH |
200 | size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova, |
201 | struct scatterlist *sg, unsigned int nents, int prot); | |
bb5547ac | 202 | phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); |
d72e31c9 AW |
203 | int (*add_device)(struct device *dev); |
204 | void (*remove_device)(struct device *dev); | |
46c6b2bc | 205 | struct iommu_group *(*device_group)(struct device *dev); |
0cd76dd1 JR |
206 | int (*domain_get_attr)(struct iommu_domain *domain, |
207 | enum iommu_attr attr, void *data); | |
208 | int (*domain_set_attr)(struct iommu_domain *domain, | |
209 | enum iommu_attr attr, void *data); | |
d7787d57 | 210 | |
e5b5234a EA |
211 | /* Request/Free a list of reserved regions for a device */ |
212 | void (*get_resv_regions)(struct device *dev, struct list_head *list); | |
213 | void (*put_resv_regions)(struct device *dev, struct list_head *list); | |
214 | void (*apply_resv_region)(struct device *dev, | |
215 | struct iommu_domain *domain, | |
216 | struct iommu_resv_region *region); | |
a1015c2b | 217 | |
d7787d57 JR |
218 | /* Window handling functions */ |
219 | int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f | 220 | phys_addr_t paddr, u64 size, int prot); |
d7787d57 | 221 | void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr); |
0d9bacb6 | 222 | /* Set the number of windows per domain */ |
69356712 | 223 | int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count); |
0d9bacb6 | 224 | /* Get the number of windows per domain */ |
69356712 | 225 | u32 (*domain_get_windows)(struct iommu_domain *domain); |
d7787d57 | 226 | |
d0f60a44 | 227 | int (*of_xlate)(struct device *dev, struct of_phandle_args *args); |
d0f60a44 | 228 | |
7d3002cc | 229 | unsigned long pgsize_bitmap; |
4a77a6cf JR |
230 | }; |
231 | ||
b0119e87 JR |
232 | /** |
233 | * struct iommu_device - IOMMU core representation of one IOMMU hardware | |
234 | * instance | |
235 | * @list: Used by the iommu-core to keep a list of registered iommus | |
236 | * @ops: iommu-ops for talking to this iommu | |
39ab9555 | 237 | * @dev: struct device for sysfs handling |
b0119e87 JR |
238 | */ |
239 | struct iommu_device { | |
240 | struct list_head list; | |
241 | const struct iommu_ops *ops; | |
c73e1ac8 | 242 | struct fwnode_handle *fwnode; |
39ab9555 | 243 | struct device dev; |
b0119e87 JR |
244 | }; |
245 | ||
246 | int iommu_device_register(struct iommu_device *iommu); | |
247 | void iommu_device_unregister(struct iommu_device *iommu); | |
39ab9555 JR |
248 | int iommu_device_sysfs_add(struct iommu_device *iommu, |
249 | struct device *parent, | |
250 | const struct attribute_group **groups, | |
251 | const char *fmt, ...) __printf(4, 5); | |
252 | void iommu_device_sysfs_remove(struct iommu_device *iommu); | |
e3d10af1 JR |
253 | int iommu_device_link(struct iommu_device *iommu, struct device *link); |
254 | void iommu_device_unlink(struct iommu_device *iommu, struct device *link); | |
b0119e87 JR |
255 | |
256 | static inline void iommu_device_set_ops(struct iommu_device *iommu, | |
257 | const struct iommu_ops *ops) | |
258 | { | |
259 | iommu->ops = ops; | |
260 | } | |
261 | ||
c73e1ac8 JR |
262 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
263 | struct fwnode_handle *fwnode) | |
264 | { | |
265 | iommu->fwnode = fwnode; | |
266 | } | |
267 | ||
d72e31c9 AW |
268 | #define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */ |
269 | #define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */ | |
270 | #define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */ | |
271 | #define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */ | |
272 | #define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */ | |
273 | #define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */ | |
274 | ||
b22f6434 | 275 | extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); |
a1b60c1c | 276 | extern bool iommu_present(struct bus_type *bus); |
3c0e0ca0 | 277 | extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); |
905d66c1 | 278 | extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); |
aa16bea9 | 279 | extern struct iommu_group *iommu_group_get_by_id(int id); |
4a77a6cf JR |
280 | extern void iommu_domain_free(struct iommu_domain *domain); |
281 | extern int iommu_attach_device(struct iommu_domain *domain, | |
282 | struct device *dev); | |
283 | extern void iommu_detach_device(struct iommu_domain *domain, | |
284 | struct device *dev); | |
2c1296d9 | 285 | extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); |
cefc53c7 | 286 | extern int iommu_map(struct iommu_domain *domain, unsigned long iova, |
7d3002cc OBC |
287 | phys_addr_t paddr, size_t size, int prot); |
288 | extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
289 | size_t size); | |
315786eb OH |
290 | extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova, |
291 | struct scatterlist *sg,unsigned int nents, | |
292 | int prot); | |
bb5547ac | 293 | extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); |
4f3f8d9d | 294 | extern void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 295 | iommu_fault_handler_t handler, void *token); |
d72e31c9 | 296 | |
e5b5234a EA |
297 | extern void iommu_get_resv_regions(struct device *dev, struct list_head *list); |
298 | extern void iommu_put_resv_regions(struct device *dev, struct list_head *list); | |
d290f1e7 | 299 | extern int iommu_request_dm_for_dev(struct device *dev); |
2b20cbba | 300 | extern struct iommu_resv_region * |
9d3a4de4 RM |
301 | iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot, |
302 | enum iommu_resv_type type); | |
6c65fb31 EA |
303 | extern int iommu_get_group_resv_regions(struct iommu_group *group, |
304 | struct list_head *head); | |
a1015c2b | 305 | |
d72e31c9 AW |
306 | extern int iommu_attach_group(struct iommu_domain *domain, |
307 | struct iommu_group *group); | |
308 | extern void iommu_detach_group(struct iommu_domain *domain, | |
309 | struct iommu_group *group); | |
310 | extern struct iommu_group *iommu_group_alloc(void); | |
311 | extern void *iommu_group_get_iommudata(struct iommu_group *group); | |
312 | extern void iommu_group_set_iommudata(struct iommu_group *group, | |
313 | void *iommu_data, | |
314 | void (*release)(void *iommu_data)); | |
315 | extern int iommu_group_set_name(struct iommu_group *group, const char *name); | |
316 | extern int iommu_group_add_device(struct iommu_group *group, | |
317 | struct device *dev); | |
318 | extern void iommu_group_remove_device(struct device *dev); | |
319 | extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, | |
320 | int (*fn)(struct device *, void *)); | |
321 | extern struct iommu_group *iommu_group_get(struct device *dev); | |
13f59a78 | 322 | extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group); |
d72e31c9 AW |
323 | extern void iommu_group_put(struct iommu_group *group); |
324 | extern int iommu_group_register_notifier(struct iommu_group *group, | |
325 | struct notifier_block *nb); | |
326 | extern int iommu_group_unregister_notifier(struct iommu_group *group, | |
327 | struct notifier_block *nb); | |
328 | extern int iommu_group_id(struct iommu_group *group); | |
104a1c13 | 329 | extern struct iommu_group *iommu_group_get_for_dev(struct device *dev); |
6827ca83 | 330 | extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); |
4f3f8d9d | 331 | |
0cd76dd1 JR |
332 | extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, |
333 | void *data); | |
334 | extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, | |
335 | void *data); | |
4f3f8d9d | 336 | |
d7787d57 JR |
337 | /* Window handling function prototypes */ |
338 | extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f VS |
339 | phys_addr_t offset, u64 size, |
340 | int prot); | |
d7787d57 | 341 | extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr); |
207c6e36 JR |
342 | |
343 | extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev, | |
344 | unsigned long iova, int flags); | |
4a77a6cf | 345 | |
315786eb OH |
346 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
347 | unsigned long iova, struct scatterlist *sg, | |
348 | unsigned int nents, int prot) | |
349 | { | |
350 | return domain->ops->map_sg(domain, iova, sg, nents, prot); | |
351 | } | |
352 | ||
5e62292b JR |
353 | /* PCI device grouping function */ |
354 | extern struct iommu_group *pci_device_group(struct device *dev); | |
6eab556a JR |
355 | /* Generic device grouping function */ |
356 | extern struct iommu_group *generic_device_group(struct device *dev); | |
5e62292b | 357 | |
57f98d2f RM |
358 | /** |
359 | * struct iommu_fwspec - per-device IOMMU instance data | |
360 | * @ops: ops for this device's IOMMU | |
361 | * @iommu_fwnode: firmware handle for this device's IOMMU | |
362 | * @iommu_priv: IOMMU driver private data for this device | |
363 | * @num_ids: number of associated device IDs | |
364 | * @ids: IDs which this device may present to the IOMMU | |
365 | */ | |
366 | struct iommu_fwspec { | |
367 | const struct iommu_ops *ops; | |
368 | struct fwnode_handle *iommu_fwnode; | |
369 | void *iommu_priv; | |
370 | unsigned int num_ids; | |
371 | u32 ids[1]; | |
372 | }; | |
373 | ||
374 | int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, | |
375 | const struct iommu_ops *ops); | |
376 | void iommu_fwspec_free(struct device *dev); | |
377 | int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); | |
534766df | 378 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); |
57f98d2f | 379 | |
4a77a6cf JR |
380 | #else /* CONFIG_IOMMU_API */ |
381 | ||
39d4ebb9 | 382 | struct iommu_ops {}; |
d72e31c9 | 383 | struct iommu_group {}; |
57f98d2f | 384 | struct iommu_fwspec {}; |
b0119e87 | 385 | struct iommu_device {}; |
4a77a6cf | 386 | |
a1b60c1c | 387 | static inline bool iommu_present(struct bus_type *bus) |
4a77a6cf JR |
388 | { |
389 | return false; | |
390 | } | |
391 | ||
3c0e0ca0 JR |
392 | static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap) |
393 | { | |
394 | return false; | |
395 | } | |
396 | ||
905d66c1 | 397 | static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus) |
4a77a6cf JR |
398 | { |
399 | return NULL; | |
400 | } | |
401 | ||
b62dfd29 AK |
402 | static inline struct iommu_group *iommu_group_get_by_id(int id) |
403 | { | |
404 | return NULL; | |
405 | } | |
406 | ||
4a77a6cf JR |
407 | static inline void iommu_domain_free(struct iommu_domain *domain) |
408 | { | |
409 | } | |
410 | ||
411 | static inline int iommu_attach_device(struct iommu_domain *domain, | |
412 | struct device *dev) | |
413 | { | |
414 | return -ENODEV; | |
415 | } | |
416 | ||
417 | static inline void iommu_detach_device(struct iommu_domain *domain, | |
418 | struct device *dev) | |
419 | { | |
420 | } | |
421 | ||
2c1296d9 JR |
422 | static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) |
423 | { | |
424 | return NULL; | |
425 | } | |
426 | ||
cefc53c7 | 427 | static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, |
ebae3e83 | 428 | phys_addr_t paddr, size_t size, int prot) |
cefc53c7 JR |
429 | { |
430 | return -ENODEV; | |
431 | } | |
432 | ||
433 | static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
ebae3e83 | 434 | size_t size) |
cefc53c7 JR |
435 | { |
436 | return -ENODEV; | |
437 | } | |
438 | ||
315786eb OH |
439 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
440 | unsigned long iova, struct scatterlist *sg, | |
441 | unsigned int nents, int prot) | |
442 | { | |
443 | return -ENODEV; | |
444 | } | |
445 | ||
d7787d57 JR |
446 | static inline int iommu_domain_window_enable(struct iommu_domain *domain, |
447 | u32 wnd_nr, phys_addr_t paddr, | |
80f97f0f | 448 | u64 size, int prot) |
d7787d57 JR |
449 | { |
450 | return -ENODEV; | |
451 | } | |
452 | ||
453 | static inline void iommu_domain_window_disable(struct iommu_domain *domain, | |
454 | u32 wnd_nr) | |
455 | { | |
456 | } | |
457 | ||
bb5547ac | 458 | static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) |
4a77a6cf JR |
459 | { |
460 | return 0; | |
461 | } | |
462 | ||
4f3f8d9d | 463 | static inline void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 464 | iommu_fault_handler_t handler, void *token) |
4f3f8d9d OBC |
465 | { |
466 | } | |
467 | ||
e5b5234a | 468 | static inline void iommu_get_resv_regions(struct device *dev, |
a1015c2b JR |
469 | struct list_head *list) |
470 | { | |
471 | } | |
472 | ||
e5b5234a | 473 | static inline void iommu_put_resv_regions(struct device *dev, |
a1015c2b JR |
474 | struct list_head *list) |
475 | { | |
476 | } | |
477 | ||
6c65fb31 EA |
478 | static inline int iommu_get_group_resv_regions(struct iommu_group *group, |
479 | struct list_head *head) | |
480 | { | |
481 | return -ENODEV; | |
482 | } | |
483 | ||
d290f1e7 JR |
484 | static inline int iommu_request_dm_for_dev(struct device *dev) |
485 | { | |
486 | return -ENODEV; | |
487 | } | |
488 | ||
bef83de5 AW |
489 | static inline int iommu_attach_group(struct iommu_domain *domain, |
490 | struct iommu_group *group) | |
d72e31c9 AW |
491 | { |
492 | return -ENODEV; | |
493 | } | |
494 | ||
bef83de5 AW |
495 | static inline void iommu_detach_group(struct iommu_domain *domain, |
496 | struct iommu_group *group) | |
d72e31c9 AW |
497 | { |
498 | } | |
499 | ||
bef83de5 | 500 | static inline struct iommu_group *iommu_group_alloc(void) |
d72e31c9 AW |
501 | { |
502 | return ERR_PTR(-ENODEV); | |
503 | } | |
504 | ||
bef83de5 | 505 | static inline void *iommu_group_get_iommudata(struct iommu_group *group) |
d72e31c9 AW |
506 | { |
507 | return NULL; | |
508 | } | |
509 | ||
bef83de5 AW |
510 | static inline void iommu_group_set_iommudata(struct iommu_group *group, |
511 | void *iommu_data, | |
512 | void (*release)(void *iommu_data)) | |
d72e31c9 AW |
513 | { |
514 | } | |
515 | ||
bef83de5 AW |
516 | static inline int iommu_group_set_name(struct iommu_group *group, |
517 | const char *name) | |
d72e31c9 AW |
518 | { |
519 | return -ENODEV; | |
520 | } | |
521 | ||
bef83de5 AW |
522 | static inline int iommu_group_add_device(struct iommu_group *group, |
523 | struct device *dev) | |
d72e31c9 AW |
524 | { |
525 | return -ENODEV; | |
526 | } | |
527 | ||
bef83de5 | 528 | static inline void iommu_group_remove_device(struct device *dev) |
d72e31c9 AW |
529 | { |
530 | } | |
531 | ||
bef83de5 AW |
532 | static inline int iommu_group_for_each_dev(struct iommu_group *group, |
533 | void *data, | |
534 | int (*fn)(struct device *, void *)) | |
d72e31c9 AW |
535 | { |
536 | return -ENODEV; | |
537 | } | |
538 | ||
bef83de5 | 539 | static inline struct iommu_group *iommu_group_get(struct device *dev) |
d72e31c9 AW |
540 | { |
541 | return NULL; | |
542 | } | |
543 | ||
bef83de5 | 544 | static inline void iommu_group_put(struct iommu_group *group) |
d72e31c9 AW |
545 | { |
546 | } | |
547 | ||
bef83de5 AW |
548 | static inline int iommu_group_register_notifier(struct iommu_group *group, |
549 | struct notifier_block *nb) | |
1460432c AW |
550 | { |
551 | return -ENODEV; | |
552 | } | |
553 | ||
bef83de5 AW |
554 | static inline int iommu_group_unregister_notifier(struct iommu_group *group, |
555 | struct notifier_block *nb) | |
d72e31c9 AW |
556 | { |
557 | return 0; | |
558 | } | |
559 | ||
bef83de5 | 560 | static inline int iommu_group_id(struct iommu_group *group) |
d72e31c9 AW |
561 | { |
562 | return -ENODEV; | |
563 | } | |
1460432c | 564 | |
0cd76dd1 JR |
565 | static inline int iommu_domain_get_attr(struct iommu_domain *domain, |
566 | enum iommu_attr attr, void *data) | |
567 | { | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | static inline int iommu_domain_set_attr(struct iommu_domain *domain, | |
572 | enum iommu_attr attr, void *data) | |
573 | { | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
39ab9555 | 577 | static inline int iommu_device_register(struct iommu_device *iommu) |
c61959ec | 578 | { |
39ab9555 | 579 | return -ENODEV; |
c61959ec AW |
580 | } |
581 | ||
39ab9555 JR |
582 | static inline void iommu_device_set_ops(struct iommu_device *iommu, |
583 | const struct iommu_ops *ops) | |
c61959ec | 584 | { |
c61959ec AW |
585 | } |
586 | ||
c73e1ac8 JR |
587 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
588 | struct fwnode_handle *fwnode) | |
c61959ec | 589 | { |
c61959ec AW |
590 | } |
591 | ||
39ab9555 | 592 | static inline void iommu_device_unregister(struct iommu_device *iommu) |
c61959ec | 593 | { |
c61959ec AW |
594 | } |
595 | ||
39ab9555 JR |
596 | static inline int iommu_device_sysfs_add(struct iommu_device *iommu, |
597 | struct device *parent, | |
598 | const struct attribute_group **groups, | |
599 | const char *fmt, ...) | |
b0119e87 | 600 | { |
39ab9555 | 601 | return -ENODEV; |
b0119e87 JR |
602 | } |
603 | ||
39ab9555 | 604 | static inline void iommu_device_sysfs_remove(struct iommu_device *iommu) |
c61959ec AW |
605 | { |
606 | } | |
607 | ||
e09f8ea5 | 608 | static inline int iommu_device_link(struct device *dev, struct device *link) |
c61959ec AW |
609 | { |
610 | return -EINVAL; | |
611 | } | |
612 | ||
e09f8ea5 | 613 | static inline void iommu_device_unlink(struct device *dev, struct device *link) |
c61959ec AW |
614 | { |
615 | } | |
616 | ||
57f98d2f RM |
617 | static inline int iommu_fwspec_init(struct device *dev, |
618 | struct fwnode_handle *iommu_fwnode, | |
619 | const struct iommu_ops *ops) | |
620 | { | |
621 | return -ENODEV; | |
622 | } | |
623 | ||
624 | static inline void iommu_fwspec_free(struct device *dev) | |
625 | { | |
626 | } | |
627 | ||
628 | static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, | |
629 | int num_ids) | |
630 | { | |
631 | return -ENODEV; | |
632 | } | |
633 | ||
e4f10ffe | 634 | static inline |
534766df | 635 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) |
e4f10ffe LP |
636 | { |
637 | return NULL; | |
638 | } | |
639 | ||
4a77a6cf JR |
640 | #endif /* CONFIG_IOMMU_API */ |
641 | ||
642 | #endif /* __LINUX_IOMMU_H */ |