]>
Commit | Line | Data |
---|---|---|
4a77a6cf JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_IOMMU_H | |
20 | #define __LINUX_IOMMU_H | |
21 | ||
e8245c1b JR |
22 | #include <linux/scatterlist.h> |
23 | #include <linux/device.h> | |
24 | #include <linux/types.h> | |
74315ccc | 25 | #include <linux/errno.h> |
9a08d376 | 26 | #include <linux/err.h> |
d0f60a44 | 27 | #include <linux/of.h> |
74315ccc | 28 | |
ca13bb3d WD |
29 | #define IOMMU_READ (1 << 0) |
30 | #define IOMMU_WRITE (1 << 1) | |
31 | #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ | |
a720b41c | 32 | #define IOMMU_NOEXEC (1 << 3) |
31e6850e | 33 | #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ |
579b2a65 | 34 | /* |
adf5e516 RM |
35 | * Where the bus hardware includes a privilege level as part of its access type |
36 | * markings, and certain devices are capable of issuing transactions marked as | |
37 | * either 'supervisor' or 'user', the IOMMU_PRIV flag requests that the other | |
38 | * given permission flags only apply to accesses at the higher privilege level, | |
39 | * and that unprivileged transactions should have as little access as possible. | |
40 | * This would usually imply the same permissions as kernel mappings on the CPU, | |
41 | * if the IOMMU page table format is equivalent. | |
579b2a65 MH |
42 | */ |
43 | #define IOMMU_PRIV (1 << 5) | |
4a77a6cf | 44 | |
905d66c1 | 45 | struct iommu_ops; |
d72e31c9 | 46 | struct iommu_group; |
ff21776d | 47 | struct bus_type; |
4a77a6cf | 48 | struct device; |
4f3f8d9d | 49 | struct iommu_domain; |
ba1eabfa | 50 | struct notifier_block; |
4f3f8d9d OBC |
51 | |
52 | /* iommu fault flags */ | |
53 | #define IOMMU_FAULT_READ 0x0 | |
54 | #define IOMMU_FAULT_WRITE 0x1 | |
55 | ||
56 | typedef int (*iommu_fault_handler_t)(struct iommu_domain *, | |
77ca2332 | 57 | struct device *, unsigned long, int, void *); |
4a77a6cf | 58 | |
0ff64f80 JR |
59 | struct iommu_domain_geometry { |
60 | dma_addr_t aperture_start; /* First address that can be mapped */ | |
61 | dma_addr_t aperture_end; /* Last address that can be mapped */ | |
62 | bool force_aperture; /* DMA only allowed in mappable range? */ | |
63 | }; | |
64 | ||
8539c7c1 JR |
65 | /* Domain feature flags */ |
66 | #define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */ | |
67 | #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API | |
68 | implementation */ | |
69 | #define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */ | |
70 | ||
71 | /* | |
72 | * This are the possible domain-types | |
73 | * | |
74 | * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate | |
75 | * devices | |
76 | * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses | |
77 | * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used | |
78 | * for VMs | |
79 | * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations. | |
80 | * This flag allows IOMMU drivers to implement | |
81 | * certain optimizations for these domains | |
82 | */ | |
83 | #define IOMMU_DOMAIN_BLOCKED (0U) | |
84 | #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) | |
85 | #define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING) | |
86 | #define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \ | |
87 | __IOMMU_DOMAIN_DMA_API) | |
88 | ||
4a77a6cf | 89 | struct iommu_domain { |
8539c7c1 | 90 | unsigned type; |
b22f6434 | 91 | const struct iommu_ops *ops; |
d16e0faa | 92 | unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */ |
4f3f8d9d | 93 | iommu_fault_handler_t handler; |
77ca2332 | 94 | void *handler_token; |
0ff64f80 | 95 | struct iommu_domain_geometry geometry; |
0db2e5d1 | 96 | void *iova_cookie; |
4a77a6cf JR |
97 | }; |
98 | ||
1aed0748 JR |
99 | enum iommu_cap { |
100 | IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA | |
101 | transactions */ | |
102 | IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ | |
c4986649 | 103 | IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ |
1aed0748 | 104 | }; |
dbb9fd86 | 105 | |
7cabf491 VS |
106 | /* |
107 | * Following constraints are specifc to FSL_PAMUV1: | |
108 | * -aperture must be power of 2, and naturally aligned | |
109 | * -number of windows must be power of 2, and address space size | |
110 | * of each window is determined by aperture size / # of windows | |
111 | * -the actual size of the mapped region of a window must be power | |
112 | * of 2 starting with 4KB and physical address must be naturally | |
113 | * aligned. | |
114 | * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. | |
115 | * The caller can invoke iommu_domain_get_attr to check if the underlying | |
116 | * iommu implementation supports these constraints. | |
117 | */ | |
118 | ||
0cd76dd1 | 119 | enum iommu_attr { |
0ff64f80 | 120 | DOMAIN_ATTR_GEOMETRY, |
d2e12160 | 121 | DOMAIN_ATTR_PAGING, |
69356712 | 122 | DOMAIN_ATTR_WINDOWS, |
7cabf491 VS |
123 | DOMAIN_ATTR_FSL_PAMU_STASH, |
124 | DOMAIN_ATTR_FSL_PAMU_ENABLE, | |
125 | DOMAIN_ATTR_FSL_PAMUV1, | |
c02607aa | 126 | DOMAIN_ATTR_NESTING, /* two stages of translation */ |
a8b8a88a | 127 | DOMAIN_ATTR_MAX, |
0cd76dd1 JR |
128 | }; |
129 | ||
d30ddcaa | 130 | /* These are the possible reserved region types */ |
9d3a4de4 RM |
131 | enum iommu_resv_type { |
132 | /* Memory regions which must be mapped 1:1 at all times */ | |
133 | IOMMU_RESV_DIRECT, | |
134 | /* Arbitrary "never map this or give it to a device" address ranges */ | |
135 | IOMMU_RESV_RESERVED, | |
136 | /* Hardware MSI region (untranslated) */ | |
137 | IOMMU_RESV_MSI, | |
138 | /* Software-managed MSI translation window */ | |
139 | IOMMU_RESV_SW_MSI, | |
140 | }; | |
d30ddcaa | 141 | |
a1015c2b | 142 | /** |
e5b5234a | 143 | * struct iommu_resv_region - descriptor for a reserved memory region |
a1015c2b JR |
144 | * @list: Linked list pointers |
145 | * @start: System physical start address of the region | |
146 | * @length: Length of the region in bytes | |
147 | * @prot: IOMMU Protection flags (READ/WRITE/...) | |
d30ddcaa | 148 | * @type: Type of the reserved region |
a1015c2b | 149 | */ |
e5b5234a | 150 | struct iommu_resv_region { |
a1015c2b JR |
151 | struct list_head list; |
152 | phys_addr_t start; | |
153 | size_t length; | |
154 | int prot; | |
9d3a4de4 | 155 | enum iommu_resv_type type; |
a1015c2b JR |
156 | }; |
157 | ||
39d4ebb9 JR |
158 | #ifdef CONFIG_IOMMU_API |
159 | ||
7d3002cc OBC |
160 | /** |
161 | * struct iommu_ops - iommu ops and capabilities | |
0d9bacb6 MD |
162 | * @capable: check capability |
163 | * @domain_alloc: allocate iommu domain | |
164 | * @domain_free: free iommu domain | |
7d3002cc OBC |
165 | * @attach_dev: attach device to an iommu domain |
166 | * @detach_dev: detach device from an iommu domain | |
167 | * @map: map a physically contiguous memory region to an iommu domain | |
168 | * @unmap: unmap a physically contiguous memory region from an iommu domain | |
add02cfd JR |
169 | * @flush_tlb_all: Synchronously flush all hardware TLBs for this domain |
170 | * @tlb_range_add: Add a given iova range to the flush queue for this domain | |
171 | * @tlb_sync: Flush all queued ranges from the hardware TLBs and empty flush | |
172 | * queue | |
7d3002cc | 173 | * @iova_to_phys: translate iova to physical address |
d72e31c9 AW |
174 | * @add_device: add device to iommu grouping |
175 | * @remove_device: remove device from iommu grouping | |
0d9bacb6 | 176 | * @device_group: find iommu group for a particular device |
0cd76dd1 JR |
177 | * @domain_get_attr: Query domain attributes |
178 | * @domain_set_attr: Change domain attributes | |
e5b5234a EA |
179 | * @get_resv_regions: Request list of reserved regions for a device |
180 | * @put_resv_regions: Free list of reserved regions for a device | |
181 | * @apply_resv_region: Temporary helper call-back for iova reserved ranges | |
0d9bacb6 MD |
182 | * @domain_window_enable: Configure and enable a particular window for a domain |
183 | * @domain_window_disable: Disable a particular window for a domain | |
184 | * @domain_set_windows: Set the number of windows for a domain | |
185 | * @domain_get_windows: Return the number of windows for a domain | |
d0f60a44 | 186 | * @of_xlate: add OF master IDs to iommu grouping |
d16e0faa | 187 | * @pgsize_bitmap: bitmap of all possible supported page sizes |
7d3002cc | 188 | */ |
4a77a6cf | 189 | struct iommu_ops { |
3c0e0ca0 | 190 | bool (*capable)(enum iommu_cap); |
938c4709 JR |
191 | |
192 | /* Domain allocation and freeing by the iommu driver */ | |
8539c7c1 | 193 | struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); |
938c4709 JR |
194 | void (*domain_free)(struct iommu_domain *); |
195 | ||
4a77a6cf JR |
196 | int (*attach_dev)(struct iommu_domain *domain, struct device *dev); |
197 | void (*detach_dev)(struct iommu_domain *domain, struct device *dev); | |
67651786 | 198 | int (*map)(struct iommu_domain *domain, unsigned long iova, |
5009065d OBC |
199 | phys_addr_t paddr, size_t size, int prot); |
200 | size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, | |
201 | size_t size); | |
add02cfd JR |
202 | void (*flush_iotlb_all)(struct iommu_domain *domain); |
203 | void (*iotlb_range_add)(struct iommu_domain *domain, | |
204 | unsigned long iova, size_t size); | |
205 | void (*iotlb_sync)(struct iommu_domain *domain); | |
bb5547ac | 206 | phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); |
d72e31c9 AW |
207 | int (*add_device)(struct device *dev); |
208 | void (*remove_device)(struct device *dev); | |
46c6b2bc | 209 | struct iommu_group *(*device_group)(struct device *dev); |
0cd76dd1 JR |
210 | int (*domain_get_attr)(struct iommu_domain *domain, |
211 | enum iommu_attr attr, void *data); | |
212 | int (*domain_set_attr)(struct iommu_domain *domain, | |
213 | enum iommu_attr attr, void *data); | |
d7787d57 | 214 | |
e5b5234a EA |
215 | /* Request/Free a list of reserved regions for a device */ |
216 | void (*get_resv_regions)(struct device *dev, struct list_head *list); | |
217 | void (*put_resv_regions)(struct device *dev, struct list_head *list); | |
218 | void (*apply_resv_region)(struct device *dev, | |
219 | struct iommu_domain *domain, | |
220 | struct iommu_resv_region *region); | |
a1015c2b | 221 | |
d7787d57 JR |
222 | /* Window handling functions */ |
223 | int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f | 224 | phys_addr_t paddr, u64 size, int prot); |
d7787d57 | 225 | void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr); |
0d9bacb6 | 226 | /* Set the number of windows per domain */ |
69356712 | 227 | int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count); |
0d9bacb6 | 228 | /* Get the number of windows per domain */ |
69356712 | 229 | u32 (*domain_get_windows)(struct iommu_domain *domain); |
d7787d57 | 230 | |
d0f60a44 | 231 | int (*of_xlate)(struct device *dev, struct of_phandle_args *args); |
e01d1913 | 232 | bool (*is_attach_deferred)(struct iommu_domain *domain, struct device *dev); |
d0f60a44 | 233 | |
7d3002cc | 234 | unsigned long pgsize_bitmap; |
4a77a6cf JR |
235 | }; |
236 | ||
b0119e87 JR |
237 | /** |
238 | * struct iommu_device - IOMMU core representation of one IOMMU hardware | |
239 | * instance | |
240 | * @list: Used by the iommu-core to keep a list of registered iommus | |
241 | * @ops: iommu-ops for talking to this iommu | |
39ab9555 | 242 | * @dev: struct device for sysfs handling |
b0119e87 JR |
243 | */ |
244 | struct iommu_device { | |
245 | struct list_head list; | |
246 | const struct iommu_ops *ops; | |
c73e1ac8 | 247 | struct fwnode_handle *fwnode; |
2926a2aa | 248 | struct device *dev; |
b0119e87 JR |
249 | }; |
250 | ||
251 | int iommu_device_register(struct iommu_device *iommu); | |
252 | void iommu_device_unregister(struct iommu_device *iommu); | |
39ab9555 JR |
253 | int iommu_device_sysfs_add(struct iommu_device *iommu, |
254 | struct device *parent, | |
255 | const struct attribute_group **groups, | |
256 | const char *fmt, ...) __printf(4, 5); | |
257 | void iommu_device_sysfs_remove(struct iommu_device *iommu); | |
e3d10af1 JR |
258 | int iommu_device_link(struct iommu_device *iommu, struct device *link); |
259 | void iommu_device_unlink(struct iommu_device *iommu, struct device *link); | |
b0119e87 JR |
260 | |
261 | static inline void iommu_device_set_ops(struct iommu_device *iommu, | |
262 | const struct iommu_ops *ops) | |
263 | { | |
264 | iommu->ops = ops; | |
265 | } | |
266 | ||
c73e1ac8 JR |
267 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
268 | struct fwnode_handle *fwnode) | |
269 | { | |
270 | iommu->fwnode = fwnode; | |
271 | } | |
272 | ||
2926a2aa JR |
273 | static inline struct iommu_device *dev_to_iommu_device(struct device *dev) |
274 | { | |
275 | return (struct iommu_device *)dev_get_drvdata(dev); | |
276 | } | |
277 | ||
d72e31c9 AW |
278 | #define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */ |
279 | #define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */ | |
280 | #define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */ | |
281 | #define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */ | |
282 | #define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */ | |
283 | #define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */ | |
284 | ||
b22f6434 | 285 | extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); |
a1b60c1c | 286 | extern bool iommu_present(struct bus_type *bus); |
3c0e0ca0 | 287 | extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); |
905d66c1 | 288 | extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); |
aa16bea9 | 289 | extern struct iommu_group *iommu_group_get_by_id(int id); |
4a77a6cf JR |
290 | extern void iommu_domain_free(struct iommu_domain *domain); |
291 | extern int iommu_attach_device(struct iommu_domain *domain, | |
292 | struct device *dev); | |
293 | extern void iommu_detach_device(struct iommu_domain *domain, | |
294 | struct device *dev); | |
2c1296d9 | 295 | extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); |
cefc53c7 | 296 | extern int iommu_map(struct iommu_domain *domain, unsigned long iova, |
7d3002cc OBC |
297 | phys_addr_t paddr, size_t size, int prot); |
298 | extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
add02cfd JR |
299 | size_t size); |
300 | extern size_t iommu_unmap_fast(struct iommu_domain *domain, | |
301 | unsigned long iova, size_t size); | |
d88e61fa CH |
302 | extern size_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, |
303 | struct scatterlist *sg,unsigned int nents, int prot); | |
bb5547ac | 304 | extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); |
4f3f8d9d | 305 | extern void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 306 | iommu_fault_handler_t handler, void *token); |
d72e31c9 | 307 | |
e5b5234a EA |
308 | extern void iommu_get_resv_regions(struct device *dev, struct list_head *list); |
309 | extern void iommu_put_resv_regions(struct device *dev, struct list_head *list); | |
d290f1e7 | 310 | extern int iommu_request_dm_for_dev(struct device *dev); |
2b20cbba | 311 | extern struct iommu_resv_region * |
9d3a4de4 RM |
312 | iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot, |
313 | enum iommu_resv_type type); | |
6c65fb31 EA |
314 | extern int iommu_get_group_resv_regions(struct iommu_group *group, |
315 | struct list_head *head); | |
a1015c2b | 316 | |
d72e31c9 AW |
317 | extern int iommu_attach_group(struct iommu_domain *domain, |
318 | struct iommu_group *group); | |
319 | extern void iommu_detach_group(struct iommu_domain *domain, | |
320 | struct iommu_group *group); | |
321 | extern struct iommu_group *iommu_group_alloc(void); | |
322 | extern void *iommu_group_get_iommudata(struct iommu_group *group); | |
323 | extern void iommu_group_set_iommudata(struct iommu_group *group, | |
324 | void *iommu_data, | |
325 | void (*release)(void *iommu_data)); | |
326 | extern int iommu_group_set_name(struct iommu_group *group, const char *name); | |
327 | extern int iommu_group_add_device(struct iommu_group *group, | |
328 | struct device *dev); | |
329 | extern void iommu_group_remove_device(struct device *dev); | |
330 | extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, | |
331 | int (*fn)(struct device *, void *)); | |
332 | extern struct iommu_group *iommu_group_get(struct device *dev); | |
13f59a78 | 333 | extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group); |
d72e31c9 AW |
334 | extern void iommu_group_put(struct iommu_group *group); |
335 | extern int iommu_group_register_notifier(struct iommu_group *group, | |
336 | struct notifier_block *nb); | |
337 | extern int iommu_group_unregister_notifier(struct iommu_group *group, | |
338 | struct notifier_block *nb); | |
339 | extern int iommu_group_id(struct iommu_group *group); | |
104a1c13 | 340 | extern struct iommu_group *iommu_group_get_for_dev(struct device *dev); |
6827ca83 | 341 | extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); |
4f3f8d9d | 342 | |
0cd76dd1 JR |
343 | extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, |
344 | void *data); | |
345 | extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, | |
346 | void *data); | |
4f3f8d9d | 347 | |
d7787d57 JR |
348 | /* Window handling function prototypes */ |
349 | extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f VS |
350 | phys_addr_t offset, u64 size, |
351 | int prot); | |
d7787d57 | 352 | extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr); |
207c6e36 JR |
353 | |
354 | extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev, | |
355 | unsigned long iova, int flags); | |
4a77a6cf | 356 | |
add02cfd JR |
357 | static inline void iommu_flush_tlb_all(struct iommu_domain *domain) |
358 | { | |
359 | if (domain->ops->flush_iotlb_all) | |
360 | domain->ops->flush_iotlb_all(domain); | |
361 | } | |
362 | ||
363 | static inline void iommu_tlb_range_add(struct iommu_domain *domain, | |
364 | unsigned long iova, size_t size) | |
365 | { | |
366 | if (domain->ops->iotlb_range_add) | |
367 | domain->ops->iotlb_range_add(domain, iova, size); | |
368 | } | |
369 | ||
370 | static inline void iommu_tlb_sync(struct iommu_domain *domain) | |
371 | { | |
372 | if (domain->ops->iotlb_sync) | |
373 | domain->ops->iotlb_sync(domain); | |
374 | } | |
375 | ||
5e62292b JR |
376 | /* PCI device grouping function */ |
377 | extern struct iommu_group *pci_device_group(struct device *dev); | |
6eab556a JR |
378 | /* Generic device grouping function */ |
379 | extern struct iommu_group *generic_device_group(struct device *dev); | |
5e62292b | 380 | |
57f98d2f RM |
381 | /** |
382 | * struct iommu_fwspec - per-device IOMMU instance data | |
383 | * @ops: ops for this device's IOMMU | |
384 | * @iommu_fwnode: firmware handle for this device's IOMMU | |
385 | * @iommu_priv: IOMMU driver private data for this device | |
386 | * @num_ids: number of associated device IDs | |
387 | * @ids: IDs which this device may present to the IOMMU | |
388 | */ | |
389 | struct iommu_fwspec { | |
390 | const struct iommu_ops *ops; | |
391 | struct fwnode_handle *iommu_fwnode; | |
392 | void *iommu_priv; | |
393 | unsigned int num_ids; | |
394 | u32 ids[1]; | |
395 | }; | |
396 | ||
397 | int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, | |
398 | const struct iommu_ops *ops); | |
399 | void iommu_fwspec_free(struct device *dev); | |
400 | int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); | |
534766df | 401 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); |
57f98d2f | 402 | |
4a77a6cf JR |
403 | #else /* CONFIG_IOMMU_API */ |
404 | ||
39d4ebb9 | 405 | struct iommu_ops {}; |
d72e31c9 | 406 | struct iommu_group {}; |
57f98d2f | 407 | struct iommu_fwspec {}; |
b0119e87 | 408 | struct iommu_device {}; |
4a77a6cf | 409 | |
a1b60c1c | 410 | static inline bool iommu_present(struct bus_type *bus) |
4a77a6cf JR |
411 | { |
412 | return false; | |
413 | } | |
414 | ||
3c0e0ca0 JR |
415 | static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap) |
416 | { | |
417 | return false; | |
418 | } | |
419 | ||
905d66c1 | 420 | static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus) |
4a77a6cf JR |
421 | { |
422 | return NULL; | |
423 | } | |
424 | ||
b62dfd29 AK |
425 | static inline struct iommu_group *iommu_group_get_by_id(int id) |
426 | { | |
427 | return NULL; | |
428 | } | |
429 | ||
4a77a6cf JR |
430 | static inline void iommu_domain_free(struct iommu_domain *domain) |
431 | { | |
432 | } | |
433 | ||
434 | static inline int iommu_attach_device(struct iommu_domain *domain, | |
435 | struct device *dev) | |
436 | { | |
437 | return -ENODEV; | |
438 | } | |
439 | ||
440 | static inline void iommu_detach_device(struct iommu_domain *domain, | |
441 | struct device *dev) | |
442 | { | |
443 | } | |
444 | ||
2c1296d9 JR |
445 | static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) |
446 | { | |
447 | return NULL; | |
448 | } | |
449 | ||
cefc53c7 | 450 | static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, |
ebae3e83 | 451 | phys_addr_t paddr, size_t size, int prot) |
cefc53c7 JR |
452 | { |
453 | return -ENODEV; | |
454 | } | |
455 | ||
c5611a87 SS |
456 | static inline size_t iommu_unmap(struct iommu_domain *domain, |
457 | unsigned long iova, size_t size) | |
cefc53c7 | 458 | { |
c5611a87 | 459 | return 0; |
cefc53c7 JR |
460 | } |
461 | ||
c5611a87 SS |
462 | static inline size_t iommu_unmap_fast(struct iommu_domain *domain, |
463 | unsigned long iova, int gfp_order) | |
cefc53c7 | 464 | { |
c5611a87 | 465 | return 0; |
cefc53c7 JR |
466 | } |
467 | ||
315786eb OH |
468 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
469 | unsigned long iova, struct scatterlist *sg, | |
470 | unsigned int nents, int prot) | |
471 | { | |
c5611a87 | 472 | return 0; |
315786eb OH |
473 | } |
474 | ||
add02cfd JR |
475 | static inline void iommu_flush_tlb_all(struct iommu_domain *domain) |
476 | { | |
477 | } | |
478 | ||
479 | static inline void iommu_tlb_range_add(struct iommu_domain *domain, | |
480 | unsigned long iova, size_t size) | |
481 | { | |
482 | } | |
483 | ||
484 | static inline void iommu_tlb_sync(struct iommu_domain *domain) | |
485 | { | |
486 | } | |
487 | ||
d7787d57 JR |
488 | static inline int iommu_domain_window_enable(struct iommu_domain *domain, |
489 | u32 wnd_nr, phys_addr_t paddr, | |
80f97f0f | 490 | u64 size, int prot) |
d7787d57 JR |
491 | { |
492 | return -ENODEV; | |
493 | } | |
494 | ||
495 | static inline void iommu_domain_window_disable(struct iommu_domain *domain, | |
496 | u32 wnd_nr) | |
497 | { | |
498 | } | |
499 | ||
bb5547ac | 500 | static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) |
4a77a6cf JR |
501 | { |
502 | return 0; | |
503 | } | |
504 | ||
4f3f8d9d | 505 | static inline void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 506 | iommu_fault_handler_t handler, void *token) |
4f3f8d9d OBC |
507 | { |
508 | } | |
509 | ||
e5b5234a | 510 | static inline void iommu_get_resv_regions(struct device *dev, |
a1015c2b JR |
511 | struct list_head *list) |
512 | { | |
513 | } | |
514 | ||
e5b5234a | 515 | static inline void iommu_put_resv_regions(struct device *dev, |
a1015c2b JR |
516 | struct list_head *list) |
517 | { | |
518 | } | |
519 | ||
6c65fb31 EA |
520 | static inline int iommu_get_group_resv_regions(struct iommu_group *group, |
521 | struct list_head *head) | |
522 | { | |
523 | return -ENODEV; | |
524 | } | |
525 | ||
d290f1e7 JR |
526 | static inline int iommu_request_dm_for_dev(struct device *dev) |
527 | { | |
528 | return -ENODEV; | |
529 | } | |
530 | ||
bef83de5 AW |
531 | static inline int iommu_attach_group(struct iommu_domain *domain, |
532 | struct iommu_group *group) | |
d72e31c9 AW |
533 | { |
534 | return -ENODEV; | |
535 | } | |
536 | ||
bef83de5 AW |
537 | static inline void iommu_detach_group(struct iommu_domain *domain, |
538 | struct iommu_group *group) | |
d72e31c9 AW |
539 | { |
540 | } | |
541 | ||
bef83de5 | 542 | static inline struct iommu_group *iommu_group_alloc(void) |
d72e31c9 AW |
543 | { |
544 | return ERR_PTR(-ENODEV); | |
545 | } | |
546 | ||
bef83de5 | 547 | static inline void *iommu_group_get_iommudata(struct iommu_group *group) |
d72e31c9 AW |
548 | { |
549 | return NULL; | |
550 | } | |
551 | ||
bef83de5 AW |
552 | static inline void iommu_group_set_iommudata(struct iommu_group *group, |
553 | void *iommu_data, | |
554 | void (*release)(void *iommu_data)) | |
d72e31c9 AW |
555 | { |
556 | } | |
557 | ||
bef83de5 AW |
558 | static inline int iommu_group_set_name(struct iommu_group *group, |
559 | const char *name) | |
d72e31c9 AW |
560 | { |
561 | return -ENODEV; | |
562 | } | |
563 | ||
bef83de5 AW |
564 | static inline int iommu_group_add_device(struct iommu_group *group, |
565 | struct device *dev) | |
d72e31c9 AW |
566 | { |
567 | return -ENODEV; | |
568 | } | |
569 | ||
bef83de5 | 570 | static inline void iommu_group_remove_device(struct device *dev) |
d72e31c9 AW |
571 | { |
572 | } | |
573 | ||
bef83de5 AW |
574 | static inline int iommu_group_for_each_dev(struct iommu_group *group, |
575 | void *data, | |
576 | int (*fn)(struct device *, void *)) | |
d72e31c9 AW |
577 | { |
578 | return -ENODEV; | |
579 | } | |
580 | ||
bef83de5 | 581 | static inline struct iommu_group *iommu_group_get(struct device *dev) |
d72e31c9 AW |
582 | { |
583 | return NULL; | |
584 | } | |
585 | ||
bef83de5 | 586 | static inline void iommu_group_put(struct iommu_group *group) |
d72e31c9 AW |
587 | { |
588 | } | |
589 | ||
bef83de5 AW |
590 | static inline int iommu_group_register_notifier(struct iommu_group *group, |
591 | struct notifier_block *nb) | |
1460432c AW |
592 | { |
593 | return -ENODEV; | |
594 | } | |
595 | ||
bef83de5 AW |
596 | static inline int iommu_group_unregister_notifier(struct iommu_group *group, |
597 | struct notifier_block *nb) | |
d72e31c9 AW |
598 | { |
599 | return 0; | |
600 | } | |
601 | ||
bef83de5 | 602 | static inline int iommu_group_id(struct iommu_group *group) |
d72e31c9 AW |
603 | { |
604 | return -ENODEV; | |
605 | } | |
1460432c | 606 | |
0cd76dd1 JR |
607 | static inline int iommu_domain_get_attr(struct iommu_domain *domain, |
608 | enum iommu_attr attr, void *data) | |
609 | { | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | static inline int iommu_domain_set_attr(struct iommu_domain *domain, | |
614 | enum iommu_attr attr, void *data) | |
615 | { | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
39ab9555 | 619 | static inline int iommu_device_register(struct iommu_device *iommu) |
c61959ec | 620 | { |
39ab9555 | 621 | return -ENODEV; |
c61959ec AW |
622 | } |
623 | ||
39ab9555 JR |
624 | static inline void iommu_device_set_ops(struct iommu_device *iommu, |
625 | const struct iommu_ops *ops) | |
c61959ec | 626 | { |
c61959ec AW |
627 | } |
628 | ||
c73e1ac8 JR |
629 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
630 | struct fwnode_handle *fwnode) | |
c61959ec | 631 | { |
c61959ec AW |
632 | } |
633 | ||
2926a2aa JR |
634 | static inline struct iommu_device *dev_to_iommu_device(struct device *dev) |
635 | { | |
636 | return NULL; | |
637 | } | |
638 | ||
39ab9555 | 639 | static inline void iommu_device_unregister(struct iommu_device *iommu) |
c61959ec | 640 | { |
c61959ec AW |
641 | } |
642 | ||
39ab9555 JR |
643 | static inline int iommu_device_sysfs_add(struct iommu_device *iommu, |
644 | struct device *parent, | |
645 | const struct attribute_group **groups, | |
646 | const char *fmt, ...) | |
b0119e87 | 647 | { |
39ab9555 | 648 | return -ENODEV; |
b0119e87 JR |
649 | } |
650 | ||
39ab9555 | 651 | static inline void iommu_device_sysfs_remove(struct iommu_device *iommu) |
c61959ec AW |
652 | { |
653 | } | |
654 | ||
e09f8ea5 | 655 | static inline int iommu_device_link(struct device *dev, struct device *link) |
c61959ec AW |
656 | { |
657 | return -EINVAL; | |
658 | } | |
659 | ||
e09f8ea5 | 660 | static inline void iommu_device_unlink(struct device *dev, struct device *link) |
c61959ec AW |
661 | { |
662 | } | |
663 | ||
57f98d2f RM |
664 | static inline int iommu_fwspec_init(struct device *dev, |
665 | struct fwnode_handle *iommu_fwnode, | |
666 | const struct iommu_ops *ops) | |
667 | { | |
668 | return -ENODEV; | |
669 | } | |
670 | ||
671 | static inline void iommu_fwspec_free(struct device *dev) | |
672 | { | |
673 | } | |
674 | ||
675 | static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, | |
676 | int num_ids) | |
677 | { | |
678 | return -ENODEV; | |
679 | } | |
680 | ||
e4f10ffe | 681 | static inline |
534766df | 682 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) |
e4f10ffe LP |
683 | { |
684 | return NULL; | |
685 | } | |
686 | ||
4a77a6cf JR |
687 | #endif /* CONFIG_IOMMU_API */ |
688 | ||
bad614b2 GH |
689 | #ifdef CONFIG_IOMMU_DEBUGFS |
690 | extern struct dentry *iommu_debugfs_dir; | |
691 | void iommu_debugfs_setup(void); | |
692 | #else | |
693 | static inline void iommu_debugfs_setup(void) {} | |
694 | #endif | |
695 | ||
4a77a6cf | 696 | #endif /* __LINUX_IOMMU_H */ |