]>
Commit | Line | Data |
---|---|---|
45051539 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
4a77a6cf JR |
2 | /* |
3 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
4 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4a77a6cf JR |
5 | */ |
6 | ||
7 | #ifndef __LINUX_IOMMU_H | |
8 | #define __LINUX_IOMMU_H | |
9 | ||
e8245c1b JR |
10 | #include <linux/scatterlist.h> |
11 | #include <linux/device.h> | |
12 | #include <linux/types.h> | |
74315ccc | 13 | #include <linux/errno.h> |
9a08d376 | 14 | #include <linux/err.h> |
d0f60a44 | 15 | #include <linux/of.h> |
4e32348b | 16 | #include <uapi/linux/iommu.h> |
74315ccc | 17 | |
ca13bb3d WD |
18 | #define IOMMU_READ (1 << 0) |
19 | #define IOMMU_WRITE (1 << 1) | |
20 | #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ | |
a720b41c | 21 | #define IOMMU_NOEXEC (1 << 3) |
31e6850e | 22 | #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ |
579b2a65 | 23 | /* |
adf5e516 RM |
24 | * Where the bus hardware includes a privilege level as part of its access type |
25 | * markings, and certain devices are capable of issuing transactions marked as | |
26 | * either 'supervisor' or 'user', the IOMMU_PRIV flag requests that the other | |
27 | * given permission flags only apply to accesses at the higher privilege level, | |
28 | * and that unprivileged transactions should have as little access as possible. | |
29 | * This would usually imply the same permissions as kernel mappings on the CPU, | |
30 | * if the IOMMU page table format is equivalent. | |
579b2a65 MH |
31 | */ |
32 | #define IOMMU_PRIV (1 << 5) | |
90ec7a76 VG |
33 | /* |
34 | * Non-coherent masters on few Qualcomm SoCs can use this page protection flag | |
35 | * to set correct cacheability attributes to use an outer level of cache - | |
36 | * last level cache, aka system cache. | |
37 | */ | |
38 | #define IOMMU_QCOM_SYS_CACHE (1 << 6) | |
4a77a6cf | 39 | |
905d66c1 | 40 | struct iommu_ops; |
d72e31c9 | 41 | struct iommu_group; |
ff21776d | 42 | struct bus_type; |
4a77a6cf | 43 | struct device; |
4f3f8d9d | 44 | struct iommu_domain; |
ba1eabfa | 45 | struct notifier_block; |
26b25a2b | 46 | struct iommu_sva; |
4e32348b | 47 | struct iommu_fault_event; |
4f3f8d9d OBC |
48 | |
49 | /* iommu fault flags */ | |
50 | #define IOMMU_FAULT_READ 0x0 | |
51 | #define IOMMU_FAULT_WRITE 0x1 | |
52 | ||
53 | typedef int (*iommu_fault_handler_t)(struct iommu_domain *, | |
77ca2332 | 54 | struct device *, unsigned long, int, void *); |
26b25a2b JPB |
55 | typedef int (*iommu_mm_exit_handler_t)(struct device *dev, struct iommu_sva *, |
56 | void *); | |
4e32348b | 57 | typedef int (*iommu_dev_fault_handler_t)(struct iommu_fault *, void *); |
4a77a6cf | 58 | |
0ff64f80 JR |
59 | struct iommu_domain_geometry { |
60 | dma_addr_t aperture_start; /* First address that can be mapped */ | |
61 | dma_addr_t aperture_end; /* Last address that can be mapped */ | |
62 | bool force_aperture; /* DMA only allowed in mappable range? */ | |
63 | }; | |
64 | ||
8539c7c1 JR |
65 | /* Domain feature flags */ |
66 | #define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */ | |
67 | #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API | |
68 | implementation */ | |
69 | #define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */ | |
70 | ||
71 | /* | |
72 | * This are the possible domain-types | |
73 | * | |
74 | * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate | |
75 | * devices | |
76 | * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses | |
77 | * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used | |
78 | * for VMs | |
79 | * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations. | |
80 | * This flag allows IOMMU drivers to implement | |
81 | * certain optimizations for these domains | |
82 | */ | |
83 | #define IOMMU_DOMAIN_BLOCKED (0U) | |
84 | #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) | |
85 | #define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING) | |
86 | #define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \ | |
87 | __IOMMU_DOMAIN_DMA_API) | |
88 | ||
4a77a6cf | 89 | struct iommu_domain { |
8539c7c1 | 90 | unsigned type; |
b22f6434 | 91 | const struct iommu_ops *ops; |
d16e0faa | 92 | unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */ |
4f3f8d9d | 93 | iommu_fault_handler_t handler; |
77ca2332 | 94 | void *handler_token; |
0ff64f80 | 95 | struct iommu_domain_geometry geometry; |
0db2e5d1 | 96 | void *iova_cookie; |
4a77a6cf JR |
97 | }; |
98 | ||
1aed0748 JR |
99 | enum iommu_cap { |
100 | IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA | |
101 | transactions */ | |
102 | IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ | |
c4986649 | 103 | IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ |
1aed0748 | 104 | }; |
dbb9fd86 | 105 | |
7cabf491 VS |
106 | /* |
107 | * Following constraints are specifc to FSL_PAMUV1: | |
108 | * -aperture must be power of 2, and naturally aligned | |
109 | * -number of windows must be power of 2, and address space size | |
110 | * of each window is determined by aperture size / # of windows | |
111 | * -the actual size of the mapped region of a window must be power | |
112 | * of 2 starting with 4KB and physical address must be naturally | |
113 | * aligned. | |
114 | * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. | |
115 | * The caller can invoke iommu_domain_get_attr to check if the underlying | |
116 | * iommu implementation supports these constraints. | |
117 | */ | |
118 | ||
0cd76dd1 | 119 | enum iommu_attr { |
0ff64f80 | 120 | DOMAIN_ATTR_GEOMETRY, |
d2e12160 | 121 | DOMAIN_ATTR_PAGING, |
69356712 | 122 | DOMAIN_ATTR_WINDOWS, |
7cabf491 VS |
123 | DOMAIN_ATTR_FSL_PAMU_STASH, |
124 | DOMAIN_ATTR_FSL_PAMU_ENABLE, | |
125 | DOMAIN_ATTR_FSL_PAMUV1, | |
c02607aa | 126 | DOMAIN_ATTR_NESTING, /* two stages of translation */ |
2da274cd | 127 | DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, |
a8b8a88a | 128 | DOMAIN_ATTR_MAX, |
0cd76dd1 JR |
129 | }; |
130 | ||
d30ddcaa | 131 | /* These are the possible reserved region types */ |
9d3a4de4 RM |
132 | enum iommu_resv_type { |
133 | /* Memory regions which must be mapped 1:1 at all times */ | |
134 | IOMMU_RESV_DIRECT, | |
adfd3738 EA |
135 | /* |
136 | * Memory regions which are advertised to be 1:1 but are | |
137 | * commonly considered relaxable in some conditions, | |
138 | * for instance in device assignment use case (USB, Graphics) | |
139 | */ | |
140 | IOMMU_RESV_DIRECT_RELAXABLE, | |
9d3a4de4 RM |
141 | /* Arbitrary "never map this or give it to a device" address ranges */ |
142 | IOMMU_RESV_RESERVED, | |
143 | /* Hardware MSI region (untranslated) */ | |
144 | IOMMU_RESV_MSI, | |
145 | /* Software-managed MSI translation window */ | |
146 | IOMMU_RESV_SW_MSI, | |
147 | }; | |
d30ddcaa | 148 | |
a1015c2b | 149 | /** |
e5b5234a | 150 | * struct iommu_resv_region - descriptor for a reserved memory region |
a1015c2b JR |
151 | * @list: Linked list pointers |
152 | * @start: System physical start address of the region | |
153 | * @length: Length of the region in bytes | |
154 | * @prot: IOMMU Protection flags (READ/WRITE/...) | |
d30ddcaa | 155 | * @type: Type of the reserved region |
a1015c2b | 156 | */ |
e5b5234a | 157 | struct iommu_resv_region { |
a1015c2b JR |
158 | struct list_head list; |
159 | phys_addr_t start; | |
160 | size_t length; | |
161 | int prot; | |
9d3a4de4 | 162 | enum iommu_resv_type type; |
a1015c2b JR |
163 | }; |
164 | ||
a3a19592 LB |
165 | /* Per device IOMMU features */ |
166 | enum iommu_dev_features { | |
167 | IOMMU_DEV_FEAT_AUX, /* Aux-domain feature */ | |
26b25a2b JPB |
168 | IOMMU_DEV_FEAT_SVA, /* Shared Virtual Addresses */ |
169 | }; | |
170 | ||
171 | #define IOMMU_PASID_INVALID (-1U) | |
172 | ||
173 | /** | |
174 | * struct iommu_sva_ops - device driver callbacks for an SVA context | |
175 | * | |
176 | * @mm_exit: called when the mm is about to be torn down by exit_mmap. After | |
177 | * @mm_exit returns, the device must not issue any more transaction | |
178 | * with the PASID given as argument. | |
179 | * | |
180 | * The @mm_exit handler is allowed to sleep. Be careful about the | |
181 | * locks taken in @mm_exit, because they might lead to deadlocks if | |
182 | * they are also held when dropping references to the mm. Consider the | |
183 | * following call chain: | |
184 | * mutex_lock(A); mmput(mm) -> exit_mm() -> @mm_exit() -> mutex_lock(A) | |
185 | * Using mmput_async() prevents this scenario. | |
186 | * | |
187 | */ | |
188 | struct iommu_sva_ops { | |
189 | iommu_mm_exit_handler_t mm_exit; | |
a3a19592 LB |
190 | }; |
191 | ||
39d4ebb9 JR |
192 | #ifdef CONFIG_IOMMU_API |
193 | ||
a7d20dc1 WD |
194 | /** |
195 | * struct iommu_iotlb_gather - Range information for a pending IOTLB flush | |
196 | * | |
197 | * @start: IOVA representing the start of the range to be flushed | |
198 | * @end: IOVA representing the end of the range to be flushed (exclusive) | |
199 | * @pgsize: The interval at which to perform the flush | |
200 | * | |
201 | * This structure is intended to be updated by multiple calls to the | |
202 | * ->unmap() function in struct iommu_ops before eventually being passed | |
203 | * into ->iotlb_sync(). | |
204 | */ | |
205 | struct iommu_iotlb_gather { | |
206 | unsigned long start; | |
207 | unsigned long end; | |
208 | size_t pgsize; | |
209 | }; | |
210 | ||
7d3002cc OBC |
211 | /** |
212 | * struct iommu_ops - iommu ops and capabilities | |
0d9bacb6 MD |
213 | * @capable: check capability |
214 | * @domain_alloc: allocate iommu domain | |
215 | * @domain_free: free iommu domain | |
7d3002cc OBC |
216 | * @attach_dev: attach device to an iommu domain |
217 | * @detach_dev: detach device from an iommu domain | |
218 | * @map: map a physically contiguous memory region to an iommu domain | |
219 | * @unmap: unmap a physically contiguous memory region from an iommu domain | |
db04d4a3 | 220 | * @flush_iotlb_all: Synchronously flush all hardware TLBs for this domain |
2405bc16 | 221 | * @iotlb_sync_map: Sync mappings created recently using @map to the hardware |
51eb7809 | 222 | * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush |
add02cfd | 223 | * queue |
7d3002cc | 224 | * @iova_to_phys: translate iova to physical address |
d72e31c9 AW |
225 | * @add_device: add device to iommu grouping |
226 | * @remove_device: remove device from iommu grouping | |
0d9bacb6 | 227 | * @device_group: find iommu group for a particular device |
0cd76dd1 JR |
228 | * @domain_get_attr: Query domain attributes |
229 | * @domain_set_attr: Change domain attributes | |
e5b5234a EA |
230 | * @get_resv_regions: Request list of reserved regions for a device |
231 | * @put_resv_regions: Free list of reserved regions for a device | |
232 | * @apply_resv_region: Temporary helper call-back for iova reserved ranges | |
0d9bacb6 MD |
233 | * @domain_window_enable: Configure and enable a particular window for a domain |
234 | * @domain_window_disable: Disable a particular window for a domain | |
d0f60a44 | 235 | * @of_xlate: add OF master IDs to iommu grouping |
a7055d57 GU |
236 | * @is_attach_deferred: Check if domain attach should be deferred from iommu |
237 | * driver init to device driver init (default no) | |
a3a19592 LB |
238 | * @dev_has/enable/disable_feat: per device entries to check/enable/disable |
239 | * iommu specific features. | |
240 | * @dev_feat_enabled: check enabled feature | |
241 | * @aux_attach/detach_dev: aux-domain specific attach/detach entries. | |
242 | * @aux_get_pasid: get the pasid given an aux-domain | |
26b25a2b JPB |
243 | * @sva_bind: Bind process address space to device |
244 | * @sva_unbind: Unbind process address space from device | |
245 | * @sva_get_pasid: Get PASID associated to a SVA handle | |
bf3255b3 | 246 | * @page_response: handle page request response |
d16e0faa | 247 | * @pgsize_bitmap: bitmap of all possible supported page sizes |
7d3002cc | 248 | */ |
4a77a6cf | 249 | struct iommu_ops { |
3c0e0ca0 | 250 | bool (*capable)(enum iommu_cap); |
938c4709 JR |
251 | |
252 | /* Domain allocation and freeing by the iommu driver */ | |
8539c7c1 | 253 | struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); |
938c4709 JR |
254 | void (*domain_free)(struct iommu_domain *); |
255 | ||
4a77a6cf JR |
256 | int (*attach_dev)(struct iommu_domain *domain, struct device *dev); |
257 | void (*detach_dev)(struct iommu_domain *domain, struct device *dev); | |
67651786 | 258 | int (*map)(struct iommu_domain *domain, unsigned long iova, |
5009065d OBC |
259 | phys_addr_t paddr, size_t size, int prot); |
260 | size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, | |
56f8af5e | 261 | size_t size, struct iommu_iotlb_gather *iotlb_gather); |
add02cfd | 262 | void (*flush_iotlb_all)(struct iommu_domain *domain); |
1d7ae53b | 263 | void (*iotlb_sync_map)(struct iommu_domain *domain); |
56f8af5e WD |
264 | void (*iotlb_sync)(struct iommu_domain *domain, |
265 | struct iommu_iotlb_gather *iotlb_gather); | |
bb5547ac | 266 | phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); |
d72e31c9 AW |
267 | int (*add_device)(struct device *dev); |
268 | void (*remove_device)(struct device *dev); | |
46c6b2bc | 269 | struct iommu_group *(*device_group)(struct device *dev); |
0cd76dd1 JR |
270 | int (*domain_get_attr)(struct iommu_domain *domain, |
271 | enum iommu_attr attr, void *data); | |
272 | int (*domain_set_attr)(struct iommu_domain *domain, | |
273 | enum iommu_attr attr, void *data); | |
d7787d57 | 274 | |
e5b5234a EA |
275 | /* Request/Free a list of reserved regions for a device */ |
276 | void (*get_resv_regions)(struct device *dev, struct list_head *list); | |
277 | void (*put_resv_regions)(struct device *dev, struct list_head *list); | |
278 | void (*apply_resv_region)(struct device *dev, | |
279 | struct iommu_domain *domain, | |
280 | struct iommu_resv_region *region); | |
a1015c2b | 281 | |
d7787d57 JR |
282 | /* Window handling functions */ |
283 | int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f | 284 | phys_addr_t paddr, u64 size, int prot); |
d7787d57 JR |
285 | void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr); |
286 | ||
d0f60a44 | 287 | int (*of_xlate)(struct device *dev, struct of_phandle_args *args); |
e01d1913 | 288 | bool (*is_attach_deferred)(struct iommu_domain *domain, struct device *dev); |
d0f60a44 | 289 | |
a3a19592 LB |
290 | /* Per device IOMMU features */ |
291 | bool (*dev_has_feat)(struct device *dev, enum iommu_dev_features f); | |
292 | bool (*dev_feat_enabled)(struct device *dev, enum iommu_dev_features f); | |
293 | int (*dev_enable_feat)(struct device *dev, enum iommu_dev_features f); | |
294 | int (*dev_disable_feat)(struct device *dev, enum iommu_dev_features f); | |
295 | ||
296 | /* Aux-domain specific attach/detach entries */ | |
297 | int (*aux_attach_dev)(struct iommu_domain *domain, struct device *dev); | |
298 | void (*aux_detach_dev)(struct iommu_domain *domain, struct device *dev); | |
299 | int (*aux_get_pasid)(struct iommu_domain *domain, struct device *dev); | |
300 | ||
26b25a2b JPB |
301 | struct iommu_sva *(*sva_bind)(struct device *dev, struct mm_struct *mm, |
302 | void *drvdata); | |
303 | void (*sva_unbind)(struct iommu_sva *handle); | |
304 | int (*sva_get_pasid)(struct iommu_sva *handle); | |
305 | ||
bf3255b3 JPB |
306 | int (*page_response)(struct device *dev, |
307 | struct iommu_fault_event *evt, | |
308 | struct iommu_page_response *msg); | |
309 | ||
7d3002cc | 310 | unsigned long pgsize_bitmap; |
4a77a6cf JR |
311 | }; |
312 | ||
b0119e87 JR |
313 | /** |
314 | * struct iommu_device - IOMMU core representation of one IOMMU hardware | |
315 | * instance | |
316 | * @list: Used by the iommu-core to keep a list of registered iommus | |
317 | * @ops: iommu-ops for talking to this iommu | |
39ab9555 | 318 | * @dev: struct device for sysfs handling |
b0119e87 JR |
319 | */ |
320 | struct iommu_device { | |
321 | struct list_head list; | |
322 | const struct iommu_ops *ops; | |
c73e1ac8 | 323 | struct fwnode_handle *fwnode; |
2926a2aa | 324 | struct device *dev; |
b0119e87 JR |
325 | }; |
326 | ||
4e32348b JP |
327 | /** |
328 | * struct iommu_fault_event - Generic fault event | |
329 | * | |
330 | * Can represent recoverable faults such as a page requests or | |
331 | * unrecoverable faults such as DMA or IRQ remapping faults. | |
332 | * | |
333 | * @fault: fault descriptor | |
bf3255b3 | 334 | * @list: pending fault event list, used for tracking responses |
4e32348b JP |
335 | */ |
336 | struct iommu_fault_event { | |
337 | struct iommu_fault fault; | |
bf3255b3 | 338 | struct list_head list; |
4e32348b JP |
339 | }; |
340 | ||
341 | /** | |
342 | * struct iommu_fault_param - per-device IOMMU fault data | |
343 | * @handler: Callback function to handle IOMMU faults at device level | |
344 | * @data: handler private data | |
bf3255b3 JPB |
345 | * @faults: holds the pending faults which needs response |
346 | * @lock: protect pending faults list | |
4e32348b JP |
347 | */ |
348 | struct iommu_fault_param { | |
349 | iommu_dev_fault_handler_t handler; | |
350 | void *data; | |
bf3255b3 JPB |
351 | struct list_head faults; |
352 | struct mutex lock; | |
4e32348b JP |
353 | }; |
354 | ||
355 | /** | |
356 | * struct iommu_param - collection of per-device IOMMU data | |
357 | * | |
358 | * @fault_param: IOMMU detected device fault reporting data | |
359 | * | |
360 | * TODO: migrate other per device data pointers under iommu_dev_data, e.g. | |
361 | * struct iommu_group *iommu_group; | |
362 | * struct iommu_fwspec *iommu_fwspec; | |
363 | */ | |
364 | struct iommu_param { | |
0c830e6b | 365 | struct mutex lock; |
4e32348b JP |
366 | struct iommu_fault_param *fault_param; |
367 | }; | |
368 | ||
b0119e87 JR |
369 | int iommu_device_register(struct iommu_device *iommu); |
370 | void iommu_device_unregister(struct iommu_device *iommu); | |
39ab9555 JR |
371 | int iommu_device_sysfs_add(struct iommu_device *iommu, |
372 | struct device *parent, | |
373 | const struct attribute_group **groups, | |
374 | const char *fmt, ...) __printf(4, 5); | |
375 | void iommu_device_sysfs_remove(struct iommu_device *iommu); | |
e3d10af1 JR |
376 | int iommu_device_link(struct iommu_device *iommu, struct device *link); |
377 | void iommu_device_unlink(struct iommu_device *iommu, struct device *link); | |
b0119e87 JR |
378 | |
379 | static inline void iommu_device_set_ops(struct iommu_device *iommu, | |
380 | const struct iommu_ops *ops) | |
381 | { | |
382 | iommu->ops = ops; | |
383 | } | |
384 | ||
c73e1ac8 JR |
385 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
386 | struct fwnode_handle *fwnode) | |
387 | { | |
388 | iommu->fwnode = fwnode; | |
389 | } | |
390 | ||
2926a2aa JR |
391 | static inline struct iommu_device *dev_to_iommu_device(struct device *dev) |
392 | { | |
393 | return (struct iommu_device *)dev_get_drvdata(dev); | |
394 | } | |
395 | ||
a7d20dc1 WD |
396 | static inline void iommu_iotlb_gather_init(struct iommu_iotlb_gather *gather) |
397 | { | |
398 | *gather = (struct iommu_iotlb_gather) { | |
399 | .start = ULONG_MAX, | |
400 | }; | |
401 | } | |
402 | ||
d72e31c9 AW |
403 | #define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */ |
404 | #define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */ | |
405 | #define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */ | |
406 | #define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */ | |
407 | #define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */ | |
408 | #define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */ | |
409 | ||
b22f6434 | 410 | extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); |
a1b60c1c | 411 | extern bool iommu_present(struct bus_type *bus); |
3c0e0ca0 | 412 | extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); |
905d66c1 | 413 | extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); |
aa16bea9 | 414 | extern struct iommu_group *iommu_group_get_by_id(int id); |
4a77a6cf JR |
415 | extern void iommu_domain_free(struct iommu_domain *domain); |
416 | extern int iommu_attach_device(struct iommu_domain *domain, | |
417 | struct device *dev); | |
418 | extern void iommu_detach_device(struct iommu_domain *domain, | |
419 | struct device *dev); | |
2c1296d9 | 420 | extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); |
6af588fe | 421 | extern struct iommu_domain *iommu_get_dma_domain(struct device *dev); |
cefc53c7 | 422 | extern int iommu_map(struct iommu_domain *domain, unsigned long iova, |
7d3002cc OBC |
423 | phys_addr_t paddr, size_t size, int prot); |
424 | extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
add02cfd JR |
425 | size_t size); |
426 | extern size_t iommu_unmap_fast(struct iommu_domain *domain, | |
a7d20dc1 WD |
427 | unsigned long iova, size_t size, |
428 | struct iommu_iotlb_gather *iotlb_gather); | |
d88e61fa CH |
429 | extern size_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, |
430 | struct scatterlist *sg,unsigned int nents, int prot); | |
bb5547ac | 431 | extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); |
4f3f8d9d | 432 | extern void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 433 | iommu_fault_handler_t handler, void *token); |
d72e31c9 | 434 | |
e5b5234a EA |
435 | extern void iommu_get_resv_regions(struct device *dev, struct list_head *list); |
436 | extern void iommu_put_resv_regions(struct device *dev, struct list_head *list); | |
d290f1e7 | 437 | extern int iommu_request_dm_for_dev(struct device *dev); |
7423e017 | 438 | extern int iommu_request_dma_domain_for_dev(struct device *dev); |
8a69961c JR |
439 | extern void iommu_set_default_passthrough(bool cmd_line); |
440 | extern void iommu_set_default_translated(bool cmd_line); | |
441 | extern bool iommu_default_passthrough(void); | |
2b20cbba | 442 | extern struct iommu_resv_region * |
9d3a4de4 RM |
443 | iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot, |
444 | enum iommu_resv_type type); | |
6c65fb31 EA |
445 | extern int iommu_get_group_resv_regions(struct iommu_group *group, |
446 | struct list_head *head); | |
a1015c2b | 447 | |
d72e31c9 AW |
448 | extern int iommu_attach_group(struct iommu_domain *domain, |
449 | struct iommu_group *group); | |
450 | extern void iommu_detach_group(struct iommu_domain *domain, | |
451 | struct iommu_group *group); | |
452 | extern struct iommu_group *iommu_group_alloc(void); | |
453 | extern void *iommu_group_get_iommudata(struct iommu_group *group); | |
454 | extern void iommu_group_set_iommudata(struct iommu_group *group, | |
455 | void *iommu_data, | |
456 | void (*release)(void *iommu_data)); | |
457 | extern int iommu_group_set_name(struct iommu_group *group, const char *name); | |
458 | extern int iommu_group_add_device(struct iommu_group *group, | |
459 | struct device *dev); | |
460 | extern void iommu_group_remove_device(struct device *dev); | |
461 | extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, | |
462 | int (*fn)(struct device *, void *)); | |
463 | extern struct iommu_group *iommu_group_get(struct device *dev); | |
13f59a78 | 464 | extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group); |
d72e31c9 AW |
465 | extern void iommu_group_put(struct iommu_group *group); |
466 | extern int iommu_group_register_notifier(struct iommu_group *group, | |
467 | struct notifier_block *nb); | |
468 | extern int iommu_group_unregister_notifier(struct iommu_group *group, | |
469 | struct notifier_block *nb); | |
0c830e6b JP |
470 | extern int iommu_register_device_fault_handler(struct device *dev, |
471 | iommu_dev_fault_handler_t handler, | |
472 | void *data); | |
473 | ||
474 | extern int iommu_unregister_device_fault_handler(struct device *dev); | |
475 | ||
476 | extern int iommu_report_device_fault(struct device *dev, | |
477 | struct iommu_fault_event *evt); | |
bf3255b3 JPB |
478 | extern int iommu_page_response(struct device *dev, |
479 | struct iommu_page_response *msg); | |
0c830e6b | 480 | |
d72e31c9 | 481 | extern int iommu_group_id(struct iommu_group *group); |
104a1c13 | 482 | extern struct iommu_group *iommu_group_get_for_dev(struct device *dev); |
6827ca83 | 483 | extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); |
4f3f8d9d | 484 | |
0cd76dd1 JR |
485 | extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, |
486 | void *data); | |
487 | extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, | |
488 | void *data); | |
4f3f8d9d | 489 | |
d7787d57 JR |
490 | /* Window handling function prototypes */ |
491 | extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f VS |
492 | phys_addr_t offset, u64 size, |
493 | int prot); | |
d7787d57 | 494 | extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr); |
207c6e36 JR |
495 | |
496 | extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev, | |
497 | unsigned long iova, int flags); | |
4a77a6cf | 498 | |
add02cfd JR |
499 | static inline void iommu_flush_tlb_all(struct iommu_domain *domain) |
500 | { | |
501 | if (domain->ops->flush_iotlb_all) | |
502 | domain->ops->flush_iotlb_all(domain); | |
503 | } | |
504 | ||
a7d20dc1 WD |
505 | static inline void iommu_tlb_sync(struct iommu_domain *domain, |
506 | struct iommu_iotlb_gather *iotlb_gather) | |
add02cfd JR |
507 | { |
508 | if (domain->ops->iotlb_sync) | |
56f8af5e | 509 | domain->ops->iotlb_sync(domain, iotlb_gather); |
a7d20dc1 WD |
510 | |
511 | iommu_iotlb_gather_init(iotlb_gather); | |
add02cfd JR |
512 | } |
513 | ||
4fcf8544 WD |
514 | static inline void iommu_iotlb_gather_add_page(struct iommu_domain *domain, |
515 | struct iommu_iotlb_gather *gather, | |
516 | unsigned long iova, size_t size) | |
517 | { | |
518 | unsigned long start = iova, end = start + size; | |
519 | ||
520 | /* | |
521 | * If the new page is disjoint from the current range or is mapped at | |
522 | * a different granularity, then sync the TLB so that the gather | |
523 | * structure can be rewritten. | |
524 | */ | |
525 | if (gather->pgsize != size || | |
526 | end < gather->start || start > gather->end) { | |
527 | if (gather->pgsize) | |
528 | iommu_tlb_sync(domain, gather); | |
529 | gather->pgsize = size; | |
530 | } | |
531 | ||
532 | if (gather->end < end) | |
533 | gather->end = end; | |
534 | ||
535 | if (gather->start > start) | |
536 | gather->start = start; | |
537 | } | |
538 | ||
5e62292b JR |
539 | /* PCI device grouping function */ |
540 | extern struct iommu_group *pci_device_group(struct device *dev); | |
6eab556a JR |
541 | /* Generic device grouping function */ |
542 | extern struct iommu_group *generic_device_group(struct device *dev); | |
eab03e2a NG |
543 | /* FSL-MC device grouping function */ |
544 | struct iommu_group *fsl_mc_device_group(struct device *dev); | |
5e62292b | 545 | |
57f98d2f RM |
546 | /** |
547 | * struct iommu_fwspec - per-device IOMMU instance data | |
548 | * @ops: ops for this device's IOMMU | |
549 | * @iommu_fwnode: firmware handle for this device's IOMMU | |
550 | * @iommu_priv: IOMMU driver private data for this device | |
551 | * @num_ids: number of associated device IDs | |
552 | * @ids: IDs which this device may present to the IOMMU | |
553 | */ | |
554 | struct iommu_fwspec { | |
555 | const struct iommu_ops *ops; | |
556 | struct fwnode_handle *iommu_fwnode; | |
557 | void *iommu_priv; | |
5702ee24 | 558 | u32 flags; |
57f98d2f RM |
559 | unsigned int num_ids; |
560 | u32 ids[1]; | |
561 | }; | |
562 | ||
5702ee24 JPB |
563 | /* ATS is supported */ |
564 | #define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) | |
565 | ||
26b25a2b JPB |
566 | /** |
567 | * struct iommu_sva - handle to a device-mm bond | |
568 | */ | |
569 | struct iommu_sva { | |
570 | struct device *dev; | |
571 | const struct iommu_sva_ops *ops; | |
572 | }; | |
573 | ||
57f98d2f RM |
574 | int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, |
575 | const struct iommu_ops *ops); | |
576 | void iommu_fwspec_free(struct device *dev); | |
577 | int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); | |
534766df | 578 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); |
57f98d2f | 579 | |
b4ef725e JR |
580 | static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) |
581 | { | |
582 | return dev->iommu_fwspec; | |
583 | } | |
584 | ||
585 | static inline void dev_iommu_fwspec_set(struct device *dev, | |
586 | struct iommu_fwspec *fwspec) | |
587 | { | |
588 | dev->iommu_fwspec = fwspec; | |
589 | } | |
590 | ||
cc5aed44 JR |
591 | int iommu_probe_device(struct device *dev); |
592 | void iommu_release_device(struct device *dev); | |
593 | ||
a3a19592 LB |
594 | bool iommu_dev_has_feature(struct device *dev, enum iommu_dev_features f); |
595 | int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features f); | |
596 | int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features f); | |
597 | bool iommu_dev_feature_enabled(struct device *dev, enum iommu_dev_features f); | |
598 | int iommu_aux_attach_device(struct iommu_domain *domain, struct device *dev); | |
599 | void iommu_aux_detach_device(struct iommu_domain *domain, struct device *dev); | |
600 | int iommu_aux_get_pasid(struct iommu_domain *domain, struct device *dev); | |
601 | ||
26b25a2b JPB |
602 | struct iommu_sva *iommu_sva_bind_device(struct device *dev, |
603 | struct mm_struct *mm, | |
604 | void *drvdata); | |
605 | void iommu_sva_unbind_device(struct iommu_sva *handle); | |
606 | int iommu_sva_set_ops(struct iommu_sva *handle, | |
607 | const struct iommu_sva_ops *ops); | |
608 | int iommu_sva_get_pasid(struct iommu_sva *handle); | |
609 | ||
4a77a6cf JR |
610 | #else /* CONFIG_IOMMU_API */ |
611 | ||
39d4ebb9 | 612 | struct iommu_ops {}; |
d72e31c9 | 613 | struct iommu_group {}; |
57f98d2f | 614 | struct iommu_fwspec {}; |
b0119e87 | 615 | struct iommu_device {}; |
4e32348b | 616 | struct iommu_fault_param {}; |
a7d20dc1 | 617 | struct iommu_iotlb_gather {}; |
4a77a6cf | 618 | |
a1b60c1c | 619 | static inline bool iommu_present(struct bus_type *bus) |
4a77a6cf JR |
620 | { |
621 | return false; | |
622 | } | |
623 | ||
3c0e0ca0 JR |
624 | static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap) |
625 | { | |
626 | return false; | |
627 | } | |
628 | ||
905d66c1 | 629 | static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus) |
4a77a6cf JR |
630 | { |
631 | return NULL; | |
632 | } | |
633 | ||
b62dfd29 AK |
634 | static inline struct iommu_group *iommu_group_get_by_id(int id) |
635 | { | |
636 | return NULL; | |
637 | } | |
638 | ||
4a77a6cf JR |
639 | static inline void iommu_domain_free(struct iommu_domain *domain) |
640 | { | |
641 | } | |
642 | ||
643 | static inline int iommu_attach_device(struct iommu_domain *domain, | |
644 | struct device *dev) | |
645 | { | |
646 | return -ENODEV; | |
647 | } | |
648 | ||
649 | static inline void iommu_detach_device(struct iommu_domain *domain, | |
650 | struct device *dev) | |
651 | { | |
652 | } | |
653 | ||
2c1296d9 JR |
654 | static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) |
655 | { | |
656 | return NULL; | |
657 | } | |
658 | ||
cefc53c7 | 659 | static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, |
ebae3e83 | 660 | phys_addr_t paddr, size_t size, int prot) |
cefc53c7 JR |
661 | { |
662 | return -ENODEV; | |
663 | } | |
664 | ||
c5611a87 SS |
665 | static inline size_t iommu_unmap(struct iommu_domain *domain, |
666 | unsigned long iova, size_t size) | |
cefc53c7 | 667 | { |
c5611a87 | 668 | return 0; |
cefc53c7 JR |
669 | } |
670 | ||
c5611a87 | 671 | static inline size_t iommu_unmap_fast(struct iommu_domain *domain, |
a7d20dc1 WD |
672 | unsigned long iova, int gfp_order, |
673 | struct iommu_iotlb_gather *iotlb_gather) | |
cefc53c7 | 674 | { |
c5611a87 | 675 | return 0; |
cefc53c7 JR |
676 | } |
677 | ||
315786eb OH |
678 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
679 | unsigned long iova, struct scatterlist *sg, | |
680 | unsigned int nents, int prot) | |
681 | { | |
c5611a87 | 682 | return 0; |
315786eb OH |
683 | } |
684 | ||
add02cfd JR |
685 | static inline void iommu_flush_tlb_all(struct iommu_domain *domain) |
686 | { | |
687 | } | |
688 | ||
a7d20dc1 WD |
689 | static inline void iommu_tlb_sync(struct iommu_domain *domain, |
690 | struct iommu_iotlb_gather *iotlb_gather) | |
add02cfd JR |
691 | { |
692 | } | |
693 | ||
d7787d57 JR |
694 | static inline int iommu_domain_window_enable(struct iommu_domain *domain, |
695 | u32 wnd_nr, phys_addr_t paddr, | |
80f97f0f | 696 | u64 size, int prot) |
d7787d57 JR |
697 | { |
698 | return -ENODEV; | |
699 | } | |
700 | ||
701 | static inline void iommu_domain_window_disable(struct iommu_domain *domain, | |
702 | u32 wnd_nr) | |
703 | { | |
704 | } | |
705 | ||
bb5547ac | 706 | static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) |
4a77a6cf JR |
707 | { |
708 | return 0; | |
709 | } | |
710 | ||
4f3f8d9d | 711 | static inline void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 712 | iommu_fault_handler_t handler, void *token) |
4f3f8d9d OBC |
713 | { |
714 | } | |
715 | ||
e5b5234a | 716 | static inline void iommu_get_resv_regions(struct device *dev, |
a1015c2b JR |
717 | struct list_head *list) |
718 | { | |
719 | } | |
720 | ||
e5b5234a | 721 | static inline void iommu_put_resv_regions(struct device *dev, |
a1015c2b JR |
722 | struct list_head *list) |
723 | { | |
724 | } | |
725 | ||
6c65fb31 EA |
726 | static inline int iommu_get_group_resv_regions(struct iommu_group *group, |
727 | struct list_head *head) | |
728 | { | |
729 | return -ENODEV; | |
730 | } | |
731 | ||
d290f1e7 JR |
732 | static inline int iommu_request_dm_for_dev(struct device *dev) |
733 | { | |
734 | return -ENODEV; | |
735 | } | |
736 | ||
7423e017 LB |
737 | static inline int iommu_request_dma_domain_for_dev(struct device *dev) |
738 | { | |
739 | return -ENODEV; | |
740 | } | |
741 | ||
8a69961c JR |
742 | static inline void iommu_set_default_passthrough(bool cmd_line) |
743 | { | |
744 | } | |
745 | ||
746 | static inline void iommu_set_default_translated(bool cmd_line) | |
747 | { | |
748 | } | |
749 | ||
750 | static inline bool iommu_default_passthrough(void) | |
751 | { | |
752 | return true; | |
753 | } | |
754 | ||
bef83de5 AW |
755 | static inline int iommu_attach_group(struct iommu_domain *domain, |
756 | struct iommu_group *group) | |
d72e31c9 AW |
757 | { |
758 | return -ENODEV; | |
759 | } | |
760 | ||
bef83de5 AW |
761 | static inline void iommu_detach_group(struct iommu_domain *domain, |
762 | struct iommu_group *group) | |
d72e31c9 AW |
763 | { |
764 | } | |
765 | ||
bef83de5 | 766 | static inline struct iommu_group *iommu_group_alloc(void) |
d72e31c9 AW |
767 | { |
768 | return ERR_PTR(-ENODEV); | |
769 | } | |
770 | ||
bef83de5 | 771 | static inline void *iommu_group_get_iommudata(struct iommu_group *group) |
d72e31c9 AW |
772 | { |
773 | return NULL; | |
774 | } | |
775 | ||
bef83de5 AW |
776 | static inline void iommu_group_set_iommudata(struct iommu_group *group, |
777 | void *iommu_data, | |
778 | void (*release)(void *iommu_data)) | |
d72e31c9 AW |
779 | { |
780 | } | |
781 | ||
bef83de5 AW |
782 | static inline int iommu_group_set_name(struct iommu_group *group, |
783 | const char *name) | |
d72e31c9 AW |
784 | { |
785 | return -ENODEV; | |
786 | } | |
787 | ||
bef83de5 AW |
788 | static inline int iommu_group_add_device(struct iommu_group *group, |
789 | struct device *dev) | |
d72e31c9 AW |
790 | { |
791 | return -ENODEV; | |
792 | } | |
793 | ||
bef83de5 | 794 | static inline void iommu_group_remove_device(struct device *dev) |
d72e31c9 AW |
795 | { |
796 | } | |
797 | ||
bef83de5 AW |
798 | static inline int iommu_group_for_each_dev(struct iommu_group *group, |
799 | void *data, | |
800 | int (*fn)(struct device *, void *)) | |
d72e31c9 AW |
801 | { |
802 | return -ENODEV; | |
803 | } | |
804 | ||
bef83de5 | 805 | static inline struct iommu_group *iommu_group_get(struct device *dev) |
d72e31c9 AW |
806 | { |
807 | return NULL; | |
808 | } | |
809 | ||
bef83de5 | 810 | static inline void iommu_group_put(struct iommu_group *group) |
d72e31c9 AW |
811 | { |
812 | } | |
813 | ||
bef83de5 AW |
814 | static inline int iommu_group_register_notifier(struct iommu_group *group, |
815 | struct notifier_block *nb) | |
1460432c AW |
816 | { |
817 | return -ENODEV; | |
818 | } | |
819 | ||
bef83de5 AW |
820 | static inline int iommu_group_unregister_notifier(struct iommu_group *group, |
821 | struct notifier_block *nb) | |
d72e31c9 AW |
822 | { |
823 | return 0; | |
824 | } | |
825 | ||
0c830e6b JP |
826 | static inline |
827 | int iommu_register_device_fault_handler(struct device *dev, | |
828 | iommu_dev_fault_handler_t handler, | |
829 | void *data) | |
830 | { | |
831 | return -ENODEV; | |
832 | } | |
833 | ||
834 | static inline int iommu_unregister_device_fault_handler(struct device *dev) | |
835 | { | |
836 | return 0; | |
837 | } | |
838 | ||
839 | static inline | |
840 | int iommu_report_device_fault(struct device *dev, struct iommu_fault_event *evt) | |
841 | { | |
842 | return -ENODEV; | |
843 | } | |
844 | ||
bf3255b3 JPB |
845 | static inline int iommu_page_response(struct device *dev, |
846 | struct iommu_page_response *msg) | |
847 | { | |
848 | return -ENODEV; | |
849 | } | |
850 | ||
bef83de5 | 851 | static inline int iommu_group_id(struct iommu_group *group) |
d72e31c9 AW |
852 | { |
853 | return -ENODEV; | |
854 | } | |
1460432c | 855 | |
0cd76dd1 JR |
856 | static inline int iommu_domain_get_attr(struct iommu_domain *domain, |
857 | enum iommu_attr attr, void *data) | |
858 | { | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | static inline int iommu_domain_set_attr(struct iommu_domain *domain, | |
863 | enum iommu_attr attr, void *data) | |
864 | { | |
865 | return -EINVAL; | |
866 | } | |
867 | ||
39ab9555 | 868 | static inline int iommu_device_register(struct iommu_device *iommu) |
c61959ec | 869 | { |
39ab9555 | 870 | return -ENODEV; |
c61959ec AW |
871 | } |
872 | ||
39ab9555 JR |
873 | static inline void iommu_device_set_ops(struct iommu_device *iommu, |
874 | const struct iommu_ops *ops) | |
c61959ec | 875 | { |
c61959ec AW |
876 | } |
877 | ||
c73e1ac8 JR |
878 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
879 | struct fwnode_handle *fwnode) | |
c61959ec | 880 | { |
c61959ec AW |
881 | } |
882 | ||
2926a2aa JR |
883 | static inline struct iommu_device *dev_to_iommu_device(struct device *dev) |
884 | { | |
885 | return NULL; | |
886 | } | |
887 | ||
a7d20dc1 WD |
888 | static inline void iommu_iotlb_gather_init(struct iommu_iotlb_gather *gather) |
889 | { | |
890 | } | |
891 | ||
4fcf8544 WD |
892 | static inline void iommu_iotlb_gather_add_page(struct iommu_domain *domain, |
893 | struct iommu_iotlb_gather *gather, | |
894 | unsigned long iova, size_t size) | |
895 | { | |
896 | } | |
897 | ||
39ab9555 | 898 | static inline void iommu_device_unregister(struct iommu_device *iommu) |
c61959ec | 899 | { |
c61959ec AW |
900 | } |
901 | ||
39ab9555 JR |
902 | static inline int iommu_device_sysfs_add(struct iommu_device *iommu, |
903 | struct device *parent, | |
904 | const struct attribute_group **groups, | |
905 | const char *fmt, ...) | |
b0119e87 | 906 | { |
39ab9555 | 907 | return -ENODEV; |
b0119e87 JR |
908 | } |
909 | ||
39ab9555 | 910 | static inline void iommu_device_sysfs_remove(struct iommu_device *iommu) |
c61959ec AW |
911 | { |
912 | } | |
913 | ||
e09f8ea5 | 914 | static inline int iommu_device_link(struct device *dev, struct device *link) |
c61959ec AW |
915 | { |
916 | return -EINVAL; | |
917 | } | |
918 | ||
e09f8ea5 | 919 | static inline void iommu_device_unlink(struct device *dev, struct device *link) |
c61959ec AW |
920 | { |
921 | } | |
922 | ||
57f98d2f RM |
923 | static inline int iommu_fwspec_init(struct device *dev, |
924 | struct fwnode_handle *iommu_fwnode, | |
925 | const struct iommu_ops *ops) | |
926 | { | |
927 | return -ENODEV; | |
928 | } | |
929 | ||
930 | static inline void iommu_fwspec_free(struct device *dev) | |
931 | { | |
932 | } | |
933 | ||
934 | static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, | |
935 | int num_ids) | |
936 | { | |
937 | return -ENODEV; | |
938 | } | |
939 | ||
e4f10ffe | 940 | static inline |
534766df | 941 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) |
e4f10ffe LP |
942 | { |
943 | return NULL; | |
944 | } | |
945 | ||
a3a19592 LB |
946 | static inline bool |
947 | iommu_dev_has_feature(struct device *dev, enum iommu_dev_features feat) | |
948 | { | |
949 | return false; | |
950 | } | |
951 | ||
952 | static inline bool | |
953 | iommu_dev_feature_enabled(struct device *dev, enum iommu_dev_features feat) | |
954 | { | |
955 | return false; | |
956 | } | |
957 | ||
958 | static inline int | |
959 | iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) | |
960 | { | |
961 | return -ENODEV; | |
962 | } | |
963 | ||
964 | static inline int | |
965 | iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) | |
966 | { | |
967 | return -ENODEV; | |
968 | } | |
969 | ||
970 | static inline int | |
971 | iommu_aux_attach_device(struct iommu_domain *domain, struct device *dev) | |
972 | { | |
973 | return -ENODEV; | |
974 | } | |
975 | ||
976 | static inline void | |
977 | iommu_aux_detach_device(struct iommu_domain *domain, struct device *dev) | |
978 | { | |
979 | } | |
980 | ||
981 | static inline int | |
982 | iommu_aux_get_pasid(struct iommu_domain *domain, struct device *dev) | |
983 | { | |
984 | return -ENODEV; | |
985 | } | |
986 | ||
26b25a2b JPB |
987 | static inline struct iommu_sva * |
988 | iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, void *drvdata) | |
989 | { | |
990 | return NULL; | |
991 | } | |
992 | ||
993 | static inline void iommu_sva_unbind_device(struct iommu_sva *handle) | |
994 | { | |
995 | } | |
996 | ||
997 | static inline int iommu_sva_set_ops(struct iommu_sva *handle, | |
998 | const struct iommu_sva_ops *ops) | |
999 | { | |
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
1003 | static inline int iommu_sva_get_pasid(struct iommu_sva *handle) | |
1004 | { | |
1005 | return IOMMU_PASID_INVALID; | |
1006 | } | |
1007 | ||
4a77a6cf JR |
1008 | #endif /* CONFIG_IOMMU_API */ |
1009 | ||
bad614b2 GH |
1010 | #ifdef CONFIG_IOMMU_DEBUGFS |
1011 | extern struct dentry *iommu_debugfs_dir; | |
1012 | void iommu_debugfs_setup(void); | |
1013 | #else | |
1014 | static inline void iommu_debugfs_setup(void) {} | |
1015 | #endif | |
1016 | ||
4a77a6cf | 1017 | #endif /* __LINUX_IOMMU_H */ |