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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
3aa551c9 | 25 | #include <linux/wait.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
ab7798ff | 31 | struct seq_file; |
57a58a94 | 32 | struct irq_desc; |
78129576 | 33 | struct irq_data; |
ec701584 | 34 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 35 | struct irq_desc *desc); |
78129576 | 36 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 37 | |
1da177e4 LT |
38 | /* |
39 | * IRQ line status. | |
6e213616 | 40 | * |
5d4d8fc9 TG |
41 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
42 | * | |
43 | * IRQ_TYPE_NONE - default, unspecified type | |
44 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
45 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
46 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
47 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
48 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
49 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
50 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
51 | * IRQ_TYPE_PROBE - Special flag for probing in progress | |
52 | * | |
53 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
54 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
55 | * updated in the code when the above trigger | |
56 | * bits are modified via set_irq_type() | |
57 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect | |
58 | * it from affinity setting | |
59 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
60 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
61 | * request_irq() | |
62 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in | |
63 | * request/setup_irq() | |
64 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
65 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
66 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
1da177e4 | 67 | */ |
5d4d8fc9 TG |
68 | enum { |
69 | IRQ_TYPE_NONE = 0x00000000, | |
70 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
71 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
72 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
73 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
74 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
75 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
76 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
77 | ||
78 | IRQ_TYPE_PROBE = 0x00000010, | |
79 | ||
80 | IRQ_LEVEL = (1 << 8), | |
81 | IRQ_PER_CPU = (1 << 9), | |
82 | IRQ_NOPROBE = (1 << 10), | |
83 | IRQ_NOREQUEST = (1 << 11), | |
84 | IRQ_NOAUTOEN = (1 << 12), | |
85 | IRQ_NO_BALANCING = (1 << 13), | |
86 | IRQ_MOVE_PCNTXT = (1 << 14), | |
87 | IRQ_NESTED_THREAD = (1 << 15), | |
5d4d8fc9 | 88 | }; |
950f4427 | 89 | |
44247184 TG |
90 | #define IRQF_MODIFY_MASK \ |
91 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 92 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
6f91a52d | 93 | IRQ_PER_CPU | IRQ_NESTED_THREAD) |
44247184 | 94 | |
8f53f924 TG |
95 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
96 | ||
97 | static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status) | |
98 | { | |
99 | return status & IRQ_PER_CPU; | |
100 | } | |
1da177e4 | 101 | |
3b8249e7 TG |
102 | /* |
103 | * Return value for chip->irq_set_affinity() | |
104 | * | |
105 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
106 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
107 | */ | |
108 | enum { | |
109 | IRQ_SET_MASK_OK = 0, | |
110 | IRQ_SET_MASK_OK_NOCOPY, | |
111 | }; | |
112 | ||
5b912c10 | 113 | struct msi_desc; |
6a6de9ef | 114 | |
ff7dcd44 TG |
115 | /** |
116 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
117 | * @irq: interrupt number | |
118 | * @node: node index useful for balancing | |
30398bf6 | 119 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 120 | * Use accessor functions to deal with it |
ff7dcd44 TG |
121 | * @chip: low level interrupt hardware access |
122 | * @handler_data: per-IRQ data for the irq_chip methods | |
123 | * @chip_data: platform-specific per-chip private data for the chip | |
124 | * methods, to allow shared chip implementations | |
125 | * @msi_desc: MSI descriptor | |
126 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
127 | * |
128 | * The fields here need to overlay the ones in irq_desc until we | |
129 | * cleaned up the direct references and switched everything over to | |
130 | * irq_data. | |
131 | */ | |
132 | struct irq_data { | |
133 | unsigned int irq; | |
134 | unsigned int node; | |
91c49917 | 135 | unsigned int state_use_accessors; |
ff7dcd44 TG |
136 | struct irq_chip *chip; |
137 | void *handler_data; | |
138 | void *chip_data; | |
139 | struct msi_desc *msi_desc; | |
140 | #ifdef CONFIG_SMP | |
141 | cpumask_var_t affinity; | |
142 | #endif | |
ff7dcd44 TG |
143 | }; |
144 | ||
f230b6d5 TG |
145 | /* |
146 | * Bit masks for irq_data.state | |
147 | * | |
876dbd4c | 148 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 149 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
150 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
151 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 152 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 153 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
154 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
155 | * from suspend | |
e1ef8241 TG |
156 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
157 | * context | |
32f4125e TG |
158 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
159 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
160 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
f230b6d5 TG |
161 | */ |
162 | enum { | |
876dbd4c | 163 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
164 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
165 | IRQD_NO_BALANCING = (1 << 10), | |
166 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 167 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 168 | IRQD_LEVEL = (1 << 13), |
7f94226f | 169 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 170 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 171 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
172 | IRQD_IRQ_MASKED = (1 << 17), |
173 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
f230b6d5 TG |
174 | }; |
175 | ||
176 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
177 | { | |
178 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
179 | } | |
180 | ||
a005677b TG |
181 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
182 | { | |
183 | return d->state_use_accessors & IRQD_PER_CPU; | |
184 | } | |
185 | ||
186 | static inline bool irqd_can_balance(struct irq_data *d) | |
187 | { | |
188 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
189 | } | |
190 | ||
2bdd1055 TG |
191 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
192 | { | |
193 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
194 | } | |
195 | ||
ee38c04b TG |
196 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
197 | { | |
198 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
199 | } | |
200 | ||
876dbd4c TG |
201 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
202 | { | |
203 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
204 | } | |
205 | ||
206 | /* | |
207 | * Must only be called inside irq_chip.irq_set_type() functions. | |
208 | */ | |
209 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
210 | { | |
211 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
212 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
213 | } | |
214 | ||
215 | static inline bool irqd_is_level_type(struct irq_data *d) | |
216 | { | |
217 | return d->state_use_accessors & IRQD_LEVEL; | |
218 | } | |
219 | ||
7f94226f TG |
220 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
221 | { | |
222 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
223 | } | |
224 | ||
e1ef8241 TG |
225 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
226 | { | |
227 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
228 | } | |
229 | ||
801a0e9a TG |
230 | static inline bool irqd_irq_disabled(struct irq_data *d) |
231 | { | |
232 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
233 | } | |
234 | ||
32f4125e TG |
235 | static inline bool irqd_irq_masked(struct irq_data *d) |
236 | { | |
237 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
238 | } | |
239 | ||
240 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
241 | { | |
242 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
243 | } | |
244 | ||
9cff60df TG |
245 | /* |
246 | * Functions for chained handlers which can be enabled/disabled by the | |
247 | * standard disable_irq/enable_irq calls. Must be called with | |
248 | * irq_desc->lock held. | |
249 | */ | |
250 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
251 | { | |
252 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
253 | } | |
254 | ||
255 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
256 | { | |
257 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
258 | } | |
259 | ||
8fee5c36 | 260 | /** |
6a6de9ef | 261 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
262 | * |
263 | * @name: name for /proc/interrupts | |
f8822657 TG |
264 | * @startup: deprecated, replaced by irq_startup |
265 | * @shutdown: deprecated, replaced by irq_shutdown | |
266 | * @enable: deprecated, replaced by irq_enable | |
267 | * @disable: deprecated, replaced by irq_disable | |
268 | * @ack: deprecated, replaced by irq_ack | |
269 | * @mask: deprecated, replaced by irq_mask | |
270 | * @mask_ack: deprecated, replaced by irq_mask_ack | |
271 | * @unmask: deprecated, replaced by irq_unmask | |
272 | * @eoi: deprecated, replaced by irq_eoi | |
273 | * @end: deprecated, will go away with __do_IRQ() | |
274 | * @set_affinity: deprecated, replaced by irq_set_affinity | |
275 | * @retrigger: deprecated, replaced by irq_retrigger | |
276 | * @set_type: deprecated, replaced by irq_set_type | |
277 | * @set_wake: deprecated, replaced by irq_wake | |
278 | * @bus_lock: deprecated, replaced by irq_bus_lock | |
279 | * @bus_sync_unlock: deprecated, replaced by irq_bus_sync_unlock | |
8fee5c36 | 280 | * |
f8822657 TG |
281 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
282 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
283 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
284 | * @irq_disable: disable the interrupt | |
285 | * @irq_ack: start of a new interrupt | |
286 | * @irq_mask: mask an interrupt source | |
287 | * @irq_mask_ack: ack and mask an interrupt source | |
288 | * @irq_unmask: unmask an interrupt source | |
289 | * @irq_eoi: end of interrupt | |
290 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
291 | * @irq_retrigger: resend an IRQ to the CPU | |
292 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
293 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
294 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
295 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
296 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
297 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
ab7798ff | 298 | * @irq_print_chip: optional to print special chip info in show_interrupts |
2bff17ad | 299 | * @flags: chip specific flags |
70aedd24 | 300 | * |
8fee5c36 | 301 | * @release: release function solely used by UML |
1da177e4 | 302 | */ |
6a6de9ef TG |
303 | struct irq_chip { |
304 | const char *name; | |
f8822657 TG |
305 | unsigned int (*irq_startup)(struct irq_data *data); |
306 | void (*irq_shutdown)(struct irq_data *data); | |
307 | void (*irq_enable)(struct irq_data *data); | |
308 | void (*irq_disable)(struct irq_data *data); | |
309 | ||
310 | void (*irq_ack)(struct irq_data *data); | |
311 | void (*irq_mask)(struct irq_data *data); | |
312 | void (*irq_mask_ack)(struct irq_data *data); | |
313 | void (*irq_unmask)(struct irq_data *data); | |
314 | void (*irq_eoi)(struct irq_data *data); | |
315 | ||
316 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
317 | int (*irq_retrigger)(struct irq_data *data); | |
318 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
319 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
320 | ||
321 | void (*irq_bus_lock)(struct irq_data *data); | |
322 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
323 | ||
0fdb4b25 DD |
324 | void (*irq_cpu_online)(struct irq_data *data); |
325 | void (*irq_cpu_offline)(struct irq_data *data); | |
326 | ||
ab7798ff TG |
327 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
328 | ||
2bff17ad TG |
329 | unsigned long flags; |
330 | ||
b77d6adc PBG |
331 | /* Currently used only by UML, might disappear one day.*/ |
332 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 333 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 334 | #endif |
1da177e4 LT |
335 | }; |
336 | ||
d4d5e089 TG |
337 | /* |
338 | * irq_chip specific flags | |
339 | * | |
77694b40 TG |
340 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
341 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 342 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
343 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
344 | * when irq enabled | |
d4d5e089 TG |
345 | */ |
346 | enum { | |
347 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 348 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 349 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 350 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
d4d5e089 TG |
351 | }; |
352 | ||
e144710b TG |
353 | /* This include will go away once we isolated irq_desc usage to core code */ |
354 | #include <linux/irqdesc.h> | |
0b8f1efa | 355 | |
34ffdb72 IM |
356 | /* |
357 | * Pick up the arch-dependent methods: | |
358 | */ | |
359 | #include <asm/hw_irq.h> | |
1da177e4 | 360 | |
b683de2b TG |
361 | #ifndef NR_IRQS_LEGACY |
362 | # define NR_IRQS_LEGACY 0 | |
363 | #endif | |
364 | ||
1318a481 TG |
365 | #ifndef ARCH_IRQ_INIT_FLAGS |
366 | # define ARCH_IRQ_INIT_FLAGS 0 | |
367 | #endif | |
368 | ||
c1594b77 | 369 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 370 | |
e144710b | 371 | struct irqaction; |
06fcb0c6 | 372 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 373 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
1da177e4 | 374 | |
0fdb4b25 DD |
375 | extern void irq_cpu_online(void); |
376 | extern void irq_cpu_offline(void); | |
c2d0c555 | 377 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
0fdb4b25 | 378 | |
1da177e4 | 379 | #ifdef CONFIG_GENERIC_HARDIRQS |
06fcb0c6 | 380 | |
3a3856d0 | 381 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
382 | void irq_move_irq(struct irq_data *data); |
383 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 384 | #else |
a439520f TG |
385 | static inline void irq_move_irq(struct irq_data *data) { } |
386 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 387 | #endif |
54d5d424 | 388 | |
1da177e4 | 389 | extern int no_irq_affinity; |
1da177e4 | 390 | |
6a6de9ef TG |
391 | /* |
392 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 393 | * callable via desc->handle_irq() |
6a6de9ef | 394 | */ |
ec701584 HH |
395 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
396 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
397 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 398 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
399 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
400 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
401 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); | |
31b47cf7 | 402 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 403 | |
6a6de9ef | 404 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 405 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 406 | irqreturn_t action_ret); |
1da177e4 | 407 | |
a4633adc | 408 | |
6a6de9ef TG |
409 | /* Enable/disable irq debugging output: */ |
410 | extern int noirqdebug_setup(char *str); | |
411 | ||
412 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
413 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
414 | ||
f8b5473f | 415 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 416 | extern struct irq_chip no_irq_chip; |
f8b5473f | 417 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 418 | |
145fc655 | 419 | extern void |
3836ca08 | 420 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
421 | irq_flow_handler_t handle, const char *name); |
422 | ||
3836ca08 TG |
423 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
424 | irq_flow_handler_t handle) | |
425 | { | |
426 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
427 | } | |
428 | ||
6a6de9ef | 429 | extern void |
3836ca08 | 430 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 431 | const char *name); |
1da177e4 | 432 | |
6a6de9ef | 433 | static inline void |
3836ca08 | 434 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 435 | { |
3836ca08 | 436 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
437 | } |
438 | ||
439 | /* | |
440 | * Set a highlevel chained flow handler for a given IRQ. | |
441 | * (a chained handler is automatically enabled and set to | |
442 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
443 | */ | |
444 | static inline void | |
3836ca08 | 445 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 446 | { |
3836ca08 | 447 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
448 | } |
449 | ||
44247184 TG |
450 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
451 | ||
452 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
453 | { | |
454 | irq_modify_status(irq, 0, set); | |
455 | } | |
456 | ||
457 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
458 | { | |
459 | irq_modify_status(irq, clr, 0); | |
460 | } | |
461 | ||
a0cd9ca2 | 462 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
463 | { |
464 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
465 | } | |
466 | ||
a0cd9ca2 | 467 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
468 | { |
469 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
470 | } | |
46f4f8f6 | 471 | |
6f91a52d TG |
472 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
473 | { | |
474 | if (nest) | |
475 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
476 | else | |
477 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
478 | } | |
479 | ||
3a16d713 | 480 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 481 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
3a16d713 EB |
482 | extern int create_irq(void); |
483 | extern void destroy_irq(unsigned int irq); | |
484 | ||
b7b29338 TG |
485 | /* |
486 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and | |
487 | * irq_free_desc instead. | |
488 | */ | |
3a16d713 | 489 | extern void dynamic_irq_cleanup(unsigned int irq); |
b7b29338 TG |
490 | static inline void dynamic_irq_init(unsigned int irq) |
491 | { | |
492 | dynamic_irq_cleanup(irq); | |
493 | } | |
dd87eb3a | 494 | |
3a16d713 | 495 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
496 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
497 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
498 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
499 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
500 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
f303a6dd | 501 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 502 | |
a0cd9ca2 | 503 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
504 | { |
505 | struct irq_data *d = irq_get_irq_data(irq); | |
506 | return d ? d->chip : NULL; | |
507 | } | |
508 | ||
509 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
510 | { | |
511 | return d->chip; | |
512 | } | |
513 | ||
a0cd9ca2 | 514 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
515 | { |
516 | struct irq_data *d = irq_get_irq_data(irq); | |
517 | return d ? d->chip_data : NULL; | |
518 | } | |
519 | ||
520 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
521 | { | |
522 | return d->chip_data; | |
523 | } | |
524 | ||
a0cd9ca2 | 525 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
526 | { |
527 | struct irq_data *d = irq_get_irq_data(irq); | |
528 | return d ? d->handler_data : NULL; | |
529 | } | |
530 | ||
a0cd9ca2 | 531 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
532 | { |
533 | return d->handler_data; | |
534 | } | |
535 | ||
a0cd9ca2 | 536 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
537 | { |
538 | struct irq_data *d = irq_get_irq_data(irq); | |
539 | return d ? d->msi_desc : NULL; | |
540 | } | |
541 | ||
542 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
543 | { | |
544 | return d->msi_desc; | |
545 | } | |
546 | ||
1f5a5b87 TG |
547 | int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node); |
548 | void irq_free_descs(unsigned int irq, unsigned int cnt); | |
06f6c339 | 549 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); |
1f5a5b87 TG |
550 | |
551 | static inline int irq_alloc_desc(int node) | |
552 | { | |
553 | return irq_alloc_descs(-1, 0, 1, node); | |
554 | } | |
555 | ||
556 | static inline int irq_alloc_desc_at(unsigned int at, int node) | |
557 | { | |
558 | return irq_alloc_descs(at, at, 1, node); | |
559 | } | |
560 | ||
561 | static inline int irq_alloc_desc_from(unsigned int from, int node) | |
562 | { | |
563 | return irq_alloc_descs(-1, from, 1, node); | |
564 | } | |
565 | ||
566 | static inline void irq_free_desc(unsigned int irq) | |
567 | { | |
568 | irq_free_descs(irq, 1); | |
569 | } | |
570 | ||
639bd12f PM |
571 | static inline int irq_reserve_irq(unsigned int irq) |
572 | { | |
573 | return irq_reserve_irqs(irq, 1); | |
574 | } | |
575 | ||
6a6de9ef | 576 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 577 | |
06fcb0c6 | 578 | #endif /* !CONFIG_S390 */ |
1da177e4 | 579 | |
06fcb0c6 | 580 | #endif /* _LINUX_IRQ_H */ |