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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
06fcb0c6 IM |
2 | #ifndef _LINUX_IRQ_H |
3 | #define _LINUX_IRQ_H | |
1da177e4 LT |
4 | |
5 | /* | |
6 | * Please do not include this file in generic code. There is currently | |
7 | * no requirement for any architecture to implement anything held | |
8 | * within this file. | |
9 | * | |
10 | * Thanks. --rmk | |
11 | */ | |
12 | ||
1da177e4 LT |
13 | #include <linux/cache.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/cpumask.h> | |
75ffc007 | 16 | #include <linux/irqhandler.h> |
908dcecd | 17 | #include <linux/irqreturn.h> |
dd3a1db9 | 18 | #include <linux/irqnr.h> |
503e5763 | 19 | #include <linux/topology.h> |
332fd7c4 | 20 | #include <linux/io.h> |
707188f5 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include <asm/irq.h> | |
24 | #include <asm/ptrace.h> | |
7d12e780 | 25 | #include <asm/irq_regs.h> |
1da177e4 | 26 | |
ab7798ff | 27 | struct seq_file; |
ec53cf23 | 28 | struct module; |
515085ef | 29 | struct msi_msg; |
bec04037 | 30 | struct irq_affinity_desc; |
1b7047ed | 31 | enum irqchip_irq_state; |
57a58a94 | 32 | |
1da177e4 LT |
33 | /* |
34 | * IRQ line status. | |
6e213616 | 35 | * |
5d4d8fc9 TG |
36 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
37 | * | |
38 | * IRQ_TYPE_NONE - default, unspecified type | |
39 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
40 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
41 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
42 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
43 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
44 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
45 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
46 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
47 | * to setup the HW to a sane default (used | |
48 | * by irqdomain map() callbacks to synchronize | |
49 | * the HW state and SW flags for a newly | |
50 | * allocated descriptor). | |
51 | * | |
5d4d8fc9 TG |
52 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
53 | * | |
54 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
55 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
56 | * updated in the code when the above trigger | |
0911f124 | 57 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
58 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
59 | * it from affinity setting | |
60 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
61 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
62 | * request_irq() | |
7f1b1244 | 63 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
64 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
65 | * request/setup_irq() | |
66 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
67 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
92068d17 | 68 | * IRQ_NESTED_THREAD - Interrupt nests into another thread |
31d9d9b6 | 69 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
70 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
71 | * it from the spurious interrupt detection | |
72 | * mechanism and from core side polling. | |
e9849777 | 73 | * IRQ_DISABLE_UNLAZY - Disable lazy irq disable |
83cfac95 | 74 | * IRQ_HIDDEN - Don't show up in /proc/interrupts |
1da177e4 | 75 | */ |
5d4d8fc9 TG |
76 | enum { |
77 | IRQ_TYPE_NONE = 0x00000000, | |
78 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
79 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
80 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
81 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
82 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
83 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
84 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 85 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
86 | |
87 | IRQ_TYPE_PROBE = 0x00000010, | |
88 | ||
89 | IRQ_LEVEL = (1 << 8), | |
90 | IRQ_PER_CPU = (1 << 9), | |
91 | IRQ_NOPROBE = (1 << 10), | |
92 | IRQ_NOREQUEST = (1 << 11), | |
93 | IRQ_NOAUTOEN = (1 << 12), | |
94 | IRQ_NO_BALANCING = (1 << 13), | |
95 | IRQ_MOVE_PCNTXT = (1 << 14), | |
96 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 97 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 98 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 99 | IRQ_IS_POLLED = (1 << 18), |
e9849777 | 100 | IRQ_DISABLE_UNLAZY = (1 << 19), |
83cfac95 | 101 | IRQ_HIDDEN = (1 << 20), |
5d4d8fc9 | 102 | }; |
950f4427 | 103 | |
44247184 TG |
104 | #define IRQF_MODIFY_MASK \ |
105 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 106 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd | 107 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
83cfac95 | 108 | IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) |
44247184 | 109 | |
8f53f924 TG |
110 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
111 | ||
3b8249e7 TG |
112 | /* |
113 | * Return value for chip->irq_set_affinity() | |
114 | * | |
9df872fa JL |
115 | * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity |
116 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity | |
2cb62547 JL |
117 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
118 | * support stacked irqchips, which indicates skipping | |
a359f757 | 119 | * all descendant irqchips. |
3b8249e7 TG |
120 | */ |
121 | enum { | |
122 | IRQ_SET_MASK_OK = 0, | |
123 | IRQ_SET_MASK_OK_NOCOPY, | |
2cb62547 | 124 | IRQ_SET_MASK_OK_DONE, |
3b8249e7 TG |
125 | }; |
126 | ||
5b912c10 | 127 | struct msi_desc; |
08a543ad | 128 | struct irq_domain; |
6a6de9ef | 129 | |
ff7dcd44 | 130 | /** |
0d0b4c86 JL |
131 | * struct irq_common_data - per irq data shared by all irqchips |
132 | * @state_use_accessors: status information for irq chip functions. | |
133 | * Use accessor functions to deal with it | |
449e9cae | 134 | * @node: node index useful for balancing |
af7080e0 | 135 | * @handler_data: per-IRQ data for the irq_chip methods |
955bfe59 QY |
136 | * @affinity: IRQ affinity on SMP. If this is an IPI |
137 | * related irq, then this is the mask of the | |
138 | * CPUs to which an IPI can be sent. | |
0d3f5425 TG |
139 | * @effective_affinity: The effective IRQ affinity on SMP as some irq |
140 | * chips do not allow multi CPU destinations. | |
141 | * A subset of @affinity. | |
b237721c | 142 | * @msi_desc: MSI descriptor |
f256c9a0 | 143 | * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. |
0d0b4c86 JL |
144 | */ |
145 | struct irq_common_data { | |
b354286e | 146 | unsigned int __private state_use_accessors; |
449e9cae JL |
147 | #ifdef CONFIG_NUMA |
148 | unsigned int node; | |
149 | #endif | |
af7080e0 | 150 | void *handler_data; |
b237721c | 151 | struct msi_desc *msi_desc; |
9df872fa | 152 | cpumask_var_t affinity; |
0d3f5425 TG |
153 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
154 | cpumask_var_t effective_affinity; | |
155 | #endif | |
f256c9a0 QY |
156 | #ifdef CONFIG_GENERIC_IRQ_IPI |
157 | unsigned int ipi_offset; | |
158 | #endif | |
0d0b4c86 JL |
159 | }; |
160 | ||
161 | /** | |
162 | * struct irq_data - per irq chip data passed down to chip functions | |
966dc736 | 163 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 164 | * @irq: interrupt number |
08a543ad | 165 | * @hwirq: hardware interrupt number, local to the interrupt domain |
0d0b4c86 | 166 | * @common: point to data shared by all irqchips |
ff7dcd44 | 167 | * @chip: low level interrupt hardware access |
08a543ad GL |
168 | * @domain: Interrupt translation domain; responsible for mapping |
169 | * between hwirq number and linux irq number. | |
f8264e34 JL |
170 | * @parent_data: pointer to parent struct irq_data to support hierarchy |
171 | * irq_domain | |
ff7dcd44 TG |
172 | * @chip_data: platform-specific per-chip private data for the chip |
173 | * methods, to allow shared chip implementations | |
ff7dcd44 TG |
174 | */ |
175 | struct irq_data { | |
966dc736 | 176 | u32 mask; |
ff7dcd44 | 177 | unsigned int irq; |
08a543ad | 178 | unsigned long hwirq; |
0d0b4c86 | 179 | struct irq_common_data *common; |
ff7dcd44 | 180 | struct irq_chip *chip; |
08a543ad | 181 | struct irq_domain *domain; |
f8264e34 JL |
182 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
183 | struct irq_data *parent_data; | |
184 | #endif | |
ff7dcd44 | 185 | void *chip_data; |
ff7dcd44 TG |
186 | }; |
187 | ||
f230b6d5 | 188 | /* |
0d0b4c86 | 189 | * Bit masks for irq_common_data.state_use_accessors |
f230b6d5 | 190 | * |
876dbd4c | 191 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 192 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
08d85f3e | 193 | * IRQD_ACTIVATED - Interrupt has already been activated |
a005677b TG |
194 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
195 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 196 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 197 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
198 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
199 | * from suspend | |
551417af | 200 | * IRQD_MOVE_PCNTXT - Interrupt can be moved in process |
e1ef8241 | 201 | * context |
32f4125e TG |
202 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
203 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
204 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 205 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
fc569712 | 206 | * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU |
9c255583 | 207 | * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel |
1bb04016 | 208 | * IRQD_IRQ_STARTED - Startup state of the interrupt |
54fdf6a0 TG |
209 | * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity |
210 | * mask. Applies only to affinity managed irqs. | |
d52dd441 | 211 | * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target |
4f8413a3 | 212 | * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set |
69790ba9 | 213 | * IRQD_CAN_RESERVE - Can use reservation mode |
6f1a4891 TG |
214 | * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change |
215 | * required | |
c16816ac TG |
216 | * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked |
217 | * from actual interrupt context. | |
f0c7baca TG |
218 | * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call |
219 | * irq_chip::irq_set_affinity() when deactivated. | |
90428a8e MS |
220 | * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if |
221 | * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. | |
f230b6d5 TG |
222 | */ |
223 | enum { | |
876dbd4c | 224 | IRQD_TRIGGER_MASK = 0xf, |
a005677b | 225 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
08d85f3e | 226 | IRQD_ACTIVATED = (1 << 9), |
a005677b TG |
227 | IRQD_NO_BALANCING = (1 << 10), |
228 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 229 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 230 | IRQD_LEVEL = (1 << 13), |
7f94226f | 231 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 232 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 233 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
234 | IRQD_IRQ_MASKED = (1 << 17), |
235 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 236 | IRQD_WAKEUP_ARMED = (1 << 19), |
fc569712 | 237 | IRQD_FORWARDED_TO_VCPU = (1 << 20), |
9c255583 | 238 | IRQD_AFFINITY_MANAGED = (1 << 21), |
201d7f47 | 239 | IRQD_IRQ_STARTED = (1 << 22), |
54fdf6a0 | 240 | IRQD_MANAGED_SHUTDOWN = (1 << 23), |
d52dd441 | 241 | IRQD_SINGLE_TARGET = (1 << 24), |
4f8413a3 | 242 | IRQD_DEFAULT_TRIGGER_SET = (1 << 25), |
69790ba9 | 243 | IRQD_CAN_RESERVE = (1 << 26), |
6f1a4891 | 244 | IRQD_MSI_NOMASK_QUIRK = (1 << 27), |
c16816ac | 245 | IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), |
f0c7baca | 246 | IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), |
90428a8e | 247 | IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30), |
f230b6d5 TG |
248 | }; |
249 | ||
b354286e | 250 | #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) |
0d0b4c86 | 251 | |
f230b6d5 TG |
252 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
253 | { | |
0d0b4c86 | 254 | return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; |
f230b6d5 TG |
255 | } |
256 | ||
a005677b TG |
257 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
258 | { | |
0d0b4c86 | 259 | return __irqd_to_state(d) & IRQD_PER_CPU; |
a005677b TG |
260 | } |
261 | ||
262 | static inline bool irqd_can_balance(struct irq_data *d) | |
263 | { | |
0d0b4c86 | 264 | return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
a005677b TG |
265 | } |
266 | ||
2bdd1055 TG |
267 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
268 | { | |
0d0b4c86 | 269 | return __irqd_to_state(d) & IRQD_AFFINITY_SET; |
2bdd1055 TG |
270 | } |
271 | ||
ee38c04b TG |
272 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
273 | { | |
0d0b4c86 | 274 | __irqd_to_state(d) |= IRQD_AFFINITY_SET; |
ee38c04b TG |
275 | } |
276 | ||
4f8413a3 MZ |
277 | static inline bool irqd_trigger_type_was_set(struct irq_data *d) |
278 | { | |
279 | return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; | |
280 | } | |
281 | ||
876dbd4c TG |
282 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
283 | { | |
0d0b4c86 | 284 | return __irqd_to_state(d) & IRQD_TRIGGER_MASK; |
876dbd4c TG |
285 | } |
286 | ||
287 | /* | |
4f8413a3 MZ |
288 | * Must only be called inside irq_chip.irq_set_type() functions or |
289 | * from the DT/ACPI setup code. | |
876dbd4c TG |
290 | */ |
291 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
292 | { | |
0d0b4c86 JL |
293 | __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; |
294 | __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; | |
4f8413a3 | 295 | __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; |
876dbd4c TG |
296 | } |
297 | ||
298 | static inline bool irqd_is_level_type(struct irq_data *d) | |
299 | { | |
0d0b4c86 | 300 | return __irqd_to_state(d) & IRQD_LEVEL; |
876dbd4c TG |
301 | } |
302 | ||
d52dd441 TG |
303 | /* |
304 | * Must only be called of irqchip.irq_set_affinity() or low level | |
a359f757 | 305 | * hierarchy domain allocation functions. |
d52dd441 TG |
306 | */ |
307 | static inline void irqd_set_single_target(struct irq_data *d) | |
308 | { | |
309 | __irqd_to_state(d) |= IRQD_SINGLE_TARGET; | |
310 | } | |
311 | ||
312 | static inline bool irqd_is_single_target(struct irq_data *d) | |
313 | { | |
314 | return __irqd_to_state(d) & IRQD_SINGLE_TARGET; | |
315 | } | |
316 | ||
c16816ac TG |
317 | static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) |
318 | { | |
319 | __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; | |
320 | } | |
321 | ||
322 | static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) | |
323 | { | |
324 | return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; | |
325 | } | |
326 | ||
90428a8e MS |
327 | static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) |
328 | { | |
329 | return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; | |
330 | } | |
331 | ||
7f94226f TG |
332 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
333 | { | |
0d0b4c86 | 334 | return __irqd_to_state(d) & IRQD_WAKEUP_STATE; |
7f94226f TG |
335 | } |
336 | ||
e1ef8241 TG |
337 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
338 | { | |
0d0b4c86 | 339 | return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; |
e1ef8241 TG |
340 | } |
341 | ||
801a0e9a TG |
342 | static inline bool irqd_irq_disabled(struct irq_data *d) |
343 | { | |
0d0b4c86 | 344 | return __irqd_to_state(d) & IRQD_IRQ_DISABLED; |
801a0e9a TG |
345 | } |
346 | ||
32f4125e TG |
347 | static inline bool irqd_irq_masked(struct irq_data *d) |
348 | { | |
0d0b4c86 | 349 | return __irqd_to_state(d) & IRQD_IRQ_MASKED; |
32f4125e TG |
350 | } |
351 | ||
352 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
353 | { | |
0d0b4c86 | 354 | return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; |
32f4125e TG |
355 | } |
356 | ||
b76f1674 TG |
357 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
358 | { | |
0d0b4c86 | 359 | return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; |
b76f1674 TG |
360 | } |
361 | ||
fc569712 TG |
362 | static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) |
363 | { | |
364 | return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; | |
365 | } | |
366 | ||
367 | static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) | |
368 | { | |
369 | __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; | |
370 | } | |
371 | ||
372 | static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) | |
373 | { | |
374 | __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; | |
375 | } | |
b76f1674 | 376 | |
9c255583 TG |
377 | static inline bool irqd_affinity_is_managed(struct irq_data *d) |
378 | { | |
379 | return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; | |
380 | } | |
381 | ||
08d85f3e MZ |
382 | static inline bool irqd_is_activated(struct irq_data *d) |
383 | { | |
384 | return __irqd_to_state(d) & IRQD_ACTIVATED; | |
385 | } | |
386 | ||
387 | static inline void irqd_set_activated(struct irq_data *d) | |
388 | { | |
389 | __irqd_to_state(d) |= IRQD_ACTIVATED; | |
390 | } | |
391 | ||
392 | static inline void irqd_clr_activated(struct irq_data *d) | |
393 | { | |
394 | __irqd_to_state(d) &= ~IRQD_ACTIVATED; | |
395 | } | |
396 | ||
201d7f47 TG |
397 | static inline bool irqd_is_started(struct irq_data *d) |
398 | { | |
399 | return __irqd_to_state(d) & IRQD_IRQ_STARTED; | |
400 | } | |
401 | ||
761ea388 | 402 | static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) |
54fdf6a0 TG |
403 | { |
404 | return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; | |
405 | } | |
406 | ||
69790ba9 TG |
407 | static inline void irqd_set_can_reserve(struct irq_data *d) |
408 | { | |
409 | __irqd_to_state(d) |= IRQD_CAN_RESERVE; | |
410 | } | |
411 | ||
412 | static inline void irqd_clr_can_reserve(struct irq_data *d) | |
413 | { | |
414 | __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; | |
415 | } | |
416 | ||
417 | static inline bool irqd_can_reserve(struct irq_data *d) | |
418 | { | |
419 | return __irqd_to_state(d) & IRQD_CAN_RESERVE; | |
420 | } | |
421 | ||
6f1a4891 TG |
422 | static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) |
423 | { | |
424 | __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; | |
425 | } | |
426 | ||
427 | static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) | |
428 | { | |
429 | __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; | |
430 | } | |
431 | ||
432 | static inline bool irqd_msi_nomask_quirk(struct irq_data *d) | |
433 | { | |
434 | return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; | |
435 | } | |
436 | ||
f0c7baca TG |
437 | static inline void irqd_set_affinity_on_activate(struct irq_data *d) |
438 | { | |
439 | __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; | |
440 | } | |
441 | ||
442 | static inline bool irqd_affinity_on_activate(struct irq_data *d) | |
443 | { | |
444 | return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; | |
445 | } | |
446 | ||
b354286e BF |
447 | #undef __irqd_to_state |
448 | ||
a699e4e4 GL |
449 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
450 | { | |
451 | return d->hwirq; | |
452 | } | |
453 | ||
8fee5c36 | 454 | /** |
6a6de9ef | 455 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 | 456 | * |
be45beb2 | 457 | * @parent_device: pointer to parent device for irqchip |
8fee5c36 | 458 | * @name: name for /proc/interrupts |
f8822657 TG |
459 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
460 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
461 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
462 | * @irq_disable: disable the interrupt | |
463 | * @irq_ack: start of a new interrupt | |
464 | * @irq_mask: mask an interrupt source | |
465 | * @irq_mask_ack: ack and mask an interrupt source | |
466 | * @irq_unmask: unmask an interrupt source | |
467 | * @irq_eoi: end of interrupt | |
83979133 TG |
468 | * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force |
469 | * argument is true, it tells the driver to | |
470 | * unconditionally apply the affinity setting. Sanity | |
471 | * checks against the supplied affinity mask are not | |
472 | * required. This is used for CPU hotplug where the | |
473 | * target CPU is not yet set in the cpu_online_mask. | |
f8822657 TG |
474 | * @irq_retrigger: resend an IRQ to the CPU |
475 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
476 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
477 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
478 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
479 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
480 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
be9b22b6 BN |
481 | * @irq_suspend: function called from core code on suspend once per |
482 | * chip, when one or more interrupts are installed | |
483 | * @irq_resume: function called from core code on resume once per chip, | |
484 | * when one ore more interrupts are installed | |
cfefd21e | 485 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
d0051816 | 486 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 487 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
488 | * @irq_request_resources: optional to request resources before calling |
489 | * any other callback related to this irq | |
490 | * @irq_release_resources: optional to release resources acquired with | |
491 | * irq_request_resources | |
515085ef | 492 | * @irq_compose_msi_msg: optional to compose message content for MSI |
9dde55b7 | 493 | * @irq_write_msi_msg: optional to write message content for MSI |
1b7047ed MZ |
494 | * @irq_get_irqchip_state: return the internal state of an interrupt |
495 | * @irq_set_irqchip_state: set the internal state of a interrupt | |
0a4377de | 496 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
34dc1ae1 QY |
497 | * @ipi_send_single: send a single IPI to destination cpus |
498 | * @ipi_send_mask: send an IPI to destination cpus in cpumask | |
b525903c JT |
499 | * @irq_nmi_setup: function called from core code before enabling an NMI |
500 | * @irq_nmi_teardown: function called from core code after disabling an NMI | |
2bff17ad | 501 | * @flags: chip specific flags |
1da177e4 | 502 | */ |
6a6de9ef | 503 | struct irq_chip { |
be45beb2 | 504 | struct device *parent_device; |
6a6de9ef | 505 | const char *name; |
f8822657 TG |
506 | unsigned int (*irq_startup)(struct irq_data *data); |
507 | void (*irq_shutdown)(struct irq_data *data); | |
508 | void (*irq_enable)(struct irq_data *data); | |
509 | void (*irq_disable)(struct irq_data *data); | |
510 | ||
511 | void (*irq_ack)(struct irq_data *data); | |
512 | void (*irq_mask)(struct irq_data *data); | |
513 | void (*irq_mask_ack)(struct irq_data *data); | |
514 | void (*irq_unmask)(struct irq_data *data); | |
515 | void (*irq_eoi)(struct irq_data *data); | |
516 | ||
517 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
518 | int (*irq_retrigger)(struct irq_data *data); | |
519 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
520 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
521 | ||
522 | void (*irq_bus_lock)(struct irq_data *data); | |
523 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
524 | ||
0fdb4b25 DD |
525 | void (*irq_cpu_online)(struct irq_data *data); |
526 | void (*irq_cpu_offline)(struct irq_data *data); | |
527 | ||
cfefd21e TG |
528 | void (*irq_suspend)(struct irq_data *data); |
529 | void (*irq_resume)(struct irq_data *data); | |
530 | void (*irq_pm_shutdown)(struct irq_data *data); | |
531 | ||
d0051816 TG |
532 | void (*irq_calc_mask)(struct irq_data *data); |
533 | ||
ab7798ff | 534 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
535 | int (*irq_request_resources)(struct irq_data *data); |
536 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 537 | |
515085ef | 538 | void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
9dde55b7 | 539 | void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
515085ef | 540 | |
1b7047ed MZ |
541 | int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); |
542 | int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); | |
543 | ||
0a4377de JL |
544 | int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); |
545 | ||
34dc1ae1 QY |
546 | void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); |
547 | void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); | |
548 | ||
b525903c JT |
549 | int (*irq_nmi_setup)(struct irq_data *data); |
550 | void (*irq_nmi_teardown)(struct irq_data *data); | |
551 | ||
2bff17ad | 552 | unsigned long flags; |
1da177e4 LT |
553 | }; |
554 | ||
d4d5e089 TG |
555 | /* |
556 | * irq_chip specific flags | |
557 | * | |
90428a8e MS |
558 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
559 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
560 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path | |
561 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks | |
562 | * when irq enabled | |
563 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip | |
564 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask | |
565 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode | |
566 | * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs | |
567 | * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips | |
568 | * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs | |
569 | * in the suspend path if they are in disabled state | |
d4d5e089 TG |
570 | */ |
571 | enum { | |
90428a8e MS |
572 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), |
573 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), | |
574 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), | |
575 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), | |
576 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), | |
577 | IRQCHIP_ONESHOT_SAFE = (1 << 5), | |
578 | IRQCHIP_EOI_THREADED = (1 << 6), | |
579 | IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), | |
580 | IRQCHIP_SUPPORTS_NMI = (1 << 8), | |
581 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), | |
d4d5e089 TG |
582 | }; |
583 | ||
e144710b | 584 | #include <linux/irqdesc.h> |
0b8f1efa | 585 | |
34ffdb72 IM |
586 | /* |
587 | * Pick up the arch-dependent methods: | |
588 | */ | |
589 | #include <asm/hw_irq.h> | |
1da177e4 | 590 | |
b683de2b TG |
591 | #ifndef NR_IRQS_LEGACY |
592 | # define NR_IRQS_LEGACY 0 | |
593 | #endif | |
594 | ||
1318a481 TG |
595 | #ifndef ARCH_IRQ_INIT_FLAGS |
596 | # define ARCH_IRQ_INIT_FLAGS 0 | |
597 | #endif | |
598 | ||
c1594b77 | 599 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 600 | |
e144710b | 601 | struct irqaction; |
31d9d9b6 MZ |
602 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
603 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 604 | |
0fdb4b25 DD |
605 | extern void irq_cpu_online(void); |
606 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
607 | extern int irq_set_affinity_locked(struct irq_data *data, |
608 | const struct cpumask *cpumask, bool force); | |
0a4377de | 609 | extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); |
0fdb4b25 | 610 | |
c5cb83bb | 611 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) |
f1e0bb0a | 612 | extern void irq_migrate_all_off_this_cpu(void); |
c5cb83bb TG |
613 | extern int irq_affinity_online_cpu(unsigned int cpu); |
614 | #else | |
615 | # define irq_affinity_online_cpu NULL | |
616 | #endif | |
f1e0bb0a | 617 | |
3a3856d0 | 618 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
d340ebd6 TG |
619 | void __irq_move_irq(struct irq_data *data); |
620 | static inline void irq_move_irq(struct irq_data *data) | |
621 | { | |
622 | if (unlikely(irqd_is_setaffinity_pending(data))) | |
623 | __irq_move_irq(data); | |
624 | } | |
a439520f | 625 | void irq_move_masked_irq(struct irq_data *data); |
f0383c24 | 626 | void irq_force_complete_move(struct irq_desc *desc); |
e144710b | 627 | #else |
a439520f TG |
628 | static inline void irq_move_irq(struct irq_data *data) { } |
629 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
f0383c24 | 630 | static inline void irq_force_complete_move(struct irq_desc *desc) { } |
e144710b | 631 | #endif |
54d5d424 | 632 | |
1da177e4 | 633 | extern int no_irq_affinity; |
1da177e4 | 634 | |
293a7a0a TG |
635 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
636 | int irq_set_parent(int irq, int parent_irq); | |
637 | #else | |
638 | static inline int irq_set_parent(int irq, int parent_irq) | |
639 | { | |
640 | return 0; | |
641 | } | |
642 | #endif | |
643 | ||
6a6de9ef TG |
644 | /* |
645 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 646 | * callable via desc->handle_irq() |
6a6de9ef | 647 | */ |
bd0b9ac4 TG |
648 | extern void handle_level_irq(struct irq_desc *desc); |
649 | extern void handle_fasteoi_irq(struct irq_desc *desc); | |
650 | extern void handle_edge_irq(struct irq_desc *desc); | |
651 | extern void handle_edge_eoi_irq(struct irq_desc *desc); | |
652 | extern void handle_simple_irq(struct irq_desc *desc); | |
edd14cfe | 653 | extern void handle_untracked_irq(struct irq_desc *desc); |
bd0b9ac4 TG |
654 | extern void handle_percpu_irq(struct irq_desc *desc); |
655 | extern void handle_percpu_devid_irq(struct irq_desc *desc); | |
656 | extern void handle_bad_irq(struct irq_desc *desc); | |
31b47cf7 | 657 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 658 | |
2dcf1fbc JT |
659 | extern void handle_fasteoi_nmi(struct irq_desc *desc); |
660 | extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); | |
661 | ||
515085ef | 662 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
be45beb2 JH |
663 | extern int irq_chip_pm_get(struct irq_data *data); |
664 | extern int irq_chip_pm_put(struct irq_data *data); | |
85f08c17 | 665 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
7703b08c DD |
666 | extern void handle_fasteoi_ack_irq(struct irq_desc *desc); |
667 | extern void handle_fasteoi_mask_irq(struct irq_desc *desc); | |
4a169a95 MS |
668 | extern int irq_chip_set_parent_state(struct irq_data *data, |
669 | enum irqchip_irq_state which, | |
670 | bool val); | |
671 | extern int irq_chip_get_parent_state(struct irq_data *data, | |
672 | enum irqchip_irq_state which, | |
673 | bool *state); | |
3cfeffc2 SA |
674 | extern void irq_chip_enable_parent(struct irq_data *data); |
675 | extern void irq_chip_disable_parent(struct irq_data *data); | |
85f08c17 JL |
676 | extern void irq_chip_ack_parent(struct irq_data *data); |
677 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); | |
56e8abab | 678 | extern void irq_chip_mask_parent(struct irq_data *data); |
5aa5bd56 | 679 | extern void irq_chip_mask_ack_parent(struct irq_data *data); |
56e8abab YC |
680 | extern void irq_chip_unmask_parent(struct irq_data *data); |
681 | extern void irq_chip_eoi_parent(struct irq_data *data); | |
682 | extern int irq_chip_set_affinity_parent(struct irq_data *data, | |
683 | const struct cpumask *dest, | |
684 | bool force); | |
08b55e2a | 685 | extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); |
0a4377de JL |
686 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
687 | void *vcpu_info); | |
b7560de1 | 688 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
2bd1298a LV |
689 | extern int irq_chip_request_resources_parent(struct irq_data *data); |
690 | extern void irq_chip_release_resources_parent(struct irq_data *data); | |
85f08c17 JL |
691 | #endif |
692 | ||
6a6de9ef | 693 | /* Handling of unhandled and spurious interrupts: */ |
0dcdbc97 | 694 | extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); |
1da177e4 | 695 | |
a4633adc | 696 | |
6a6de9ef TG |
697 | /* Enable/disable irq debugging output: */ |
698 | extern int noirqdebug_setup(char *str); | |
699 | ||
700 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
701 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
702 | ||
f8b5473f | 703 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 704 | extern struct irq_chip no_irq_chip; |
f8b5473f | 705 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 706 | |
145fc655 | 707 | extern void |
3836ca08 | 708 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
709 | irq_flow_handler_t handle, const char *name); |
710 | ||
3836ca08 TG |
711 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
712 | irq_flow_handler_t handle) | |
713 | { | |
714 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
715 | } | |
716 | ||
31d9d9b6 | 717 | extern int irq_set_percpu_devid(unsigned int irq); |
222df54f MZ |
718 | extern int irq_set_percpu_devid_partition(unsigned int irq, |
719 | const struct cpumask *affinity); | |
720 | extern int irq_get_percpu_devid_partition(unsigned int irq, | |
721 | struct cpumask *affinity); | |
31d9d9b6 | 722 | |
6a6de9ef | 723 | extern void |
3836ca08 | 724 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 725 | const char *name); |
1da177e4 | 726 | |
6a6de9ef | 727 | static inline void |
3836ca08 | 728 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 729 | { |
3836ca08 | 730 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
731 | } |
732 | ||
733 | /* | |
734 | * Set a highlevel chained flow handler for a given IRQ. | |
735 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 736 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
737 | */ |
738 | static inline void | |
3836ca08 | 739 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 740 | { |
3836ca08 | 741 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
742 | } |
743 | ||
3b0f95be RK |
744 | /* |
745 | * Set a highlevel chained flow handler and its data for a given IRQ. | |
746 | * (a chained handler is automatically enabled and set to | |
747 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) | |
748 | */ | |
749 | void | |
750 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
751 | void *data); | |
752 | ||
44247184 TG |
753 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
754 | ||
755 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
756 | { | |
757 | irq_modify_status(irq, 0, set); | |
758 | } | |
759 | ||
760 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
761 | { | |
762 | irq_modify_status(irq, clr, 0); | |
763 | } | |
764 | ||
a0cd9ca2 | 765 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
766 | { |
767 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
768 | } | |
769 | ||
a0cd9ca2 | 770 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
771 | { |
772 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
773 | } | |
46f4f8f6 | 774 | |
7f1b1244 PM |
775 | static inline void irq_set_nothread(unsigned int irq) |
776 | { | |
777 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
778 | } | |
779 | ||
780 | static inline void irq_set_thread(unsigned int irq) | |
781 | { | |
782 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
783 | } | |
784 | ||
6f91a52d TG |
785 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
786 | { | |
787 | if (nest) | |
788 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
789 | else | |
790 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
791 | } | |
792 | ||
31d9d9b6 MZ |
793 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
794 | { | |
795 | irq_set_status_flags(irq, | |
796 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
797 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
798 | } | |
799 | ||
3a16d713 | 800 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
801 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
802 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
803 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
804 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
805 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
806 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
807 | struct msi_desc *entry); | |
f303a6dd | 808 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 809 | |
a0cd9ca2 | 810 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
811 | { |
812 | struct irq_data *d = irq_get_irq_data(irq); | |
813 | return d ? d->chip : NULL; | |
814 | } | |
815 | ||
816 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
817 | { | |
818 | return d->chip; | |
819 | } | |
820 | ||
a0cd9ca2 | 821 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
822 | { |
823 | struct irq_data *d = irq_get_irq_data(irq); | |
824 | return d ? d->chip_data : NULL; | |
825 | } | |
826 | ||
827 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
828 | { | |
829 | return d->chip_data; | |
830 | } | |
831 | ||
a0cd9ca2 | 832 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
833 | { |
834 | struct irq_data *d = irq_get_irq_data(irq); | |
af7080e0 | 835 | return d ? d->common->handler_data : NULL; |
f303a6dd TG |
836 | } |
837 | ||
a0cd9ca2 | 838 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd | 839 | { |
af7080e0 | 840 | return d->common->handler_data; |
f303a6dd TG |
841 | } |
842 | ||
a0cd9ca2 | 843 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
844 | { |
845 | struct irq_data *d = irq_get_irq_data(irq); | |
b237721c | 846 | return d ? d->common->msi_desc : NULL; |
f303a6dd TG |
847 | } |
848 | ||
c391f262 | 849 | static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) |
f303a6dd | 850 | { |
b237721c | 851 | return d->common->msi_desc; |
f303a6dd TG |
852 | } |
853 | ||
1f6236bf JMC |
854 | static inline u32 irq_get_trigger_type(unsigned int irq) |
855 | { | |
856 | struct irq_data *d = irq_get_irq_data(irq); | |
857 | return d ? irqd_get_trigger_type(d) : 0; | |
858 | } | |
859 | ||
449e9cae | 860 | static inline int irq_common_data_get_node(struct irq_common_data *d) |
6783011b | 861 | { |
449e9cae | 862 | #ifdef CONFIG_NUMA |
6783011b | 863 | return d->node; |
449e9cae JL |
864 | #else |
865 | return 0; | |
866 | #endif | |
867 | } | |
868 | ||
869 | static inline int irq_data_get_node(struct irq_data *d) | |
870 | { | |
871 | return irq_common_data_get_node(d->common); | |
6783011b JL |
872 | } |
873 | ||
c64301a2 JL |
874 | static inline struct cpumask *irq_get_affinity_mask(int irq) |
875 | { | |
876 | struct irq_data *d = irq_get_irq_data(irq); | |
877 | ||
9df872fa | 878 | return d ? d->common->affinity : NULL; |
c64301a2 JL |
879 | } |
880 | ||
881 | static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) | |
882 | { | |
9df872fa | 883 | return d->common->affinity; |
c64301a2 JL |
884 | } |
885 | ||
0d3f5425 TG |
886 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
887 | static inline | |
888 | struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) | |
889 | { | |
0551968a | 890 | return d->common->effective_affinity; |
0d3f5425 TG |
891 | } |
892 | static inline void irq_data_update_effective_affinity(struct irq_data *d, | |
893 | const struct cpumask *m) | |
894 | { | |
895 | cpumask_copy(d->common->effective_affinity, m); | |
896 | } | |
897 | #else | |
898 | static inline void irq_data_update_effective_affinity(struct irq_data *d, | |
899 | const struct cpumask *m) | |
900 | { | |
901 | } | |
902 | static inline | |
903 | struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) | |
904 | { | |
905 | return d->common->affinity; | |
906 | } | |
907 | #endif | |
908 | ||
3e238012 TG |
909 | static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq) |
910 | { | |
911 | struct irq_data *d = irq_get_irq_data(irq); | |
912 | ||
913 | return d ? irq_data_get_effective_affinity_mask(d) : NULL; | |
914 | } | |
915 | ||
62a08ae2 TG |
916 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
917 | ||
b6873807 | 918 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
bec04037 DL |
919 | struct module *owner, |
920 | const struct irq_affinity_desc *affinity); | |
b6873807 | 921 | |
2b5e7730 BG |
922 | int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, |
923 | unsigned int cnt, int node, struct module *owner, | |
bec04037 | 924 | const struct irq_affinity_desc *affinity); |
2b5e7730 | 925 | |
ec53cf23 PG |
926 | /* use macros to avoid needing export.h for THIS_MODULE */ |
927 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
06ee6d57 | 928 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) |
b6873807 | 929 | |
ec53cf23 | 930 | #define irq_alloc_desc(node) \ |
4c7bcb51 | 931 | irq_alloc_descs(-1, 1, 1, node) |
1f5a5b87 | 932 | |
ec53cf23 PG |
933 | #define irq_alloc_desc_at(at, node) \ |
934 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 935 | |
ec53cf23 PG |
936 | #define irq_alloc_desc_from(from, node) \ |
937 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 938 | |
51906e77 AG |
939 | #define irq_alloc_descs_from(from, cnt, node) \ |
940 | irq_alloc_descs(-1, from, cnt, node) | |
941 | ||
2b5e7730 BG |
942 | #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ |
943 | __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) | |
944 | ||
945 | #define devm_irq_alloc_desc(dev, node) \ | |
4c7bcb51 | 946 | devm_irq_alloc_descs(dev, -1, 1, 1, node) |
2b5e7730 BG |
947 | |
948 | #define devm_irq_alloc_desc_at(dev, at, node) \ | |
949 | devm_irq_alloc_descs(dev, at, at, 1, node) | |
950 | ||
951 | #define devm_irq_alloc_desc_from(dev, from, node) \ | |
952 | devm_irq_alloc_descs(dev, -1, from, 1, node) | |
953 | ||
954 | #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ | |
955 | devm_irq_alloc_descs(dev, -1, from, cnt, node) | |
956 | ||
ec53cf23 | 957 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
958 | static inline void irq_free_desc(unsigned int irq) |
959 | { | |
960 | irq_free_descs(irq, 1); | |
961 | } | |
962 | ||
c940e01c TG |
963 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
964 | void irq_init_desc(unsigned int irq); | |
965 | #endif | |
966 | ||
7d828062 TG |
967 | /** |
968 | * struct irq_chip_regs - register offsets for struct irq_gci | |
969 | * @enable: Enable register offset to reg_base | |
970 | * @disable: Disable register offset to reg_base | |
971 | * @mask: Mask register offset to reg_base | |
972 | * @ack: Ack register offset to reg_base | |
973 | * @eoi: Eoi register offset to reg_base | |
974 | * @type: Type configuration register offset to reg_base | |
975 | * @polarity: Polarity configuration register offset to reg_base | |
976 | */ | |
977 | struct irq_chip_regs { | |
978 | unsigned long enable; | |
979 | unsigned long disable; | |
980 | unsigned long mask; | |
981 | unsigned long ack; | |
982 | unsigned long eoi; | |
983 | unsigned long type; | |
984 | unsigned long polarity; | |
985 | }; | |
986 | ||
987 | /** | |
988 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
989 | * @chip: The real interrupt chip which provides the callbacks | |
990 | * @regs: Register offsets for this chip | |
991 | * @handler: Flow handler associated with this chip | |
992 | * @type: Chip can handle these flow types | |
899f0e66 GF |
993 | * @mask_cache_priv: Cached mask register private to the chip type |
994 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
995 | * |
996 | * A irq_generic_chip can have several instances of irq_chip_type when | |
997 | * it requires different functions and register offsets for different | |
998 | * flow types. | |
999 | */ | |
1000 | struct irq_chip_type { | |
1001 | struct irq_chip chip; | |
1002 | struct irq_chip_regs regs; | |
1003 | irq_flow_handler_t handler; | |
1004 | u32 type; | |
899f0e66 GF |
1005 | u32 mask_cache_priv; |
1006 | u32 *mask_cache; | |
7d828062 TG |
1007 | }; |
1008 | ||
1009 | /** | |
1010 | * struct irq_chip_generic - Generic irq chip data structure | |
1011 | * @lock: Lock to protect register and cache data access | |
1012 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
1013 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
1014 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
be9b22b6 BN |
1015 | * @suspend: Function called from core code on suspend once per |
1016 | * chip; can be useful instead of irq_chip::suspend to | |
1017 | * handle chip details even when no interrupts are in use | |
1018 | * @resume: Function called from core code on resume once per chip; | |
1019 | * can be useful instead of irq_chip::suspend to handle | |
1020 | * chip details even when no interrupts are in use | |
7d828062 TG |
1021 | * @irq_base: Interrupt base nr for this chip |
1022 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 1023 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
1024 | * @type_cache: Cached type register |
1025 | * @polarity_cache: Cached polarity register | |
1026 | * @wake_enabled: Interrupt can wakeup from suspend | |
1027 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
1028 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
1029 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 1030 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 1031 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 1032 | * @domain: irq domain pointer |
cfefd21e | 1033 | * @list: List head for keeping track of instances |
7d828062 TG |
1034 | * @chip_types: Array of interrupt irq_chip_types |
1035 | * | |
1036 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
1037 | * implementations which can be associated to a particular irq line of | |
1038 | * an irq_chip_generic instance. That allows to share and protect | |
1039 | * state in an irq_chip_generic instance when we need to implement | |
1040 | * different flow mechanisms (level/edge) for it. | |
1041 | */ | |
1042 | struct irq_chip_generic { | |
1043 | raw_spinlock_t lock; | |
1044 | void __iomem *reg_base; | |
2b280376 KC |
1045 | u32 (*reg_readl)(void __iomem *addr); |
1046 | void (*reg_writel)(u32 val, void __iomem *addr); | |
be9b22b6 BN |
1047 | void (*suspend)(struct irq_chip_generic *gc); |
1048 | void (*resume)(struct irq_chip_generic *gc); | |
7d828062 TG |
1049 | unsigned int irq_base; |
1050 | unsigned int irq_cnt; | |
1051 | u32 mask_cache; | |
1052 | u32 type_cache; | |
1053 | u32 polarity_cache; | |
1054 | u32 wake_enabled; | |
1055 | u32 wake_active; | |
1056 | unsigned int num_ct; | |
1057 | void *private; | |
088f40b7 | 1058 | unsigned long installed; |
e8bd834f | 1059 | unsigned long unused; |
088f40b7 | 1060 | struct irq_domain *domain; |
cfefd21e | 1061 | struct list_head list; |
7856e9f1 | 1062 | struct irq_chip_type chip_types[]; |
7d828062 TG |
1063 | }; |
1064 | ||
1065 | /** | |
1066 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
1067 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
1068 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
1069 | * irq chips which need to call irq_set_wake() on | |
1070 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 1071 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 1072 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
b7905595 | 1073 | * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) |
7d828062 TG |
1074 | */ |
1075 | enum irq_gc_flags { | |
1076 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
1077 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 1078 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 1079 | IRQ_GC_NO_MASK = 1 << 3, |
b7905595 | 1080 | IRQ_GC_BE_IO = 1 << 4, |
7d828062 TG |
1081 | }; |
1082 | ||
088f40b7 TG |
1083 | /* |
1084 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
1085 | * @irqs_per_chip: Number of interrupts per chip | |
1086 | * @num_chips: Number of chips | |
1087 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
1088 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
1089 | * @gc_flags: Generic chip specific setup flags | |
1090 | * @gc: Array of pointers to generic interrupt chips | |
1091 | */ | |
1092 | struct irq_domain_chip_generic { | |
1093 | unsigned int irqs_per_chip; | |
1094 | unsigned int num_chips; | |
1095 | unsigned int irq_flags_to_clear; | |
1096 | unsigned int irq_flags_to_set; | |
1097 | enum irq_gc_flags gc_flags; | |
7856e9f1 | 1098 | struct irq_chip_generic *gc[]; |
088f40b7 TG |
1099 | }; |
1100 | ||
7d828062 TG |
1101 | /* Generic chip callback functions */ |
1102 | void irq_gc_noop(struct irq_data *d); | |
1103 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
1104 | void irq_gc_mask_set_bit(struct irq_data *d); | |
1105 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
1106 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
1107 | void irq_gc_ack_set_bit(struct irq_data *d); |
1108 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
20608924 | 1109 | void irq_gc_mask_disable_and_ack_set(struct irq_data *d); |
7d828062 TG |
1110 | void irq_gc_eoi(struct irq_data *d); |
1111 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
1112 | ||
1113 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
1114 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
1115 | irq_hw_number_t hw_irq); | |
7d828062 TG |
1116 | struct irq_chip_generic * |
1117 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
1118 | void __iomem *reg_base, irq_flow_handler_t handler); | |
1119 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
1120 | enum irq_gc_flags flags, unsigned int clr, | |
1121 | unsigned int set); | |
1122 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
1123 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
1124 | unsigned int clr, unsigned int set); | |
7d828062 | 1125 | |
1c3e3630 BG |
1126 | struct irq_chip_generic * |
1127 | devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, | |
1128 | unsigned int irq_base, void __iomem *reg_base, | |
1129 | irq_flow_handler_t handler); | |
30fd8fc5 BG |
1130 | int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, |
1131 | u32 msk, enum irq_gc_flags flags, | |
1132 | unsigned int clr, unsigned int set); | |
1c3e3630 | 1133 | |
088f40b7 | 1134 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
088f40b7 | 1135 | |
f88eecfe SF |
1136 | int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, |
1137 | int num_ct, const char *name, | |
1138 | irq_flow_handler_t handler, | |
1139 | unsigned int clr, unsigned int set, | |
1140 | enum irq_gc_flags flags); | |
1141 | ||
1142 | #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ | |
1143 | handler, clr, set, flags) \ | |
1144 | ({ \ | |
1145 | MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ | |
1146 | __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ | |
1147 | handler, clr, set, flags); \ | |
1148 | }) | |
088f40b7 | 1149 | |
707188f5 BG |
1150 | static inline void irq_free_generic_chip(struct irq_chip_generic *gc) |
1151 | { | |
1152 | kfree(gc); | |
1153 | } | |
1154 | ||
32bb6cbb BG |
1155 | static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, |
1156 | u32 msk, unsigned int clr, | |
1157 | unsigned int set) | |
1158 | { | |
1159 | irq_remove_generic_chip(gc, msk, clr, set); | |
1160 | irq_free_generic_chip(gc); | |
1161 | } | |
1162 | ||
7d828062 TG |
1163 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
1164 | { | |
1165 | return container_of(d->chip, struct irq_chip_type, chip); | |
1166 | } | |
1167 | ||
1168 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
1169 | ||
1170 | #ifdef CONFIG_SMP | |
1171 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
1172 | { | |
1173 | raw_spin_lock(&gc->lock); | |
1174 | } | |
1175 | ||
1176 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
1177 | { | |
1178 | raw_spin_unlock(&gc->lock); | |
1179 | } | |
1180 | #else | |
1181 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
1182 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
1183 | #endif | |
1184 | ||
ebf9ff75 BB |
1185 | /* |
1186 | * The irqsave variants are for usage in non interrupt code. Do not use | |
1187 | * them in irq_chip callbacks. Use irq_gc_lock() instead. | |
1188 | */ | |
1189 | #define irq_gc_lock_irqsave(gc, flags) \ | |
1190 | raw_spin_lock_irqsave(&(gc)->lock, flags) | |
1191 | ||
1192 | #define irq_gc_unlock_irqrestore(gc, flags) \ | |
1193 | raw_spin_unlock_irqrestore(&(gc)->lock, flags) | |
1194 | ||
332fd7c4 KC |
1195 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
1196 | u32 val, int reg_offset) | |
1197 | { | |
2b280376 KC |
1198 | if (gc->reg_writel) |
1199 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
1200 | else | |
1201 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
1202 | } |
1203 | ||
1204 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
1205 | int reg_offset) | |
1206 | { | |
2b280376 KC |
1207 | if (gc->reg_readl) |
1208 | return gc->reg_readl(gc->reg_base + reg_offset); | |
1209 | else | |
1210 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
1211 | } |
1212 | ||
2f75d9e1 TG |
1213 | struct irq_matrix; |
1214 | struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, | |
1215 | unsigned int alloc_start, | |
1216 | unsigned int alloc_end); | |
1217 | void irq_matrix_online(struct irq_matrix *m); | |
1218 | void irq_matrix_offline(struct irq_matrix *m); | |
1219 | void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); | |
1220 | int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); | |
1221 | void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); | |
76f99ae5 DL |
1222 | int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, |
1223 | unsigned int *mapped_cpu); | |
2f75d9e1 TG |
1224 | void irq_matrix_reserve(struct irq_matrix *m); |
1225 | void irq_matrix_remove_reserved(struct irq_matrix *m); | |
1226 | int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, | |
1227 | bool reserved, unsigned int *mapped_cpu); | |
1228 | void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, | |
1229 | unsigned int bit, bool managed); | |
1230 | void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); | |
1231 | unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); | |
1232 | unsigned int irq_matrix_allocated(struct irq_matrix *m); | |
1233 | unsigned int irq_matrix_reserved(struct irq_matrix *m); | |
1234 | void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); | |
1235 | ||
d17bf24e QY |
1236 | /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ |
1237 | #define INVALID_HWIRQ (~0UL) | |
f9bce791 | 1238 | irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); |
3b8e29a8 QY |
1239 | int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); |
1240 | int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); | |
1241 | int ipi_send_single(unsigned int virq, unsigned int cpu); | |
1242 | int ipi_send_mask(unsigned int virq, const struct cpumask *dest); | |
d17bf24e | 1243 | |
caacdbf4 PD |
1244 | #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER |
1245 | /* | |
1246 | * Registers a generic IRQ handling function as the top-level IRQ handler in | |
1247 | * the system, which is generally the first C code called from an assembly | |
1248 | * architecture-specific interrupt handler. | |
1249 | * | |
1250 | * Returns 0 on success, or -EBUSY if an IRQ handler has already been | |
1251 | * registered. | |
1252 | */ | |
1253 | int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); | |
1254 | ||
1255 | /* | |
1256 | * Allows interrupt handlers to find the irqchip that's been registered as the | |
1257 | * top-level IRQ handler. | |
1258 | */ | |
1259 | extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; | |
ea0c80d1 | 1260 | #else |
b0b8b689 | 1261 | #ifndef set_handle_irq |
ea0c80d1 ZL |
1262 | #define set_handle_irq(handle_irq) \ |
1263 | do { \ | |
1264 | (void)handle_irq; \ | |
1265 | WARN_ON(1); \ | |
1266 | } while (0) | |
caacdbf4 | 1267 | #endif |
b0b8b689 | 1268 | #endif |
caacdbf4 | 1269 | |
06fcb0c6 | 1270 | #endif /* _LINUX_IRQ_H */ |