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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
908dcecd | 20 | #include <linux/irqreturn.h> |
1da177e4 LT |
21 | |
22 | #include <asm/irq.h> | |
23 | #include <asm/ptrace.h> | |
24 | ||
25 | /* | |
26 | * IRQ line status. | |
6e213616 TG |
27 | * |
28 | * Bits 0-16 are reserved for the IRQF_* bits in linux/interrupt.h | |
29 | * | |
30 | * IRQ types | |
1da177e4 | 31 | */ |
6e213616 TG |
32 | #define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ |
33 | #define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ | |
34 | #define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ | |
35 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) | |
36 | #define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ | |
37 | #define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ | |
38 | #define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ | |
39 | #define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ | |
40 | ||
41 | /* Internal flags */ | |
42 | #define IRQ_INPROGRESS 0x00010000 /* IRQ handler active - do not enter! */ | |
43 | #define IRQ_DISABLED 0x00020000 /* IRQ disabled - do not enter! */ | |
44 | #define IRQ_PENDING 0x00040000 /* IRQ pending - replay on enable */ | |
45 | #define IRQ_REPLAY 0x00080000 /* IRQ has been replayed but not acked yet */ | |
46 | #define IRQ_AUTODETECT 0x00100000 /* IRQ is being autodetected */ | |
47 | #define IRQ_WAITING 0x00200000 /* IRQ not yet seen - for autodetection */ | |
48 | #define IRQ_LEVEL 0x00400000 /* IRQ level triggered */ | |
49 | #define IRQ_MASKED 0x00800000 /* IRQ masked - shouldn't be seen again */ | |
b8bdb460 | 50 | #define IRQ_PER_CPU 0x01000000 /* IRQ is per CPU */ |
0d7012a9 | 51 | #ifdef CONFIG_IRQ_PER_CPU |
f26fdd59 KW |
52 | # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) |
53 | #else | |
54 | # define CHECK_IRQ_PER_CPU(var) 0 | |
55 | #endif | |
1da177e4 | 56 | |
6e213616 TG |
57 | #define IRQ_NOPROBE 0x02000000 /* IRQ is not valid for probing */ |
58 | #define IRQ_NOREQUEST 0x04000000 /* IRQ cannot be requested */ | |
59 | #define IRQ_NOAUTOEN 0x08000000 /* IRQ will not be enabled on request irq */ | |
60 | #define IRQ_DELAYED_DISABLE 0x10000000 /* IRQ disable (masking) happens delayed. */ | |
15a647eb | 61 | #define IRQ_WAKEUP 0x20000000 /* IRQ triggers system wakeup */ |
6a6de9ef TG |
62 | |
63 | struct proc_dir_entry; | |
64 | ||
8fee5c36 | 65 | /** |
6a6de9ef | 66 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
67 | * |
68 | * @name: name for /proc/interrupts | |
69 | * @startup: start up the interrupt (defaults to ->enable if NULL) | |
70 | * @shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
71 | * @enable: enable the interrupt (defaults to chip->unmask if NULL) | |
72 | * @disable: disable the interrupt (defaults to chip->mask if NULL) | |
8fee5c36 IM |
73 | * @ack: start of a new interrupt |
74 | * @mask: mask an interrupt source | |
75 | * @mask_ack: ack and mask an interrupt source | |
76 | * @unmask: unmask an interrupt source | |
47c2a3aa IM |
77 | * @eoi: end of interrupt - chip level |
78 | * @end: end of interrupt - flow level | |
8fee5c36 IM |
79 | * @set_affinity: set the CPU affinity on SMP machines |
80 | * @retrigger: resend an IRQ to the CPU | |
81 | * @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
82 | * @set_wake: enable/disable power-management wake-on of an IRQ | |
83 | * | |
84 | * @release: release function solely used by UML | |
6a6de9ef | 85 | * @typename: obsoleted by name, kept as migration helper |
1da177e4 | 86 | */ |
6a6de9ef TG |
87 | struct irq_chip { |
88 | const char *name; | |
71d218b7 IM |
89 | unsigned int (*startup)(unsigned int irq); |
90 | void (*shutdown)(unsigned int irq); | |
91 | void (*enable)(unsigned int irq); | |
92 | void (*disable)(unsigned int irq); | |
6a6de9ef | 93 | |
71d218b7 | 94 | void (*ack)(unsigned int irq); |
6a6de9ef TG |
95 | void (*mask)(unsigned int irq); |
96 | void (*mask_ack)(unsigned int irq); | |
97 | void (*unmask)(unsigned int irq); | |
47c2a3aa | 98 | void (*eoi)(unsigned int irq); |
6a6de9ef | 99 | |
71d218b7 IM |
100 | void (*end)(unsigned int irq); |
101 | void (*set_affinity)(unsigned int irq, cpumask_t dest); | |
c0ad90a3 | 102 | int (*retrigger)(unsigned int irq); |
6a6de9ef TG |
103 | int (*set_type)(unsigned int irq, unsigned int flow_type); |
104 | int (*set_wake)(unsigned int irq, unsigned int on); | |
c0ad90a3 | 105 | |
b77d6adc PBG |
106 | /* Currently used only by UML, might disappear one day.*/ |
107 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 108 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 109 | #endif |
6a6de9ef TG |
110 | /* |
111 | * For compatibility, ->typename is copied into ->name. | |
112 | * Will disappear. | |
113 | */ | |
114 | const char *typename; | |
1da177e4 LT |
115 | }; |
116 | ||
8fee5c36 IM |
117 | /** |
118 | * struct irq_desc - interrupt descriptor | |
119 | * | |
6a6de9ef TG |
120 | * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()] |
121 | * @chip: low level interrupt hardware access | |
122 | * @handler_data: per-IRQ data for the irq_chip methods | |
123 | * @chip_data: platform-specific per-chip private data for the chip | |
124 | * methods, to allow shared chip implementations | |
8fee5c36 IM |
125 | * @action: the irq action chain |
126 | * @status: status information | |
127 | * @depth: disable-depth, for nested irq_disable() calls | |
15a647eb | 128 | * @wake_depth: enable depth, for multiple set_irq_wake() callers |
8fee5c36 IM |
129 | * @irq_count: stats field to detect stalled irqs |
130 | * @irqs_unhandled: stats field for spurious unhandled interrupts | |
131 | * @lock: locking for SMP | |
132 | * @affinity: IRQ affinity on SMP | |
6a6de9ef | 133 | * @cpu: cpu index useful for balancing |
8fee5c36 IM |
134 | * @pending_mask: pending rebalanced interrupts |
135 | * @move_irq: need to re-target IRQ destination | |
136 | * @dir: /proc/irq/ procfs entry | |
137 | * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP | |
1da177e4 LT |
138 | * |
139 | * Pad this out to 32 bytes for cache and indexing reasons. | |
140 | */ | |
34ffdb72 | 141 | struct irq_desc { |
6a6de9ef TG |
142 | void fastcall (*handle_irq)(unsigned int irq, |
143 | struct irq_desc *desc, | |
144 | struct pt_regs *regs); | |
145 | struct irq_chip *chip; | |
146 | void *handler_data; | |
71d218b7 IM |
147 | void *chip_data; |
148 | struct irqaction *action; /* IRQ action list */ | |
149 | unsigned int status; /* IRQ status */ | |
6a6de9ef | 150 | |
71d218b7 | 151 | unsigned int depth; /* nested irq disables */ |
15a647eb | 152 | unsigned int wake_depth; /* nested wake enables */ |
71d218b7 IM |
153 | unsigned int irq_count; /* For detecting broken IRQs */ |
154 | unsigned int irqs_unhandled; | |
155 | spinlock_t lock; | |
a53da52f | 156 | #ifdef CONFIG_SMP |
71d218b7 | 157 | cpumask_t affinity; |
6a6de9ef | 158 | unsigned int cpu; |
a53da52f | 159 | #endif |
06fcb0c6 | 160 | #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) |
cd916d31 | 161 | cpumask_t pending_mask; |
71d218b7 | 162 | unsigned int move_irq; /* need to re-target IRQ dest */ |
54d5d424 | 163 | #endif |
4a733ee1 IM |
164 | #ifdef CONFIG_PROC_FS |
165 | struct proc_dir_entry *dir; | |
166 | #endif | |
34ffdb72 | 167 | } ____cacheline_aligned; |
1da177e4 | 168 | |
34ffdb72 | 169 | extern struct irq_desc irq_desc[NR_IRQS]; |
1da177e4 | 170 | |
34ffdb72 IM |
171 | /* |
172 | * Migration helpers for obsolete names, they will go away: | |
173 | */ | |
6a6de9ef TG |
174 | #define hw_interrupt_type irq_chip |
175 | typedef struct irq_chip hw_irq_controller; | |
176 | #define no_irq_type no_irq_chip | |
34ffdb72 IM |
177 | typedef struct irq_desc irq_desc_t; |
178 | ||
179 | /* | |
180 | * Pick up the arch-dependent methods: | |
181 | */ | |
182 | #include <asm/hw_irq.h> | |
1da177e4 | 183 | |
06fcb0c6 | 184 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
1da177e4 LT |
185 | |
186 | #ifdef CONFIG_GENERIC_HARDIRQS | |
06fcb0c6 | 187 | |
d061daa0 TG |
188 | #ifndef handle_dynamic_tick |
189 | # define handle_dynamic_tick(a) do { } while (0) | |
190 | #endif | |
191 | ||
54d5d424 AR |
192 | #ifdef CONFIG_SMP |
193 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
194 | { | |
a53da52f | 195 | irq_desc[irq].affinity = mask; |
54d5d424 AR |
196 | } |
197 | #else | |
198 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
199 | { | |
200 | } | |
201 | #endif | |
202 | ||
203 | #ifdef CONFIG_SMP | |
204 | ||
06fcb0c6 | 205 | #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) |
54d5d424 | 206 | |
c777ac55 AM |
207 | void set_pending_irq(unsigned int irq, cpumask_t mask); |
208 | void move_native_irq(int irq); | |
54d5d424 AR |
209 | |
210 | #ifdef CONFIG_PCI_MSI | |
211 | /* | |
212 | * Wonder why these are dummies? | |
213 | * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq() | |
214 | * counter part after translating the vector to irq info. We need to perform | |
215 | * this operation on the real irq, when we dont use vector, i.e when | |
216 | * pci_use_vector() is false. | |
217 | */ | |
218 | static inline void move_irq(int irq) | |
219 | { | |
220 | } | |
221 | ||
222 | static inline void set_irq_info(int irq, cpumask_t mask) | |
223 | { | |
224 | } | |
225 | ||
06fcb0c6 | 226 | #else /* CONFIG_PCI_MSI */ |
54d5d424 AR |
227 | |
228 | static inline void move_irq(int irq) | |
229 | { | |
230 | move_native_irq(irq); | |
231 | } | |
232 | ||
233 | static inline void set_irq_info(int irq, cpumask_t mask) | |
234 | { | |
235 | set_native_irq_info(irq, mask); | |
236 | } | |
54d5d424 | 237 | |
06fcb0c6 IM |
238 | #endif /* CONFIG_PCI_MSI */ |
239 | ||
240 | #else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */ | |
241 | ||
242 | static inline void move_irq(int irq) | |
243 | { | |
244 | } | |
245 | ||
246 | static inline void move_native_irq(int irq) | |
247 | { | |
248 | } | |
249 | ||
250 | static inline void set_pending_irq(unsigned int irq, cpumask_t mask) | |
251 | { | |
252 | } | |
54d5d424 | 253 | |
54d5d424 AR |
254 | static inline void set_irq_info(int irq, cpumask_t mask) |
255 | { | |
256 | set_native_irq_info(irq, mask); | |
257 | } | |
258 | ||
06fcb0c6 | 259 | #endif /* CONFIG_GENERIC_PENDING_IRQ */ |
54d5d424 | 260 | |
06fcb0c6 | 261 | #else /* CONFIG_SMP */ |
54d5d424 AR |
262 | |
263 | #define move_irq(x) | |
264 | #define move_native_irq(x) | |
265 | ||
06fcb0c6 | 266 | #endif /* CONFIG_SMP */ |
54d5d424 | 267 | |
1b61b910 ZY |
268 | #ifdef CONFIG_IRQBALANCE |
269 | extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask); | |
270 | #else | |
271 | static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) | |
272 | { | |
273 | } | |
274 | #endif | |
275 | ||
71d218b7 IM |
276 | #ifdef CONFIG_AUTO_IRQ_AFFINITY |
277 | extern int select_smp_affinity(unsigned int irq); | |
278 | #else | |
279 | static inline int select_smp_affinity(unsigned int irq) | |
280 | { | |
281 | return 1; | |
282 | } | |
283 | #endif | |
284 | ||
1da177e4 | 285 | extern int no_irq_affinity; |
1da177e4 | 286 | |
6a6de9ef TG |
287 | /* Handle irq action chains: */ |
288 | extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs, | |
289 | struct irqaction *action); | |
290 | ||
291 | /* | |
292 | * Built-in IRQ handlers for various IRQ types, | |
293 | * callable via desc->chip->handle_irq() | |
294 | */ | |
295 | extern void fastcall | |
296 | handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs); | |
297 | extern void fastcall | |
47c2a3aa | 298 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc, |
6a6de9ef TG |
299 | struct pt_regs *regs); |
300 | extern void fastcall | |
301 | handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs); | |
302 | extern void fastcall | |
303 | handle_simple_irq(unsigned int irq, struct irq_desc *desc, | |
304 | struct pt_regs *regs); | |
305 | extern void fastcall | |
306 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc, | |
307 | struct pt_regs *regs); | |
308 | extern void fastcall | |
309 | handle_bad_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs); | |
310 | ||
311 | /* | |
312 | * Get a descriptive string for the highlevel handler, for | |
313 | * /proc/interrupts output: | |
314 | */ | |
315 | extern const char * | |
316 | handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *, | |
317 | struct pt_regs *)); | |
318 | ||
2e60bbb6 | 319 | /* |
6a6de9ef TG |
320 | * Monolithic do_IRQ implementation. |
321 | * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly) | |
2e60bbb6 | 322 | */ |
af8c65b5 | 323 | #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
1da177e4 | 324 | extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs); |
af8c65b5 | 325 | #endif |
2e60bbb6 | 326 | |
dae86204 IM |
327 | /* |
328 | * Architectures call this to let the generic IRQ layer | |
329 | * handle an interrupt. If the descriptor is attached to an | |
330 | * irqchip-style controller then we call the ->handle_irq() handler, | |
331 | * and it calls __do_IRQ() if it's attached to an irqtype-style controller. | |
332 | */ | |
333 | static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs) | |
334 | { | |
335 | struct irq_desc *desc = irq_desc + irq; | |
336 | ||
af8c65b5 DH |
337 | #ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
338 | desc->handle_irq(irq, desc, regs); | |
339 | #else | |
dae86204 IM |
340 | if (likely(desc->handle_irq)) |
341 | desc->handle_irq(irq, desc, regs); | |
342 | else | |
343 | __do_IRQ(irq, regs); | |
af8c65b5 | 344 | #endif |
dae86204 IM |
345 | } |
346 | ||
6a6de9ef | 347 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 348 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
2e60bbb6 | 349 | int action_ret, struct pt_regs *regs); |
1da177e4 | 350 | |
a4633adc TG |
351 | /* Resending of interrupts :*/ |
352 | void check_irq_resend(struct irq_desc *desc, unsigned int irq); | |
353 | ||
6a6de9ef | 354 | /* Initialize /proc/irq/ */ |
1da177e4 | 355 | extern void init_irq_proc(void); |
eee45269 | 356 | |
6a6de9ef TG |
357 | /* Enable/disable irq debugging output: */ |
358 | extern int noirqdebug_setup(char *str); | |
359 | ||
360 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
361 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
362 | ||
f8b5473f | 363 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 364 | extern struct irq_chip no_irq_chip; |
f8b5473f | 365 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef TG |
366 | |
367 | extern void | |
368 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
369 | void fastcall (*handle)(unsigned int, | |
370 | struct irq_desc *, | |
371 | struct pt_regs *)); | |
372 | extern void | |
373 | __set_irq_handler(unsigned int irq, | |
374 | void fastcall (*handle)(unsigned int, struct irq_desc *, | |
375 | struct pt_regs *), | |
376 | int is_chained); | |
1da177e4 | 377 | |
6a6de9ef TG |
378 | /* |
379 | * Set a highlevel flow handler for a given IRQ: | |
380 | */ | |
381 | static inline void | |
382 | set_irq_handler(unsigned int irq, | |
383 | void fastcall (*handle)(unsigned int, struct irq_desc *, | |
384 | struct pt_regs *)) | |
385 | { | |
386 | __set_irq_handler(irq, handle, 0); | |
387 | } | |
388 | ||
389 | /* | |
390 | * Set a highlevel chained flow handler for a given IRQ. | |
391 | * (a chained handler is automatically enabled and set to | |
392 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
393 | */ | |
394 | static inline void | |
395 | set_irq_chained_handler(unsigned int irq, | |
396 | void fastcall (*handle)(unsigned int, struct irq_desc *, | |
397 | struct pt_regs *)) | |
398 | { | |
399 | __set_irq_handler(irq, handle, 1); | |
400 | } | |
401 | ||
dd87eb3a TG |
402 | /* Set/get chip/data for an IRQ: */ |
403 | ||
404 | extern int set_irq_chip(unsigned int irq, struct irq_chip *chip); | |
405 | extern int set_irq_data(unsigned int irq, void *data); | |
406 | extern int set_irq_chip_data(unsigned int irq, void *data); | |
407 | extern int set_irq_type(unsigned int irq, unsigned int type); | |
408 | ||
409 | #define get_irq_chip(irq) (irq_desc[irq].chip) | |
410 | #define get_irq_chip_data(irq) (irq_desc[irq].chip_data) | |
411 | #define get_irq_data(irq) (irq_desc[irq].handler_data) | |
412 | ||
6a6de9ef | 413 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 414 | |
06fcb0c6 | 415 | #endif /* !CONFIG_S390 */ |
1da177e4 | 416 | |
06fcb0c6 | 417 | #endif /* _LINUX_IRQ_H */ |