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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
06fcb0c6 IM |
2 | #ifndef _LINUX_IRQ_H |
3 | #define _LINUX_IRQ_H | |
1da177e4 LT |
4 | |
5 | /* | |
6 | * Please do not include this file in generic code. There is currently | |
7 | * no requirement for any architecture to implement anything held | |
8 | * within this file. | |
9 | * | |
10 | * Thanks. --rmk | |
11 | */ | |
12 | ||
1da177e4 LT |
13 | #include <linux/cache.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/cpumask.h> | |
75ffc007 | 16 | #include <linux/irqhandler.h> |
908dcecd | 17 | #include <linux/irqreturn.h> |
dd3a1db9 | 18 | #include <linux/irqnr.h> |
503e5763 | 19 | #include <linux/topology.h> |
332fd7c4 | 20 | #include <linux/io.h> |
707188f5 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include <asm/irq.h> | |
24 | #include <asm/ptrace.h> | |
7d12e780 | 25 | #include <asm/irq_regs.h> |
1da177e4 | 26 | |
ab7798ff | 27 | struct seq_file; |
ec53cf23 | 28 | struct module; |
515085ef | 29 | struct msi_msg; |
1b7047ed | 30 | enum irqchip_irq_state; |
57a58a94 | 31 | |
1da177e4 LT |
32 | /* |
33 | * IRQ line status. | |
6e213616 | 34 | * |
5d4d8fc9 TG |
35 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
36 | * | |
37 | * IRQ_TYPE_NONE - default, unspecified type | |
38 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
39 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
40 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
41 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
42 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
43 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
44 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
45 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
46 | * to setup the HW to a sane default (used | |
47 | * by irqdomain map() callbacks to synchronize | |
48 | * the HW state and SW flags for a newly | |
49 | * allocated descriptor). | |
50 | * | |
5d4d8fc9 TG |
51 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
52 | * | |
53 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
54 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
55 | * updated in the code when the above trigger | |
0911f124 | 56 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
57 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
58 | * it from affinity setting | |
59 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
60 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
61 | * request_irq() | |
7f1b1244 | 62 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
63 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
64 | * request/setup_irq() | |
65 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
66 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
92068d17 | 67 | * IRQ_NESTED_THREAD - Interrupt nests into another thread |
31d9d9b6 | 68 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
69 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
70 | * it from the spurious interrupt detection | |
71 | * mechanism and from core side polling. | |
e9849777 | 72 | * IRQ_DISABLE_UNLAZY - Disable lazy irq disable |
1da177e4 | 73 | */ |
5d4d8fc9 TG |
74 | enum { |
75 | IRQ_TYPE_NONE = 0x00000000, | |
76 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
77 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
78 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
79 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
80 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
81 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
82 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 83 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
84 | |
85 | IRQ_TYPE_PROBE = 0x00000010, | |
86 | ||
87 | IRQ_LEVEL = (1 << 8), | |
88 | IRQ_PER_CPU = (1 << 9), | |
89 | IRQ_NOPROBE = (1 << 10), | |
90 | IRQ_NOREQUEST = (1 << 11), | |
91 | IRQ_NOAUTOEN = (1 << 12), | |
92 | IRQ_NO_BALANCING = (1 << 13), | |
93 | IRQ_MOVE_PCNTXT = (1 << 14), | |
94 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 95 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 96 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 97 | IRQ_IS_POLLED = (1 << 18), |
e9849777 | 98 | IRQ_DISABLE_UNLAZY = (1 << 19), |
5d4d8fc9 | 99 | }; |
950f4427 | 100 | |
44247184 TG |
101 | #define IRQF_MODIFY_MASK \ |
102 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 103 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd | 104 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
e9849777 | 105 | IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) |
44247184 | 106 | |
8f53f924 TG |
107 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
108 | ||
3b8249e7 TG |
109 | /* |
110 | * Return value for chip->irq_set_affinity() | |
111 | * | |
9df872fa JL |
112 | * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity |
113 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity | |
2cb62547 JL |
114 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
115 | * support stacked irqchips, which indicates skipping | |
116 | * all descendent irqchips. | |
3b8249e7 TG |
117 | */ |
118 | enum { | |
119 | IRQ_SET_MASK_OK = 0, | |
120 | IRQ_SET_MASK_OK_NOCOPY, | |
2cb62547 | 121 | IRQ_SET_MASK_OK_DONE, |
3b8249e7 TG |
122 | }; |
123 | ||
5b912c10 | 124 | struct msi_desc; |
08a543ad | 125 | struct irq_domain; |
6a6de9ef | 126 | |
ff7dcd44 | 127 | /** |
0d0b4c86 JL |
128 | * struct irq_common_data - per irq data shared by all irqchips |
129 | * @state_use_accessors: status information for irq chip functions. | |
130 | * Use accessor functions to deal with it | |
449e9cae | 131 | * @node: node index useful for balancing |
af7080e0 | 132 | * @handler_data: per-IRQ data for the irq_chip methods |
955bfe59 QY |
133 | * @affinity: IRQ affinity on SMP. If this is an IPI |
134 | * related irq, then this is the mask of the | |
135 | * CPUs to which an IPI can be sent. | |
0d3f5425 TG |
136 | * @effective_affinity: The effective IRQ affinity on SMP as some irq |
137 | * chips do not allow multi CPU destinations. | |
138 | * A subset of @affinity. | |
b237721c | 139 | * @msi_desc: MSI descriptor |
f256c9a0 | 140 | * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. |
0d0b4c86 JL |
141 | */ |
142 | struct irq_common_data { | |
b354286e | 143 | unsigned int __private state_use_accessors; |
449e9cae JL |
144 | #ifdef CONFIG_NUMA |
145 | unsigned int node; | |
146 | #endif | |
af7080e0 | 147 | void *handler_data; |
b237721c | 148 | struct msi_desc *msi_desc; |
9df872fa | 149 | cpumask_var_t affinity; |
0d3f5425 TG |
150 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
151 | cpumask_var_t effective_affinity; | |
152 | #endif | |
f256c9a0 QY |
153 | #ifdef CONFIG_GENERIC_IRQ_IPI |
154 | unsigned int ipi_offset; | |
155 | #endif | |
0d0b4c86 JL |
156 | }; |
157 | ||
158 | /** | |
159 | * struct irq_data - per irq chip data passed down to chip functions | |
966dc736 | 160 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 161 | * @irq: interrupt number |
08a543ad | 162 | * @hwirq: hardware interrupt number, local to the interrupt domain |
0d0b4c86 | 163 | * @common: point to data shared by all irqchips |
ff7dcd44 | 164 | * @chip: low level interrupt hardware access |
08a543ad GL |
165 | * @domain: Interrupt translation domain; responsible for mapping |
166 | * between hwirq number and linux irq number. | |
f8264e34 JL |
167 | * @parent_data: pointer to parent struct irq_data to support hierarchy |
168 | * irq_domain | |
ff7dcd44 TG |
169 | * @chip_data: platform-specific per-chip private data for the chip |
170 | * methods, to allow shared chip implementations | |
ff7dcd44 TG |
171 | */ |
172 | struct irq_data { | |
966dc736 | 173 | u32 mask; |
ff7dcd44 | 174 | unsigned int irq; |
08a543ad | 175 | unsigned long hwirq; |
0d0b4c86 | 176 | struct irq_common_data *common; |
ff7dcd44 | 177 | struct irq_chip *chip; |
08a543ad | 178 | struct irq_domain *domain; |
f8264e34 JL |
179 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
180 | struct irq_data *parent_data; | |
181 | #endif | |
ff7dcd44 | 182 | void *chip_data; |
ff7dcd44 TG |
183 | }; |
184 | ||
f230b6d5 | 185 | /* |
0d0b4c86 | 186 | * Bit masks for irq_common_data.state_use_accessors |
f230b6d5 | 187 | * |
876dbd4c | 188 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 189 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
08d85f3e | 190 | * IRQD_ACTIVATED - Interrupt has already been activated |
a005677b TG |
191 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
192 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 193 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 194 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
195 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
196 | * from suspend | |
e1ef8241 TG |
197 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
198 | * context | |
32f4125e TG |
199 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
200 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
201 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 202 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
fc569712 | 203 | * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU |
9c255583 | 204 | * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel |
1bb04016 | 205 | * IRQD_IRQ_STARTED - Startup state of the interrupt |
54fdf6a0 TG |
206 | * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity |
207 | * mask. Applies only to affinity managed irqs. | |
d52dd441 | 208 | * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target |
4f8413a3 | 209 | * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set |
69790ba9 | 210 | * IRQD_CAN_RESERVE - Can use reservation mode |
f230b6d5 TG |
211 | */ |
212 | enum { | |
876dbd4c | 213 | IRQD_TRIGGER_MASK = 0xf, |
a005677b | 214 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
08d85f3e | 215 | IRQD_ACTIVATED = (1 << 9), |
a005677b TG |
216 | IRQD_NO_BALANCING = (1 << 10), |
217 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 218 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 219 | IRQD_LEVEL = (1 << 13), |
7f94226f | 220 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 221 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 222 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
223 | IRQD_IRQ_MASKED = (1 << 17), |
224 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 225 | IRQD_WAKEUP_ARMED = (1 << 19), |
fc569712 | 226 | IRQD_FORWARDED_TO_VCPU = (1 << 20), |
9c255583 | 227 | IRQD_AFFINITY_MANAGED = (1 << 21), |
201d7f47 | 228 | IRQD_IRQ_STARTED = (1 << 22), |
54fdf6a0 | 229 | IRQD_MANAGED_SHUTDOWN = (1 << 23), |
d52dd441 | 230 | IRQD_SINGLE_TARGET = (1 << 24), |
4f8413a3 | 231 | IRQD_DEFAULT_TRIGGER_SET = (1 << 25), |
69790ba9 | 232 | IRQD_CAN_RESERVE = (1 << 26), |
f230b6d5 TG |
233 | }; |
234 | ||
b354286e | 235 | #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) |
0d0b4c86 | 236 | |
f230b6d5 TG |
237 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
238 | { | |
0d0b4c86 | 239 | return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; |
f230b6d5 TG |
240 | } |
241 | ||
a005677b TG |
242 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
243 | { | |
0d0b4c86 | 244 | return __irqd_to_state(d) & IRQD_PER_CPU; |
a005677b TG |
245 | } |
246 | ||
247 | static inline bool irqd_can_balance(struct irq_data *d) | |
248 | { | |
0d0b4c86 | 249 | return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
a005677b TG |
250 | } |
251 | ||
2bdd1055 TG |
252 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
253 | { | |
0d0b4c86 | 254 | return __irqd_to_state(d) & IRQD_AFFINITY_SET; |
2bdd1055 TG |
255 | } |
256 | ||
ee38c04b TG |
257 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
258 | { | |
0d0b4c86 | 259 | __irqd_to_state(d) |= IRQD_AFFINITY_SET; |
ee38c04b TG |
260 | } |
261 | ||
4f8413a3 MZ |
262 | static inline bool irqd_trigger_type_was_set(struct irq_data *d) |
263 | { | |
264 | return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; | |
265 | } | |
266 | ||
876dbd4c TG |
267 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
268 | { | |
0d0b4c86 | 269 | return __irqd_to_state(d) & IRQD_TRIGGER_MASK; |
876dbd4c TG |
270 | } |
271 | ||
272 | /* | |
4f8413a3 MZ |
273 | * Must only be called inside irq_chip.irq_set_type() functions or |
274 | * from the DT/ACPI setup code. | |
876dbd4c TG |
275 | */ |
276 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
277 | { | |
0d0b4c86 JL |
278 | __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; |
279 | __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; | |
4f8413a3 | 280 | __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; |
876dbd4c TG |
281 | } |
282 | ||
283 | static inline bool irqd_is_level_type(struct irq_data *d) | |
284 | { | |
0d0b4c86 | 285 | return __irqd_to_state(d) & IRQD_LEVEL; |
876dbd4c TG |
286 | } |
287 | ||
d52dd441 TG |
288 | /* |
289 | * Must only be called of irqchip.irq_set_affinity() or low level | |
290 | * hieararchy domain allocation functions. | |
291 | */ | |
292 | static inline void irqd_set_single_target(struct irq_data *d) | |
293 | { | |
294 | __irqd_to_state(d) |= IRQD_SINGLE_TARGET; | |
295 | } | |
296 | ||
297 | static inline bool irqd_is_single_target(struct irq_data *d) | |
298 | { | |
299 | return __irqd_to_state(d) & IRQD_SINGLE_TARGET; | |
300 | } | |
301 | ||
7f94226f TG |
302 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
303 | { | |
0d0b4c86 | 304 | return __irqd_to_state(d) & IRQD_WAKEUP_STATE; |
7f94226f TG |
305 | } |
306 | ||
e1ef8241 TG |
307 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
308 | { | |
0d0b4c86 | 309 | return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; |
e1ef8241 TG |
310 | } |
311 | ||
801a0e9a TG |
312 | static inline bool irqd_irq_disabled(struct irq_data *d) |
313 | { | |
0d0b4c86 | 314 | return __irqd_to_state(d) & IRQD_IRQ_DISABLED; |
801a0e9a TG |
315 | } |
316 | ||
32f4125e TG |
317 | static inline bool irqd_irq_masked(struct irq_data *d) |
318 | { | |
0d0b4c86 | 319 | return __irqd_to_state(d) & IRQD_IRQ_MASKED; |
32f4125e TG |
320 | } |
321 | ||
322 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
323 | { | |
0d0b4c86 | 324 | return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; |
32f4125e TG |
325 | } |
326 | ||
b76f1674 TG |
327 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
328 | { | |
0d0b4c86 | 329 | return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; |
b76f1674 TG |
330 | } |
331 | ||
fc569712 TG |
332 | static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) |
333 | { | |
334 | return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; | |
335 | } | |
336 | ||
337 | static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) | |
338 | { | |
339 | __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; | |
340 | } | |
341 | ||
342 | static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) | |
343 | { | |
344 | __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; | |
345 | } | |
b76f1674 | 346 | |
9c255583 TG |
347 | static inline bool irqd_affinity_is_managed(struct irq_data *d) |
348 | { | |
349 | return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; | |
350 | } | |
351 | ||
08d85f3e MZ |
352 | static inline bool irqd_is_activated(struct irq_data *d) |
353 | { | |
354 | return __irqd_to_state(d) & IRQD_ACTIVATED; | |
355 | } | |
356 | ||
357 | static inline void irqd_set_activated(struct irq_data *d) | |
358 | { | |
359 | __irqd_to_state(d) |= IRQD_ACTIVATED; | |
360 | } | |
361 | ||
362 | static inline void irqd_clr_activated(struct irq_data *d) | |
363 | { | |
364 | __irqd_to_state(d) &= ~IRQD_ACTIVATED; | |
365 | } | |
366 | ||
201d7f47 TG |
367 | static inline bool irqd_is_started(struct irq_data *d) |
368 | { | |
369 | return __irqd_to_state(d) & IRQD_IRQ_STARTED; | |
370 | } | |
371 | ||
761ea388 | 372 | static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) |
54fdf6a0 TG |
373 | { |
374 | return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; | |
375 | } | |
376 | ||
69790ba9 TG |
377 | static inline void irqd_set_can_reserve(struct irq_data *d) |
378 | { | |
379 | __irqd_to_state(d) |= IRQD_CAN_RESERVE; | |
380 | } | |
381 | ||
382 | static inline void irqd_clr_can_reserve(struct irq_data *d) | |
383 | { | |
384 | __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; | |
385 | } | |
386 | ||
387 | static inline bool irqd_can_reserve(struct irq_data *d) | |
388 | { | |
389 | return __irqd_to_state(d) & IRQD_CAN_RESERVE; | |
390 | } | |
391 | ||
b354286e BF |
392 | #undef __irqd_to_state |
393 | ||
a699e4e4 GL |
394 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
395 | { | |
396 | return d->hwirq; | |
397 | } | |
398 | ||
8fee5c36 | 399 | /** |
6a6de9ef | 400 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 | 401 | * |
be45beb2 | 402 | * @parent_device: pointer to parent device for irqchip |
8fee5c36 | 403 | * @name: name for /proc/interrupts |
f8822657 TG |
404 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
405 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
406 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
407 | * @irq_disable: disable the interrupt | |
408 | * @irq_ack: start of a new interrupt | |
409 | * @irq_mask: mask an interrupt source | |
410 | * @irq_mask_ack: ack and mask an interrupt source | |
411 | * @irq_unmask: unmask an interrupt source | |
412 | * @irq_eoi: end of interrupt | |
83979133 TG |
413 | * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force |
414 | * argument is true, it tells the driver to | |
415 | * unconditionally apply the affinity setting. Sanity | |
416 | * checks against the supplied affinity mask are not | |
417 | * required. This is used for CPU hotplug where the | |
418 | * target CPU is not yet set in the cpu_online_mask. | |
f8822657 TG |
419 | * @irq_retrigger: resend an IRQ to the CPU |
420 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
421 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
422 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
423 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
424 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
425 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
be9b22b6 BN |
426 | * @irq_suspend: function called from core code on suspend once per |
427 | * chip, when one or more interrupts are installed | |
428 | * @irq_resume: function called from core code on resume once per chip, | |
429 | * when one ore more interrupts are installed | |
cfefd21e | 430 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
d0051816 | 431 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 432 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
433 | * @irq_request_resources: optional to request resources before calling |
434 | * any other callback related to this irq | |
435 | * @irq_release_resources: optional to release resources acquired with | |
436 | * irq_request_resources | |
515085ef | 437 | * @irq_compose_msi_msg: optional to compose message content for MSI |
9dde55b7 | 438 | * @irq_write_msi_msg: optional to write message content for MSI |
1b7047ed MZ |
439 | * @irq_get_irqchip_state: return the internal state of an interrupt |
440 | * @irq_set_irqchip_state: set the internal state of a interrupt | |
0a4377de | 441 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
34dc1ae1 QY |
442 | * @ipi_send_single: send a single IPI to destination cpus |
443 | * @ipi_send_mask: send an IPI to destination cpus in cpumask | |
2bff17ad | 444 | * @flags: chip specific flags |
1da177e4 | 445 | */ |
6a6de9ef | 446 | struct irq_chip { |
be45beb2 | 447 | struct device *parent_device; |
6a6de9ef | 448 | const char *name; |
f8822657 TG |
449 | unsigned int (*irq_startup)(struct irq_data *data); |
450 | void (*irq_shutdown)(struct irq_data *data); | |
451 | void (*irq_enable)(struct irq_data *data); | |
452 | void (*irq_disable)(struct irq_data *data); | |
453 | ||
454 | void (*irq_ack)(struct irq_data *data); | |
455 | void (*irq_mask)(struct irq_data *data); | |
456 | void (*irq_mask_ack)(struct irq_data *data); | |
457 | void (*irq_unmask)(struct irq_data *data); | |
458 | void (*irq_eoi)(struct irq_data *data); | |
459 | ||
460 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
461 | int (*irq_retrigger)(struct irq_data *data); | |
462 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
463 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
464 | ||
465 | void (*irq_bus_lock)(struct irq_data *data); | |
466 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
467 | ||
0fdb4b25 DD |
468 | void (*irq_cpu_online)(struct irq_data *data); |
469 | void (*irq_cpu_offline)(struct irq_data *data); | |
470 | ||
cfefd21e TG |
471 | void (*irq_suspend)(struct irq_data *data); |
472 | void (*irq_resume)(struct irq_data *data); | |
473 | void (*irq_pm_shutdown)(struct irq_data *data); | |
474 | ||
d0051816 TG |
475 | void (*irq_calc_mask)(struct irq_data *data); |
476 | ||
ab7798ff | 477 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
478 | int (*irq_request_resources)(struct irq_data *data); |
479 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 480 | |
515085ef | 481 | void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
9dde55b7 | 482 | void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
515085ef | 483 | |
1b7047ed MZ |
484 | int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); |
485 | int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); | |
486 | ||
0a4377de JL |
487 | int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); |
488 | ||
34dc1ae1 QY |
489 | void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); |
490 | void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); | |
491 | ||
2bff17ad | 492 | unsigned long flags; |
1da177e4 LT |
493 | }; |
494 | ||
d4d5e089 TG |
495 | /* |
496 | * irq_chip specific flags | |
497 | * | |
77694b40 TG |
498 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
499 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 500 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
501 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
502 | * when irq enabled | |
60f96b41 | 503 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 504 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 505 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
506 | */ |
507 | enum { | |
508 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 509 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 510 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 511 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 512 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 513 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 514 | IRQCHIP_EOI_THREADED = (1 << 6), |
6988e0e0 | 515 | IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), |
d4d5e089 TG |
516 | }; |
517 | ||
e144710b | 518 | #include <linux/irqdesc.h> |
0b8f1efa | 519 | |
34ffdb72 IM |
520 | /* |
521 | * Pick up the arch-dependent methods: | |
522 | */ | |
523 | #include <asm/hw_irq.h> | |
1da177e4 | 524 | |
b683de2b TG |
525 | #ifndef NR_IRQS_LEGACY |
526 | # define NR_IRQS_LEGACY 0 | |
527 | #endif | |
528 | ||
1318a481 TG |
529 | #ifndef ARCH_IRQ_INIT_FLAGS |
530 | # define ARCH_IRQ_INIT_FLAGS 0 | |
531 | #endif | |
532 | ||
c1594b77 | 533 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 534 | |
e144710b | 535 | struct irqaction; |
06fcb0c6 | 536 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 537 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
538 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
539 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 540 | |
0fdb4b25 DD |
541 | extern void irq_cpu_online(void); |
542 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
543 | extern int irq_set_affinity_locked(struct irq_data *data, |
544 | const struct cpumask *cpumask, bool force); | |
0a4377de | 545 | extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); |
0fdb4b25 | 546 | |
c5cb83bb | 547 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) |
f1e0bb0a | 548 | extern void irq_migrate_all_off_this_cpu(void); |
c5cb83bb TG |
549 | extern int irq_affinity_online_cpu(unsigned int cpu); |
550 | #else | |
551 | # define irq_affinity_online_cpu NULL | |
552 | #endif | |
f1e0bb0a | 553 | |
3a3856d0 | 554 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
d340ebd6 TG |
555 | void __irq_move_irq(struct irq_data *data); |
556 | static inline void irq_move_irq(struct irq_data *data) | |
557 | { | |
558 | if (unlikely(irqd_is_setaffinity_pending(data))) | |
559 | __irq_move_irq(data); | |
560 | } | |
a439520f | 561 | void irq_move_masked_irq(struct irq_data *data); |
f0383c24 | 562 | void irq_force_complete_move(struct irq_desc *desc); |
e144710b | 563 | #else |
a439520f TG |
564 | static inline void irq_move_irq(struct irq_data *data) { } |
565 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
f0383c24 | 566 | static inline void irq_force_complete_move(struct irq_desc *desc) { } |
e144710b | 567 | #endif |
54d5d424 | 568 | |
1da177e4 | 569 | extern int no_irq_affinity; |
1da177e4 | 570 | |
293a7a0a TG |
571 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
572 | int irq_set_parent(int irq, int parent_irq); | |
573 | #else | |
574 | static inline int irq_set_parent(int irq, int parent_irq) | |
575 | { | |
576 | return 0; | |
577 | } | |
578 | #endif | |
579 | ||
6a6de9ef TG |
580 | /* |
581 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 582 | * callable via desc->handle_irq() |
6a6de9ef | 583 | */ |
bd0b9ac4 TG |
584 | extern void handle_level_irq(struct irq_desc *desc); |
585 | extern void handle_fasteoi_irq(struct irq_desc *desc); | |
586 | extern void handle_edge_irq(struct irq_desc *desc); | |
587 | extern void handle_edge_eoi_irq(struct irq_desc *desc); | |
588 | extern void handle_simple_irq(struct irq_desc *desc); | |
edd14cfe | 589 | extern void handle_untracked_irq(struct irq_desc *desc); |
bd0b9ac4 TG |
590 | extern void handle_percpu_irq(struct irq_desc *desc); |
591 | extern void handle_percpu_devid_irq(struct irq_desc *desc); | |
592 | extern void handle_bad_irq(struct irq_desc *desc); | |
31b47cf7 | 593 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 594 | |
515085ef | 595 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
be45beb2 JH |
596 | extern int irq_chip_pm_get(struct irq_data *data); |
597 | extern int irq_chip_pm_put(struct irq_data *data); | |
85f08c17 | 598 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
7703b08c DD |
599 | extern void handle_fasteoi_ack_irq(struct irq_desc *desc); |
600 | extern void handle_fasteoi_mask_irq(struct irq_desc *desc); | |
3cfeffc2 SA |
601 | extern void irq_chip_enable_parent(struct irq_data *data); |
602 | extern void irq_chip_disable_parent(struct irq_data *data); | |
85f08c17 JL |
603 | extern void irq_chip_ack_parent(struct irq_data *data); |
604 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); | |
56e8abab YC |
605 | extern void irq_chip_mask_parent(struct irq_data *data); |
606 | extern void irq_chip_unmask_parent(struct irq_data *data); | |
607 | extern void irq_chip_eoi_parent(struct irq_data *data); | |
608 | extern int irq_chip_set_affinity_parent(struct irq_data *data, | |
609 | const struct cpumask *dest, | |
610 | bool force); | |
08b55e2a | 611 | extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); |
0a4377de JL |
612 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
613 | void *vcpu_info); | |
b7560de1 | 614 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
85f08c17 JL |
615 | #endif |
616 | ||
6a6de9ef | 617 | /* Handling of unhandled and spurious interrupts: */ |
0dcdbc97 | 618 | extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); |
1da177e4 | 619 | |
a4633adc | 620 | |
6a6de9ef TG |
621 | /* Enable/disable irq debugging output: */ |
622 | extern int noirqdebug_setup(char *str); | |
623 | ||
624 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
625 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
626 | ||
f8b5473f | 627 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 628 | extern struct irq_chip no_irq_chip; |
f8b5473f | 629 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 630 | |
145fc655 | 631 | extern void |
3836ca08 | 632 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
633 | irq_flow_handler_t handle, const char *name); |
634 | ||
3836ca08 TG |
635 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
636 | irq_flow_handler_t handle) | |
637 | { | |
638 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
639 | } | |
640 | ||
31d9d9b6 | 641 | extern int irq_set_percpu_devid(unsigned int irq); |
222df54f MZ |
642 | extern int irq_set_percpu_devid_partition(unsigned int irq, |
643 | const struct cpumask *affinity); | |
644 | extern int irq_get_percpu_devid_partition(unsigned int irq, | |
645 | struct cpumask *affinity); | |
31d9d9b6 | 646 | |
6a6de9ef | 647 | extern void |
3836ca08 | 648 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 649 | const char *name); |
1da177e4 | 650 | |
6a6de9ef | 651 | static inline void |
3836ca08 | 652 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 653 | { |
3836ca08 | 654 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
655 | } |
656 | ||
657 | /* | |
658 | * Set a highlevel chained flow handler for a given IRQ. | |
659 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 660 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
661 | */ |
662 | static inline void | |
3836ca08 | 663 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 664 | { |
3836ca08 | 665 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
666 | } |
667 | ||
3b0f95be RK |
668 | /* |
669 | * Set a highlevel chained flow handler and its data for a given IRQ. | |
670 | * (a chained handler is automatically enabled and set to | |
671 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) | |
672 | */ | |
673 | void | |
674 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
675 | void *data); | |
676 | ||
44247184 TG |
677 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
678 | ||
679 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
680 | { | |
681 | irq_modify_status(irq, 0, set); | |
682 | } | |
683 | ||
684 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
685 | { | |
686 | irq_modify_status(irq, clr, 0); | |
687 | } | |
688 | ||
a0cd9ca2 | 689 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
690 | { |
691 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
692 | } | |
693 | ||
a0cd9ca2 | 694 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
695 | { |
696 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
697 | } | |
46f4f8f6 | 698 | |
7f1b1244 PM |
699 | static inline void irq_set_nothread(unsigned int irq) |
700 | { | |
701 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
702 | } | |
703 | ||
704 | static inline void irq_set_thread(unsigned int irq) | |
705 | { | |
706 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
707 | } | |
708 | ||
6f91a52d TG |
709 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
710 | { | |
711 | if (nest) | |
712 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
713 | else | |
714 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
715 | } | |
716 | ||
31d9d9b6 MZ |
717 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
718 | { | |
719 | irq_set_status_flags(irq, | |
720 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
721 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
722 | } | |
723 | ||
3a16d713 | 724 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
725 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
726 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
727 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
728 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
729 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
730 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
731 | struct msi_desc *entry); | |
f303a6dd | 732 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 733 | |
a0cd9ca2 | 734 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
735 | { |
736 | struct irq_data *d = irq_get_irq_data(irq); | |
737 | return d ? d->chip : NULL; | |
738 | } | |
739 | ||
740 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
741 | { | |
742 | return d->chip; | |
743 | } | |
744 | ||
a0cd9ca2 | 745 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
746 | { |
747 | struct irq_data *d = irq_get_irq_data(irq); | |
748 | return d ? d->chip_data : NULL; | |
749 | } | |
750 | ||
751 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
752 | { | |
753 | return d->chip_data; | |
754 | } | |
755 | ||
a0cd9ca2 | 756 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
757 | { |
758 | struct irq_data *d = irq_get_irq_data(irq); | |
af7080e0 | 759 | return d ? d->common->handler_data : NULL; |
f303a6dd TG |
760 | } |
761 | ||
a0cd9ca2 | 762 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd | 763 | { |
af7080e0 | 764 | return d->common->handler_data; |
f303a6dd TG |
765 | } |
766 | ||
a0cd9ca2 | 767 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
768 | { |
769 | struct irq_data *d = irq_get_irq_data(irq); | |
b237721c | 770 | return d ? d->common->msi_desc : NULL; |
f303a6dd TG |
771 | } |
772 | ||
c391f262 | 773 | static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) |
f303a6dd | 774 | { |
b237721c | 775 | return d->common->msi_desc; |
f303a6dd TG |
776 | } |
777 | ||
1f6236bf JMC |
778 | static inline u32 irq_get_trigger_type(unsigned int irq) |
779 | { | |
780 | struct irq_data *d = irq_get_irq_data(irq); | |
781 | return d ? irqd_get_trigger_type(d) : 0; | |
782 | } | |
783 | ||
449e9cae | 784 | static inline int irq_common_data_get_node(struct irq_common_data *d) |
6783011b | 785 | { |
449e9cae | 786 | #ifdef CONFIG_NUMA |
6783011b | 787 | return d->node; |
449e9cae JL |
788 | #else |
789 | return 0; | |
790 | #endif | |
791 | } | |
792 | ||
793 | static inline int irq_data_get_node(struct irq_data *d) | |
794 | { | |
795 | return irq_common_data_get_node(d->common); | |
6783011b JL |
796 | } |
797 | ||
c64301a2 JL |
798 | static inline struct cpumask *irq_get_affinity_mask(int irq) |
799 | { | |
800 | struct irq_data *d = irq_get_irq_data(irq); | |
801 | ||
9df872fa | 802 | return d ? d->common->affinity : NULL; |
c64301a2 JL |
803 | } |
804 | ||
805 | static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) | |
806 | { | |
9df872fa | 807 | return d->common->affinity; |
c64301a2 JL |
808 | } |
809 | ||
0d3f5425 TG |
810 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
811 | static inline | |
812 | struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) | |
813 | { | |
0551968a | 814 | return d->common->effective_affinity; |
0d3f5425 TG |
815 | } |
816 | static inline void irq_data_update_effective_affinity(struct irq_data *d, | |
817 | const struct cpumask *m) | |
818 | { | |
819 | cpumask_copy(d->common->effective_affinity, m); | |
820 | } | |
821 | #else | |
822 | static inline void irq_data_update_effective_affinity(struct irq_data *d, | |
823 | const struct cpumask *m) | |
824 | { | |
825 | } | |
826 | static inline | |
827 | struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) | |
828 | { | |
829 | return d->common->affinity; | |
830 | } | |
831 | #endif | |
832 | ||
62a08ae2 TG |
833 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
834 | ||
b6873807 | 835 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
06ee6d57 | 836 | struct module *owner, const struct cpumask *affinity); |
b6873807 | 837 | |
2b5e7730 BG |
838 | int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, |
839 | unsigned int cnt, int node, struct module *owner, | |
840 | const struct cpumask *affinity); | |
841 | ||
ec53cf23 PG |
842 | /* use macros to avoid needing export.h for THIS_MODULE */ |
843 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
06ee6d57 | 844 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) |
b6873807 | 845 | |
ec53cf23 PG |
846 | #define irq_alloc_desc(node) \ |
847 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 848 | |
ec53cf23 PG |
849 | #define irq_alloc_desc_at(at, node) \ |
850 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 851 | |
ec53cf23 PG |
852 | #define irq_alloc_desc_from(from, node) \ |
853 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 854 | |
51906e77 AG |
855 | #define irq_alloc_descs_from(from, cnt, node) \ |
856 | irq_alloc_descs(-1, from, cnt, node) | |
857 | ||
2b5e7730 BG |
858 | #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ |
859 | __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) | |
860 | ||
861 | #define devm_irq_alloc_desc(dev, node) \ | |
862 | devm_irq_alloc_descs(dev, -1, 0, 1, node) | |
863 | ||
864 | #define devm_irq_alloc_desc_at(dev, at, node) \ | |
865 | devm_irq_alloc_descs(dev, at, at, 1, node) | |
866 | ||
867 | #define devm_irq_alloc_desc_from(dev, from, node) \ | |
868 | devm_irq_alloc_descs(dev, -1, from, 1, node) | |
869 | ||
870 | #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ | |
871 | devm_irq_alloc_descs(dev, -1, from, cnt, node) | |
872 | ||
ec53cf23 | 873 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
874 | static inline void irq_free_desc(unsigned int irq) |
875 | { | |
876 | irq_free_descs(irq, 1); | |
877 | } | |
878 | ||
7b6ef126 TG |
879 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
880 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
881 | static inline unsigned int irq_alloc_hwirq(int node) | |
882 | { | |
883 | return irq_alloc_hwirqs(1, node); | |
884 | } | |
885 | void irq_free_hwirqs(unsigned int from, int cnt); | |
886 | static inline void irq_free_hwirq(unsigned int irq) | |
887 | { | |
888 | return irq_free_hwirqs(irq, 1); | |
889 | } | |
890 | int arch_setup_hwirq(unsigned int irq, int node); | |
891 | void arch_teardown_hwirq(unsigned int irq); | |
892 | #endif | |
893 | ||
c940e01c TG |
894 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
895 | void irq_init_desc(unsigned int irq); | |
896 | #endif | |
897 | ||
7d828062 TG |
898 | /** |
899 | * struct irq_chip_regs - register offsets for struct irq_gci | |
900 | * @enable: Enable register offset to reg_base | |
901 | * @disable: Disable register offset to reg_base | |
902 | * @mask: Mask register offset to reg_base | |
903 | * @ack: Ack register offset to reg_base | |
904 | * @eoi: Eoi register offset to reg_base | |
905 | * @type: Type configuration register offset to reg_base | |
906 | * @polarity: Polarity configuration register offset to reg_base | |
907 | */ | |
908 | struct irq_chip_regs { | |
909 | unsigned long enable; | |
910 | unsigned long disable; | |
911 | unsigned long mask; | |
912 | unsigned long ack; | |
913 | unsigned long eoi; | |
914 | unsigned long type; | |
915 | unsigned long polarity; | |
916 | }; | |
917 | ||
918 | /** | |
919 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
920 | * @chip: The real interrupt chip which provides the callbacks | |
921 | * @regs: Register offsets for this chip | |
922 | * @handler: Flow handler associated with this chip | |
923 | * @type: Chip can handle these flow types | |
899f0e66 GF |
924 | * @mask_cache_priv: Cached mask register private to the chip type |
925 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
926 | * |
927 | * A irq_generic_chip can have several instances of irq_chip_type when | |
928 | * it requires different functions and register offsets for different | |
929 | * flow types. | |
930 | */ | |
931 | struct irq_chip_type { | |
932 | struct irq_chip chip; | |
933 | struct irq_chip_regs regs; | |
934 | irq_flow_handler_t handler; | |
935 | u32 type; | |
899f0e66 GF |
936 | u32 mask_cache_priv; |
937 | u32 *mask_cache; | |
7d828062 TG |
938 | }; |
939 | ||
940 | /** | |
941 | * struct irq_chip_generic - Generic irq chip data structure | |
942 | * @lock: Lock to protect register and cache data access | |
943 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
944 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
945 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
be9b22b6 BN |
946 | * @suspend: Function called from core code on suspend once per |
947 | * chip; can be useful instead of irq_chip::suspend to | |
948 | * handle chip details even when no interrupts are in use | |
949 | * @resume: Function called from core code on resume once per chip; | |
950 | * can be useful instead of irq_chip::suspend to handle | |
951 | * chip details even when no interrupts are in use | |
7d828062 TG |
952 | * @irq_base: Interrupt base nr for this chip |
953 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 954 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
955 | * @type_cache: Cached type register |
956 | * @polarity_cache: Cached polarity register | |
957 | * @wake_enabled: Interrupt can wakeup from suspend | |
958 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
959 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
960 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 961 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 962 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 963 | * @domain: irq domain pointer |
cfefd21e | 964 | * @list: List head for keeping track of instances |
7d828062 TG |
965 | * @chip_types: Array of interrupt irq_chip_types |
966 | * | |
967 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
968 | * implementations which can be associated to a particular irq line of | |
969 | * an irq_chip_generic instance. That allows to share and protect | |
970 | * state in an irq_chip_generic instance when we need to implement | |
971 | * different flow mechanisms (level/edge) for it. | |
972 | */ | |
973 | struct irq_chip_generic { | |
974 | raw_spinlock_t lock; | |
975 | void __iomem *reg_base; | |
2b280376 KC |
976 | u32 (*reg_readl)(void __iomem *addr); |
977 | void (*reg_writel)(u32 val, void __iomem *addr); | |
be9b22b6 BN |
978 | void (*suspend)(struct irq_chip_generic *gc); |
979 | void (*resume)(struct irq_chip_generic *gc); | |
7d828062 TG |
980 | unsigned int irq_base; |
981 | unsigned int irq_cnt; | |
982 | u32 mask_cache; | |
983 | u32 type_cache; | |
984 | u32 polarity_cache; | |
985 | u32 wake_enabled; | |
986 | u32 wake_active; | |
987 | unsigned int num_ct; | |
988 | void *private; | |
088f40b7 | 989 | unsigned long installed; |
e8bd834f | 990 | unsigned long unused; |
088f40b7 | 991 | struct irq_domain *domain; |
cfefd21e | 992 | struct list_head list; |
7d828062 TG |
993 | struct irq_chip_type chip_types[0]; |
994 | }; | |
995 | ||
996 | /** | |
997 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
998 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
999 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
1000 | * irq chips which need to call irq_set_wake() on | |
1001 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 1002 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 1003 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
b7905595 | 1004 | * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) |
7d828062 TG |
1005 | */ |
1006 | enum irq_gc_flags { | |
1007 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
1008 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 1009 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 1010 | IRQ_GC_NO_MASK = 1 << 3, |
b7905595 | 1011 | IRQ_GC_BE_IO = 1 << 4, |
7d828062 TG |
1012 | }; |
1013 | ||
088f40b7 TG |
1014 | /* |
1015 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
1016 | * @irqs_per_chip: Number of interrupts per chip | |
1017 | * @num_chips: Number of chips | |
1018 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
1019 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
1020 | * @gc_flags: Generic chip specific setup flags | |
1021 | * @gc: Array of pointers to generic interrupt chips | |
1022 | */ | |
1023 | struct irq_domain_chip_generic { | |
1024 | unsigned int irqs_per_chip; | |
1025 | unsigned int num_chips; | |
1026 | unsigned int irq_flags_to_clear; | |
1027 | unsigned int irq_flags_to_set; | |
1028 | enum irq_gc_flags gc_flags; | |
1029 | struct irq_chip_generic *gc[0]; | |
1030 | }; | |
1031 | ||
7d828062 TG |
1032 | /* Generic chip callback functions */ |
1033 | void irq_gc_noop(struct irq_data *d); | |
1034 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
1035 | void irq_gc_mask_set_bit(struct irq_data *d); | |
1036 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
1037 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
1038 | void irq_gc_ack_set_bit(struct irq_data *d); |
1039 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
20608924 | 1040 | void irq_gc_mask_disable_and_ack_set(struct irq_data *d); |
7d828062 TG |
1041 | void irq_gc_eoi(struct irq_data *d); |
1042 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
1043 | ||
1044 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
1045 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
1046 | irq_hw_number_t hw_irq); | |
7d828062 TG |
1047 | struct irq_chip_generic * |
1048 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
1049 | void __iomem *reg_base, irq_flow_handler_t handler); | |
1050 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
1051 | enum irq_gc_flags flags, unsigned int clr, | |
1052 | unsigned int set); | |
1053 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
1054 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
1055 | unsigned int clr, unsigned int set); | |
7d828062 | 1056 | |
1c3e3630 BG |
1057 | struct irq_chip_generic * |
1058 | devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, | |
1059 | unsigned int irq_base, void __iomem *reg_base, | |
1060 | irq_flow_handler_t handler); | |
30fd8fc5 BG |
1061 | int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, |
1062 | u32 msk, enum irq_gc_flags flags, | |
1063 | unsigned int clr, unsigned int set); | |
1c3e3630 | 1064 | |
088f40b7 | 1065 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
088f40b7 | 1066 | |
f88eecfe SF |
1067 | int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, |
1068 | int num_ct, const char *name, | |
1069 | irq_flow_handler_t handler, | |
1070 | unsigned int clr, unsigned int set, | |
1071 | enum irq_gc_flags flags); | |
1072 | ||
1073 | #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ | |
1074 | handler, clr, set, flags) \ | |
1075 | ({ \ | |
1076 | MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ | |
1077 | __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ | |
1078 | handler, clr, set, flags); \ | |
1079 | }) | |
088f40b7 | 1080 | |
707188f5 BG |
1081 | static inline void irq_free_generic_chip(struct irq_chip_generic *gc) |
1082 | { | |
1083 | kfree(gc); | |
1084 | } | |
1085 | ||
32bb6cbb BG |
1086 | static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, |
1087 | u32 msk, unsigned int clr, | |
1088 | unsigned int set) | |
1089 | { | |
1090 | irq_remove_generic_chip(gc, msk, clr, set); | |
1091 | irq_free_generic_chip(gc); | |
1092 | } | |
1093 | ||
7d828062 TG |
1094 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
1095 | { | |
1096 | return container_of(d->chip, struct irq_chip_type, chip); | |
1097 | } | |
1098 | ||
1099 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
1100 | ||
1101 | #ifdef CONFIG_SMP | |
1102 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
1103 | { | |
1104 | raw_spin_lock(&gc->lock); | |
1105 | } | |
1106 | ||
1107 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
1108 | { | |
1109 | raw_spin_unlock(&gc->lock); | |
1110 | } | |
1111 | #else | |
1112 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
1113 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
1114 | #endif | |
1115 | ||
ebf9ff75 BB |
1116 | /* |
1117 | * The irqsave variants are for usage in non interrupt code. Do not use | |
1118 | * them in irq_chip callbacks. Use irq_gc_lock() instead. | |
1119 | */ | |
1120 | #define irq_gc_lock_irqsave(gc, flags) \ | |
1121 | raw_spin_lock_irqsave(&(gc)->lock, flags) | |
1122 | ||
1123 | #define irq_gc_unlock_irqrestore(gc, flags) \ | |
1124 | raw_spin_unlock_irqrestore(&(gc)->lock, flags) | |
1125 | ||
332fd7c4 KC |
1126 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
1127 | u32 val, int reg_offset) | |
1128 | { | |
2b280376 KC |
1129 | if (gc->reg_writel) |
1130 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
1131 | else | |
1132 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
1133 | } |
1134 | ||
1135 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
1136 | int reg_offset) | |
1137 | { | |
2b280376 KC |
1138 | if (gc->reg_readl) |
1139 | return gc->reg_readl(gc->reg_base + reg_offset); | |
1140 | else | |
1141 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
1142 | } |
1143 | ||
2f75d9e1 TG |
1144 | struct irq_matrix; |
1145 | struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, | |
1146 | unsigned int alloc_start, | |
1147 | unsigned int alloc_end); | |
1148 | void irq_matrix_online(struct irq_matrix *m); | |
1149 | void irq_matrix_offline(struct irq_matrix *m); | |
1150 | void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); | |
1151 | int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); | |
1152 | void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); | |
1153 | int irq_matrix_alloc_managed(struct irq_matrix *m, unsigned int cpu); | |
1154 | void irq_matrix_reserve(struct irq_matrix *m); | |
1155 | void irq_matrix_remove_reserved(struct irq_matrix *m); | |
1156 | int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, | |
1157 | bool reserved, unsigned int *mapped_cpu); | |
1158 | void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, | |
1159 | unsigned int bit, bool managed); | |
1160 | void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); | |
1161 | unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); | |
1162 | unsigned int irq_matrix_allocated(struct irq_matrix *m); | |
1163 | unsigned int irq_matrix_reserved(struct irq_matrix *m); | |
1164 | void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); | |
1165 | ||
d17bf24e QY |
1166 | /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ |
1167 | #define INVALID_HWIRQ (~0UL) | |
f9bce791 | 1168 | irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); |
3b8e29a8 QY |
1169 | int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); |
1170 | int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); | |
1171 | int ipi_send_single(unsigned int virq, unsigned int cpu); | |
1172 | int ipi_send_mask(unsigned int virq, const struct cpumask *dest); | |
d17bf24e | 1173 | |
caacdbf4 PD |
1174 | #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER |
1175 | /* | |
1176 | * Registers a generic IRQ handling function as the top-level IRQ handler in | |
1177 | * the system, which is generally the first C code called from an assembly | |
1178 | * architecture-specific interrupt handler. | |
1179 | * | |
1180 | * Returns 0 on success, or -EBUSY if an IRQ handler has already been | |
1181 | * registered. | |
1182 | */ | |
1183 | int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); | |
1184 | ||
1185 | /* | |
1186 | * Allows interrupt handlers to find the irqchip that's been registered as the | |
1187 | * top-level IRQ handler. | |
1188 | */ | |
1189 | extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; | |
1190 | #endif | |
1191 | ||
06fcb0c6 | 1192 | #endif /* _LINUX_IRQ_H */ |