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CommitLineData
06fcb0c6
IM
1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
1da177e4
LT
3
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
23f9b317 12#include <linux/smp.h>
1da177e4 13
06fcb0c6 14#ifndef CONFIG_S390
1da177e4
LT
15
16#include <linux/linkage.h>
17#include <linux/cache.h>
18#include <linux/spinlock.h>
19#include <linux/cpumask.h>
908dcecd 20#include <linux/irqreturn.h>
dd3a1db9 21#include <linux/irqnr.h>
77904fd6 22#include <linux/errno.h>
1da177e4
LT
23
24#include <asm/irq.h>
25#include <asm/ptrace.h>
7d12e780 26#include <asm/irq_regs.h>
1da177e4 27
57a58a94 28struct irq_desc;
ec701584 29typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780 30 struct irq_desc *desc);
57a58a94
DH
31
32
1da177e4
LT
33/*
34 * IRQ line status.
6e213616 35 *
950f4427 36 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616
TG
37 *
38 * IRQ types
1da177e4 39 */
6e213616
TG
40#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
41#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
42#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
43#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
44#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
45#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
46#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
47#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
48
49/* Internal flags */
950f4427
TG
50#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
51#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
52#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
53#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
54#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
55#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
56#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
57#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
58#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
59#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
60#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
61#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33
IM
62#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
63#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
64#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850 65#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
72b1e22d 66#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
950f4427 67
0d7012a9 68#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 69# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427 70# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
f26fdd59
KW
71#else
72# define CHECK_IRQ_PER_CPU(var) 0
950f4427 73# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59 74#endif
1da177e4 75
6a6de9ef 76struct proc_dir_entry;
5b912c10 77struct msi_desc;
6a6de9ef 78
8fee5c36 79/**
6a6de9ef 80 * struct irq_chip - hardware interrupt chip descriptor
8fee5c36
IM
81 *
82 * @name: name for /proc/interrupts
83 * @startup: start up the interrupt (defaults to ->enable if NULL)
84 * @shutdown: shut down the interrupt (defaults to ->disable if NULL)
85 * @enable: enable the interrupt (defaults to chip->unmask if NULL)
86 * @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36
IM
87 * @ack: start of a new interrupt
88 * @mask: mask an interrupt source
89 * @mask_ack: ack and mask an interrupt source
90 * @unmask: unmask an interrupt source
47c2a3aa
IM
91 * @eoi: end of interrupt - chip level
92 * @end: end of interrupt - flow level
8fee5c36
IM
93 * @set_affinity: set the CPU affinity on SMP machines
94 * @retrigger: resend an IRQ to the CPU
95 * @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
96 * @set_wake: enable/disable power-management wake-on of an IRQ
97 *
98 * @release: release function solely used by UML
6a6de9ef 99 * @typename: obsoleted by name, kept as migration helper
1da177e4 100 */
6a6de9ef
TG
101struct irq_chip {
102 const char *name;
71d218b7
IM
103 unsigned int (*startup)(unsigned int irq);
104 void (*shutdown)(unsigned int irq);
105 void (*enable)(unsigned int irq);
106 void (*disable)(unsigned int irq);
6a6de9ef 107
71d218b7 108 void (*ack)(unsigned int irq);
6a6de9ef
TG
109 void (*mask)(unsigned int irq);
110 void (*mask_ack)(unsigned int irq);
111 void (*unmask)(unsigned int irq);
47c2a3aa 112 void (*eoi)(unsigned int irq);
6a6de9ef 113
71d218b7
IM
114 void (*end)(unsigned int irq);
115 void (*set_affinity)(unsigned int irq, cpumask_t dest);
c0ad90a3 116 int (*retrigger)(unsigned int irq);
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TG
117 int (*set_type)(unsigned int irq, unsigned int flow_type);
118 int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3 119
b77d6adc
PBG
120 /* Currently used only by UML, might disappear one day.*/
121#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7 122 void (*release)(unsigned int irq, void *dev_id);
b77d6adc 123#endif
6a6de9ef
TG
124 /*
125 * For compatibility, ->typename is copied into ->name.
126 * Will disappear.
127 */
128 const char *typename;
1da177e4
LT
129};
130
8fee5c36
IM
131/**
132 * struct irq_desc - interrupt descriptor
133 *
6a6de9ef
TG
134 * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
135 * @chip: low level interrupt hardware access
472900b8 136 * @msi_desc: MSI descriptor
6a6de9ef
TG
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @chip_data: platform-specific per-chip private data for the chip
139 * methods, to allow shared chip implementations
8fee5c36
IM
140 * @action: the irq action chain
141 * @status: status information
142 * @depth: disable-depth, for nested irq_disable() calls
15a647eb 143 * @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36
IM
144 * @irq_count: stats field to detect stalled irqs
145 * @irqs_unhandled: stats field for spurious unhandled interrupts
5ac4d823 146 * @last_unhandled: aging timer for unhandled count
8fee5c36
IM
147 * @lock: locking for SMP
148 * @affinity: IRQ affinity on SMP
6a6de9ef 149 * @cpu: cpu index useful for balancing
8fee5c36 150 * @pending_mask: pending rebalanced interrupts
8fee5c36
IM
151 * @dir: /proc/irq/ procfs entry
152 * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
a460e745 153 * @name: flow handler name for /proc/interrupts output
1da177e4 154 */
34ffdb72 155struct irq_desc {
08678b08 156 unsigned int irq;
57a58a94 157 irq_flow_handler_t handle_irq;
6a6de9ef 158 struct irq_chip *chip;
5b912c10 159 struct msi_desc *msi_desc;
6a6de9ef 160 void *handler_data;
71d218b7
IM
161 void *chip_data;
162 struct irqaction *action; /* IRQ action list */
163 unsigned int status; /* IRQ status */
6a6de9ef 164
71d218b7 165 unsigned int depth; /* nested irq disables */
15a647eb 166 unsigned int wake_depth; /* nested wake enables */
71d218b7
IM
167 unsigned int irq_count; /* For detecting broken IRQs */
168 unsigned int irqs_unhandled;
4f27c00b 169 unsigned long last_unhandled; /* Aging timer for unhandled count */
71d218b7 170 spinlock_t lock;
a53da52f 171#ifdef CONFIG_SMP
71d218b7 172 cpumask_t affinity;
6a6de9ef 173 unsigned int cpu;
a53da52f 174#endif
8b8e8c1b 175#ifdef CONFIG_GENERIC_PENDING_IRQ
cd916d31 176 cpumask_t pending_mask;
54d5d424 177#endif
4a733ee1 178#ifdef CONFIG_PROC_FS
a460e745 179 struct proc_dir_entry *dir;
4a733ee1 180#endif
a460e745 181 const char *name;
e729aa16 182} ____cacheline_internodealigned_in_smp;
1da177e4 183
9059d8fa 184
34ffdb72 185extern struct irq_desc irq_desc[NR_IRQS];
9059d8fa 186
c6b7674f
TG
187static inline struct irq_desc *irq_to_desc(unsigned int irq)
188{
189 return (irq < nr_irqs) ? irq_desc + irq : NULL;
190}
191
34ffdb72
IM
192/*
193 * Migration helpers for obsolete names, they will go away:
194 */
6a6de9ef
TG
195#define hw_interrupt_type irq_chip
196typedef struct irq_chip hw_irq_controller;
197#define no_irq_type no_irq_chip
34ffdb72
IM
198typedef struct irq_desc irq_desc_t;
199
200/*
201 * Pick up the arch-dependent methods:
202 */
203#include <asm/hw_irq.h>
1da177e4 204
06fcb0c6 205extern int setup_irq(unsigned int irq, struct irqaction *new);
1da177e4
LT
206
207#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6 208
54d5d424
AR
209#ifdef CONFIG_SMP
210
8b8e8c1b 211#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424 212
c777ac55
AM
213void set_pending_irq(unsigned int irq, cpumask_t mask);
214void move_native_irq(int irq);
e7b946e9 215void move_masked_irq(int irq);
54d5d424 216
8b8e8c1b 217#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6
IM
218
219static inline void move_irq(int irq)
220{
221}
222
223static inline void move_native_irq(int irq)
224{
225}
226
e7b946e9
EB
227static inline void move_masked_irq(int irq)
228{
229}
230
06fcb0c6
IM
231static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
232{
233}
54d5d424 234
06fcb0c6 235#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424 236
06fcb0c6 237#else /* CONFIG_SMP */
54d5d424 238
54d5d424 239#define move_native_irq(x)
e7b946e9 240#define move_masked_irq(x)
54d5d424 241
06fcb0c6 242#endif /* CONFIG_SMP */
54d5d424 243
1da177e4 244extern int no_irq_affinity;
1da177e4 245
950f4427
TG
246static inline int irq_balancing_disabled(unsigned int irq)
247{
08678b08
YL
248 struct irq_desc *desc;
249
250 desc = irq_to_desc(irq);
251 return desc->status & IRQ_NO_BALANCING_MASK;
950f4427
TG
252}
253
6a6de9ef 254/* Handle irq action chains: */
7d12e780 255extern int handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef
TG
256
257/*
258 * Built-in IRQ handlers for various IRQ types,
259 * callable via desc->chip->handle_irq()
260 */
ec701584
HH
261extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
262extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
263extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
264extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
265extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
266extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
6a6de9ef 267
2e60bbb6 268/*
6a6de9ef 269 * Monolithic do_IRQ implementation.
2e60bbb6 270 */
af8c65b5 271#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584 272extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5 273#endif
2e60bbb6 274
dae86204
IM
275/*
276 * Architectures call this to let the generic IRQ layer
277 * handle an interrupt. If the descriptor is attached to an
278 * irqchip-style controller then we call the ->handle_irq() handler,
279 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
280 */
46926b67 281static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204 282{
af8c65b5 283#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780 284 desc->handle_irq(irq, desc);
af8c65b5 285#else
dae86204 286 if (likely(desc->handle_irq))
7d12e780 287 desc->handle_irq(irq, desc);
dae86204 288 else
7d12e780 289 __do_IRQ(irq);
af8c65b5 290#endif
dae86204
IM
291}
292
46926b67
YL
293static inline void generic_handle_irq(unsigned int irq)
294{
295 generic_handle_irq_desc(irq, irq_to_desc(irq));
296}
297
6a6de9ef 298/* Handling of unhandled and spurious interrupts: */
34ffdb72 299extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
7d12e780 300 int action_ret);
1da177e4 301
a4633adc
TG
302/* Resending of interrupts :*/
303void check_irq_resend(struct irq_desc *desc, unsigned int irq);
304
6a6de9ef
TG
305/* Enable/disable irq debugging output: */
306extern int noirqdebug_setup(char *str);
307
308/* Checks whether the interrupt can be requested by request_irq(): */
309extern int can_request_irq(unsigned int irq, unsigned long irqflags);
310
f8b5473f 311/* Dummy irq-chip implementations: */
6a6de9ef 312extern struct irq_chip no_irq_chip;
f8b5473f 313extern struct irq_chip dummy_irq_chip;
6a6de9ef 314
145fc655
IM
315extern void
316set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
317 irq_flow_handler_t handle);
6a6de9ef 318extern void
a460e745
IM
319set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
320 irq_flow_handler_t handle, const char *name);
321
6a6de9ef 322extern void
a460e745
IM
323__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
324 const char *name);
1da177e4 325
b019e573
KH
326/* caller has locked the irq_desc and both params are valid */
327static inline void __set_irq_handler_unlocked(int irq,
328 irq_flow_handler_t handler)
329{
08678b08
YL
330 struct irq_desc *desc;
331
332 desc = irq_to_desc(irq);
333 desc->handle_irq = handler;
b019e573
KH
334}
335
6a6de9ef
TG
336/*
337 * Set a highlevel flow handler for a given IRQ:
338 */
339static inline void
57a58a94 340set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef 341{
a460e745 342 __set_irq_handler(irq, handle, 0, NULL);
6a6de9ef
TG
343}
344
345/*
346 * Set a highlevel chained flow handler for a given IRQ.
347 * (a chained handler is automatically enabled and set to
348 * IRQ_NOREQUEST and IRQ_NOPROBE)
349 */
350static inline void
351set_irq_chained_handler(unsigned int irq,
57a58a94 352 irq_flow_handler_t handle)
6a6de9ef 353{
a460e745 354 __set_irq_handler(irq, handle, 1, NULL);
6a6de9ef
TG
355}
356
46f4f8f6
RB
357extern void set_irq_noprobe(unsigned int irq);
358extern void set_irq_probe(unsigned int irq);
359
3a16d713 360/* Handle dynamic irq creation and destruction */
6d50bc26 361extern unsigned int create_irq_nr(unsigned int irq_want);
3a16d713
EB
362extern int create_irq(void);
363extern void destroy_irq(unsigned int irq);
364
1f80025e
EB
365/* Test to see if a driver has successfully requested an irq */
366static inline int irq_has_action(unsigned int irq)
367{
08678b08 368 struct irq_desc *desc = irq_to_desc(irq);
1f80025e
EB
369 return desc->action != NULL;
370}
371
3a16d713
EB
372/* Dynamic irq helper functions */
373extern void dynamic_irq_init(unsigned int irq);
374extern void dynamic_irq_cleanup(unsigned int irq);
dd87eb3a 375
3a16d713 376/* Set/get chip/data for an IRQ: */
dd87eb3a
TG
377extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
378extern int set_irq_data(unsigned int irq, void *data);
379extern int set_irq_chip_data(unsigned int irq, void *data);
380extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10 381extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a 382
08678b08
YL
383#define get_irq_chip(irq) (irq_to_desc(irq)->chip)
384#define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data)
385#define get_irq_data(irq) (irq_to_desc(irq)->handler_data)
386#define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc)
dd87eb3a 387
6a6de9ef 388#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4 389
06fcb0c6 390#endif /* !CONFIG_S390 */
1da177e4 391
06fcb0c6 392#endif /* _LINUX_IRQ_H */