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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
908dcecd | 18 | #include <linux/irqreturn.h> |
dd3a1db9 | 19 | #include <linux/irqnr.h> |
77904fd6 | 20 | #include <linux/errno.h> |
503e5763 | 21 | #include <linux/topology.h> |
3aa551c9 | 22 | #include <linux/wait.h> |
1da177e4 LT |
23 | |
24 | #include <asm/irq.h> | |
25 | #include <asm/ptrace.h> | |
7d12e780 | 26 | #include <asm/irq_regs.h> |
1da177e4 | 27 | |
ab7798ff | 28 | struct seq_file; |
ec53cf23 | 29 | struct module; |
57a58a94 | 30 | struct irq_desc; |
78129576 | 31 | struct irq_data; |
ec701584 | 32 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 33 | struct irq_desc *desc); |
78129576 | 34 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 35 | |
1da177e4 LT |
36 | /* |
37 | * IRQ line status. | |
6e213616 | 38 | * |
5d4d8fc9 TG |
39 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
40 | * | |
41 | * IRQ_TYPE_NONE - default, unspecified type | |
42 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
43 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
44 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
45 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
46 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
47 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
48 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
49 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
50 | * to setup the HW to a sane default (used | |
51 | * by irqdomain map() callbacks to synchronize | |
52 | * the HW state and SW flags for a newly | |
53 | * allocated descriptor). | |
54 | * | |
5d4d8fc9 TG |
55 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
56 | * | |
57 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
58 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
59 | * updated in the code when the above trigger | |
0911f124 | 60 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
61 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
62 | * it from affinity setting | |
63 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
64 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
65 | * request_irq() | |
7f1b1244 | 66 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
67 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
68 | * request/setup_irq() | |
69 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
70 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
71 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
31d9d9b6 | 72 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
73 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
74 | * it from the spurious interrupt detection | |
75 | * mechanism and from core side polling. | |
1da177e4 | 76 | */ |
5d4d8fc9 TG |
77 | enum { |
78 | IRQ_TYPE_NONE = 0x00000000, | |
79 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
80 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
81 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
82 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
83 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
84 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
85 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 86 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
87 | |
88 | IRQ_TYPE_PROBE = 0x00000010, | |
89 | ||
90 | IRQ_LEVEL = (1 << 8), | |
91 | IRQ_PER_CPU = (1 << 9), | |
92 | IRQ_NOPROBE = (1 << 10), | |
93 | IRQ_NOREQUEST = (1 << 11), | |
94 | IRQ_NOAUTOEN = (1 << 12), | |
95 | IRQ_NO_BALANCING = (1 << 13), | |
96 | IRQ_MOVE_PCNTXT = (1 << 14), | |
97 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 98 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 99 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 100 | IRQ_IS_POLLED = (1 << 18), |
5d4d8fc9 | 101 | }; |
950f4427 | 102 | |
44247184 TG |
103 | #define IRQF_MODIFY_MASK \ |
104 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 105 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd TG |
106 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
107 | IRQ_IS_POLLED) | |
44247184 | 108 | |
8f53f924 TG |
109 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
110 | ||
3b8249e7 TG |
111 | /* |
112 | * Return value for chip->irq_set_affinity() | |
113 | * | |
114 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
115 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
116 | */ | |
117 | enum { | |
118 | IRQ_SET_MASK_OK = 0, | |
119 | IRQ_SET_MASK_OK_NOCOPY, | |
120 | }; | |
121 | ||
5b912c10 | 122 | struct msi_desc; |
08a543ad | 123 | struct irq_domain; |
6a6de9ef | 124 | |
ff7dcd44 TG |
125 | /** |
126 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
966dc736 | 127 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 128 | * @irq: interrupt number |
08a543ad | 129 | * @hwirq: hardware interrupt number, local to the interrupt domain |
ff7dcd44 | 130 | * @node: node index useful for balancing |
30398bf6 | 131 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 132 | * Use accessor functions to deal with it |
ff7dcd44 | 133 | * @chip: low level interrupt hardware access |
08a543ad GL |
134 | * @domain: Interrupt translation domain; responsible for mapping |
135 | * between hwirq number and linux irq number. | |
ff7dcd44 TG |
136 | * @handler_data: per-IRQ data for the irq_chip methods |
137 | * @chip_data: platform-specific per-chip private data for the chip | |
138 | * methods, to allow shared chip implementations | |
139 | * @msi_desc: MSI descriptor | |
140 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
141 | * |
142 | * The fields here need to overlay the ones in irq_desc until we | |
143 | * cleaned up the direct references and switched everything over to | |
144 | * irq_data. | |
145 | */ | |
146 | struct irq_data { | |
966dc736 | 147 | u32 mask; |
ff7dcd44 | 148 | unsigned int irq; |
08a543ad | 149 | unsigned long hwirq; |
ff7dcd44 | 150 | unsigned int node; |
91c49917 | 151 | unsigned int state_use_accessors; |
ff7dcd44 | 152 | struct irq_chip *chip; |
08a543ad | 153 | struct irq_domain *domain; |
ff7dcd44 TG |
154 | void *handler_data; |
155 | void *chip_data; | |
156 | struct msi_desc *msi_desc; | |
ff7dcd44 | 157 | cpumask_var_t affinity; |
ff7dcd44 TG |
158 | }; |
159 | ||
f230b6d5 TG |
160 | /* |
161 | * Bit masks for irq_data.state | |
162 | * | |
876dbd4c | 163 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 164 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
165 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
166 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 167 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 168 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
169 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
170 | * from suspend | |
e1ef8241 TG |
171 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
172 | * context | |
32f4125e TG |
173 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
174 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
175 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 176 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
f230b6d5 TG |
177 | */ |
178 | enum { | |
876dbd4c | 179 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
180 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
181 | IRQD_NO_BALANCING = (1 << 10), | |
182 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 183 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 184 | IRQD_LEVEL = (1 << 13), |
7f94226f | 185 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 186 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 187 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
188 | IRQD_IRQ_MASKED = (1 << 17), |
189 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 190 | IRQD_WAKEUP_ARMED = (1 << 19), |
f230b6d5 TG |
191 | }; |
192 | ||
193 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
194 | { | |
195 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
196 | } | |
197 | ||
a005677b TG |
198 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
199 | { | |
200 | return d->state_use_accessors & IRQD_PER_CPU; | |
201 | } | |
202 | ||
203 | static inline bool irqd_can_balance(struct irq_data *d) | |
204 | { | |
205 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
206 | } | |
207 | ||
2bdd1055 TG |
208 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
209 | { | |
210 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
211 | } | |
212 | ||
ee38c04b TG |
213 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
214 | { | |
215 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
216 | } | |
217 | ||
876dbd4c TG |
218 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
219 | { | |
220 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Must only be called inside irq_chip.irq_set_type() functions. | |
225 | */ | |
226 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
227 | { | |
228 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
229 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
230 | } | |
231 | ||
232 | static inline bool irqd_is_level_type(struct irq_data *d) | |
233 | { | |
234 | return d->state_use_accessors & IRQD_LEVEL; | |
235 | } | |
236 | ||
7f94226f TG |
237 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
238 | { | |
239 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
240 | } | |
241 | ||
e1ef8241 TG |
242 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
243 | { | |
244 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
245 | } | |
246 | ||
801a0e9a TG |
247 | static inline bool irqd_irq_disabled(struct irq_data *d) |
248 | { | |
249 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
250 | } | |
251 | ||
32f4125e TG |
252 | static inline bool irqd_irq_masked(struct irq_data *d) |
253 | { | |
254 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
255 | } | |
256 | ||
257 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
258 | { | |
259 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
260 | } | |
261 | ||
b76f1674 TG |
262 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
263 | { | |
264 | return d->state_use_accessors & IRQD_WAKEUP_ARMED; | |
265 | } | |
266 | ||
267 | ||
9cff60df TG |
268 | /* |
269 | * Functions for chained handlers which can be enabled/disabled by the | |
270 | * standard disable_irq/enable_irq calls. Must be called with | |
271 | * irq_desc->lock held. | |
272 | */ | |
273 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
274 | { | |
275 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
276 | } | |
277 | ||
278 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
279 | { | |
280 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
281 | } | |
282 | ||
a699e4e4 GL |
283 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
284 | { | |
285 | return d->hwirq; | |
286 | } | |
287 | ||
8fee5c36 | 288 | /** |
6a6de9ef | 289 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
290 | * |
291 | * @name: name for /proc/interrupts | |
f8822657 TG |
292 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
293 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
294 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
295 | * @irq_disable: disable the interrupt | |
296 | * @irq_ack: start of a new interrupt | |
297 | * @irq_mask: mask an interrupt source | |
298 | * @irq_mask_ack: ack and mask an interrupt source | |
299 | * @irq_unmask: unmask an interrupt source | |
300 | * @irq_eoi: end of interrupt | |
301 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
302 | * @irq_retrigger: resend an IRQ to the CPU | |
303 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
304 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
305 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
306 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
307 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
308 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
cfefd21e TG |
309 | * @irq_suspend: function called from core code on suspend once per chip |
310 | * @irq_resume: function called from core code on resume once per chip | |
311 | * @irq_pm_shutdown: function called from core code on shutdown once per chip | |
d0051816 | 312 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 313 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
314 | * @irq_request_resources: optional to request resources before calling |
315 | * any other callback related to this irq | |
316 | * @irq_release_resources: optional to release resources acquired with | |
317 | * irq_request_resources | |
2bff17ad | 318 | * @flags: chip specific flags |
1da177e4 | 319 | */ |
6a6de9ef TG |
320 | struct irq_chip { |
321 | const char *name; | |
f8822657 TG |
322 | unsigned int (*irq_startup)(struct irq_data *data); |
323 | void (*irq_shutdown)(struct irq_data *data); | |
324 | void (*irq_enable)(struct irq_data *data); | |
325 | void (*irq_disable)(struct irq_data *data); | |
326 | ||
327 | void (*irq_ack)(struct irq_data *data); | |
328 | void (*irq_mask)(struct irq_data *data); | |
329 | void (*irq_mask_ack)(struct irq_data *data); | |
330 | void (*irq_unmask)(struct irq_data *data); | |
331 | void (*irq_eoi)(struct irq_data *data); | |
332 | ||
333 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
334 | int (*irq_retrigger)(struct irq_data *data); | |
335 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
336 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
337 | ||
338 | void (*irq_bus_lock)(struct irq_data *data); | |
339 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
340 | ||
0fdb4b25 DD |
341 | void (*irq_cpu_online)(struct irq_data *data); |
342 | void (*irq_cpu_offline)(struct irq_data *data); | |
343 | ||
cfefd21e TG |
344 | void (*irq_suspend)(struct irq_data *data); |
345 | void (*irq_resume)(struct irq_data *data); | |
346 | void (*irq_pm_shutdown)(struct irq_data *data); | |
347 | ||
d0051816 TG |
348 | void (*irq_calc_mask)(struct irq_data *data); |
349 | ||
ab7798ff | 350 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
351 | int (*irq_request_resources)(struct irq_data *data); |
352 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 353 | |
2bff17ad | 354 | unsigned long flags; |
1da177e4 LT |
355 | }; |
356 | ||
d4d5e089 TG |
357 | /* |
358 | * irq_chip specific flags | |
359 | * | |
77694b40 TG |
360 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
361 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 362 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
363 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
364 | * when irq enabled | |
60f96b41 | 365 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 366 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 367 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
368 | */ |
369 | enum { | |
370 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 371 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 372 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 373 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 374 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 375 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 376 | IRQCHIP_EOI_THREADED = (1 << 6), |
d4d5e089 TG |
377 | }; |
378 | ||
e144710b TG |
379 | /* This include will go away once we isolated irq_desc usage to core code */ |
380 | #include <linux/irqdesc.h> | |
0b8f1efa | 381 | |
34ffdb72 IM |
382 | /* |
383 | * Pick up the arch-dependent methods: | |
384 | */ | |
385 | #include <asm/hw_irq.h> | |
1da177e4 | 386 | |
b683de2b TG |
387 | #ifndef NR_IRQS_LEGACY |
388 | # define NR_IRQS_LEGACY 0 | |
389 | #endif | |
390 | ||
1318a481 TG |
391 | #ifndef ARCH_IRQ_INIT_FLAGS |
392 | # define ARCH_IRQ_INIT_FLAGS 0 | |
393 | #endif | |
394 | ||
c1594b77 | 395 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 396 | |
e144710b | 397 | struct irqaction; |
06fcb0c6 | 398 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 399 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
400 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
401 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 402 | |
0fdb4b25 DD |
403 | extern void irq_cpu_online(void); |
404 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
405 | extern int irq_set_affinity_locked(struct irq_data *data, |
406 | const struct cpumask *cpumask, bool force); | |
0fdb4b25 | 407 | |
3a3856d0 | 408 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
409 | void irq_move_irq(struct irq_data *data); |
410 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 411 | #else |
a439520f TG |
412 | static inline void irq_move_irq(struct irq_data *data) { } |
413 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 414 | #endif |
54d5d424 | 415 | |
1da177e4 | 416 | extern int no_irq_affinity; |
1da177e4 | 417 | |
293a7a0a TG |
418 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
419 | int irq_set_parent(int irq, int parent_irq); | |
420 | #else | |
421 | static inline int irq_set_parent(int irq, int parent_irq) | |
422 | { | |
423 | return 0; | |
424 | } | |
425 | #endif | |
426 | ||
6a6de9ef TG |
427 | /* |
428 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 429 | * callable via desc->handle_irq() |
6a6de9ef | 430 | */ |
ec701584 HH |
431 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
432 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
433 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 434 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
435 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
436 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
31d9d9b6 | 437 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 | 438 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
31b47cf7 | 439 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 440 | |
6a6de9ef | 441 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 442 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 443 | irqreturn_t action_ret); |
1da177e4 | 444 | |
a4633adc | 445 | |
6a6de9ef TG |
446 | /* Enable/disable irq debugging output: */ |
447 | extern int noirqdebug_setup(char *str); | |
448 | ||
449 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
450 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
451 | ||
f8b5473f | 452 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 453 | extern struct irq_chip no_irq_chip; |
f8b5473f | 454 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 455 | |
145fc655 | 456 | extern void |
3836ca08 | 457 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
458 | irq_flow_handler_t handle, const char *name); |
459 | ||
3836ca08 TG |
460 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
461 | irq_flow_handler_t handle) | |
462 | { | |
463 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
464 | } | |
465 | ||
31d9d9b6 MZ |
466 | extern int irq_set_percpu_devid(unsigned int irq); |
467 | ||
6a6de9ef | 468 | extern void |
3836ca08 | 469 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 470 | const char *name); |
1da177e4 | 471 | |
6a6de9ef | 472 | static inline void |
3836ca08 | 473 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 474 | { |
3836ca08 | 475 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
476 | } |
477 | ||
478 | /* | |
479 | * Set a highlevel chained flow handler for a given IRQ. | |
480 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 481 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
482 | */ |
483 | static inline void | |
3836ca08 | 484 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 485 | { |
3836ca08 | 486 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
487 | } |
488 | ||
44247184 TG |
489 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
490 | ||
491 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
492 | { | |
493 | irq_modify_status(irq, 0, set); | |
494 | } | |
495 | ||
496 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
497 | { | |
498 | irq_modify_status(irq, clr, 0); | |
499 | } | |
500 | ||
a0cd9ca2 | 501 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
502 | { |
503 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
504 | } | |
505 | ||
a0cd9ca2 | 506 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
507 | { |
508 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
509 | } | |
46f4f8f6 | 510 | |
7f1b1244 PM |
511 | static inline void irq_set_nothread(unsigned int irq) |
512 | { | |
513 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
514 | } | |
515 | ||
516 | static inline void irq_set_thread(unsigned int irq) | |
517 | { | |
518 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
519 | } | |
520 | ||
6f91a52d TG |
521 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
522 | { | |
523 | if (nest) | |
524 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
525 | else | |
526 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
527 | } | |
528 | ||
31d9d9b6 MZ |
529 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
530 | { | |
531 | irq_set_status_flags(irq, | |
532 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
533 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
534 | } | |
535 | ||
3a16d713 | 536 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
537 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
538 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
539 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
540 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
541 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
542 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
543 | struct msi_desc *entry); | |
f303a6dd | 544 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 545 | |
a0cd9ca2 | 546 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
547 | { |
548 | struct irq_data *d = irq_get_irq_data(irq); | |
549 | return d ? d->chip : NULL; | |
550 | } | |
551 | ||
552 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
553 | { | |
554 | return d->chip; | |
555 | } | |
556 | ||
a0cd9ca2 | 557 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
558 | { |
559 | struct irq_data *d = irq_get_irq_data(irq); | |
560 | return d ? d->chip_data : NULL; | |
561 | } | |
562 | ||
563 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
564 | { | |
565 | return d->chip_data; | |
566 | } | |
567 | ||
a0cd9ca2 | 568 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
569 | { |
570 | struct irq_data *d = irq_get_irq_data(irq); | |
571 | return d ? d->handler_data : NULL; | |
572 | } | |
573 | ||
a0cd9ca2 | 574 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
575 | { |
576 | return d->handler_data; | |
577 | } | |
578 | ||
a0cd9ca2 | 579 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
580 | { |
581 | struct irq_data *d = irq_get_irq_data(irq); | |
582 | return d ? d->msi_desc : NULL; | |
583 | } | |
584 | ||
585 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
586 | { | |
587 | return d->msi_desc; | |
588 | } | |
589 | ||
1f6236bf JMC |
590 | static inline u32 irq_get_trigger_type(unsigned int irq) |
591 | { | |
592 | struct irq_data *d = irq_get_irq_data(irq); | |
593 | return d ? irqd_get_trigger_type(d) : 0; | |
594 | } | |
595 | ||
62a08ae2 TG |
596 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
597 | ||
b6873807 SAS |
598 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
599 | struct module *owner); | |
600 | ||
ec53cf23 PG |
601 | /* use macros to avoid needing export.h for THIS_MODULE */ |
602 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
603 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 604 | |
ec53cf23 PG |
605 | #define irq_alloc_desc(node) \ |
606 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 607 | |
ec53cf23 PG |
608 | #define irq_alloc_desc_at(at, node) \ |
609 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 610 | |
ec53cf23 PG |
611 | #define irq_alloc_desc_from(from, node) \ |
612 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 613 | |
51906e77 AG |
614 | #define irq_alloc_descs_from(from, cnt, node) \ |
615 | irq_alloc_descs(-1, from, cnt, node) | |
616 | ||
ec53cf23 | 617 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
618 | static inline void irq_free_desc(unsigned int irq) |
619 | { | |
620 | irq_free_descs(irq, 1); | |
621 | } | |
622 | ||
7b6ef126 TG |
623 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
624 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
625 | static inline unsigned int irq_alloc_hwirq(int node) | |
626 | { | |
627 | return irq_alloc_hwirqs(1, node); | |
628 | } | |
629 | void irq_free_hwirqs(unsigned int from, int cnt); | |
630 | static inline void irq_free_hwirq(unsigned int irq) | |
631 | { | |
632 | return irq_free_hwirqs(irq, 1); | |
633 | } | |
634 | int arch_setup_hwirq(unsigned int irq, int node); | |
635 | void arch_teardown_hwirq(unsigned int irq); | |
636 | #endif | |
637 | ||
c940e01c TG |
638 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
639 | void irq_init_desc(unsigned int irq); | |
640 | #endif | |
641 | ||
7d828062 TG |
642 | #ifndef irq_reg_writel |
643 | # define irq_reg_writel(val, addr) writel(val, addr) | |
644 | #endif | |
645 | #ifndef irq_reg_readl | |
646 | # define irq_reg_readl(addr) readl(addr) | |
647 | #endif | |
648 | ||
649 | /** | |
650 | * struct irq_chip_regs - register offsets for struct irq_gci | |
651 | * @enable: Enable register offset to reg_base | |
652 | * @disable: Disable register offset to reg_base | |
653 | * @mask: Mask register offset to reg_base | |
654 | * @ack: Ack register offset to reg_base | |
655 | * @eoi: Eoi register offset to reg_base | |
656 | * @type: Type configuration register offset to reg_base | |
657 | * @polarity: Polarity configuration register offset to reg_base | |
658 | */ | |
659 | struct irq_chip_regs { | |
660 | unsigned long enable; | |
661 | unsigned long disable; | |
662 | unsigned long mask; | |
663 | unsigned long ack; | |
664 | unsigned long eoi; | |
665 | unsigned long type; | |
666 | unsigned long polarity; | |
667 | }; | |
668 | ||
669 | /** | |
670 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
671 | * @chip: The real interrupt chip which provides the callbacks | |
672 | * @regs: Register offsets for this chip | |
673 | * @handler: Flow handler associated with this chip | |
674 | * @type: Chip can handle these flow types | |
899f0e66 GF |
675 | * @mask_cache_priv: Cached mask register private to the chip type |
676 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
677 | * |
678 | * A irq_generic_chip can have several instances of irq_chip_type when | |
679 | * it requires different functions and register offsets for different | |
680 | * flow types. | |
681 | */ | |
682 | struct irq_chip_type { | |
683 | struct irq_chip chip; | |
684 | struct irq_chip_regs regs; | |
685 | irq_flow_handler_t handler; | |
686 | u32 type; | |
899f0e66 GF |
687 | u32 mask_cache_priv; |
688 | u32 *mask_cache; | |
7d828062 TG |
689 | }; |
690 | ||
691 | /** | |
692 | * struct irq_chip_generic - Generic irq chip data structure | |
693 | * @lock: Lock to protect register and cache data access | |
694 | * @reg_base: Register base address (virtual) | |
695 | * @irq_base: Interrupt base nr for this chip | |
696 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 697 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
698 | * @type_cache: Cached type register |
699 | * @polarity_cache: Cached polarity register | |
700 | * @wake_enabled: Interrupt can wakeup from suspend | |
701 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
702 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
703 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 704 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 705 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 706 | * @domain: irq domain pointer |
cfefd21e | 707 | * @list: List head for keeping track of instances |
7d828062 TG |
708 | * @chip_types: Array of interrupt irq_chip_types |
709 | * | |
710 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
711 | * implementations which can be associated to a particular irq line of | |
712 | * an irq_chip_generic instance. That allows to share and protect | |
713 | * state in an irq_chip_generic instance when we need to implement | |
714 | * different flow mechanisms (level/edge) for it. | |
715 | */ | |
716 | struct irq_chip_generic { | |
717 | raw_spinlock_t lock; | |
718 | void __iomem *reg_base; | |
719 | unsigned int irq_base; | |
720 | unsigned int irq_cnt; | |
721 | u32 mask_cache; | |
722 | u32 type_cache; | |
723 | u32 polarity_cache; | |
724 | u32 wake_enabled; | |
725 | u32 wake_active; | |
726 | unsigned int num_ct; | |
727 | void *private; | |
088f40b7 | 728 | unsigned long installed; |
e8bd834f | 729 | unsigned long unused; |
088f40b7 | 730 | struct irq_domain *domain; |
cfefd21e | 731 | struct list_head list; |
7d828062 TG |
732 | struct irq_chip_type chip_types[0]; |
733 | }; | |
734 | ||
735 | /** | |
736 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
737 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
738 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
739 | * irq chips which need to call irq_set_wake() on | |
740 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 741 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 742 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
7d828062 TG |
743 | */ |
744 | enum irq_gc_flags { | |
745 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
746 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 747 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 748 | IRQ_GC_NO_MASK = 1 << 3, |
7d828062 TG |
749 | }; |
750 | ||
088f40b7 TG |
751 | /* |
752 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
753 | * @irqs_per_chip: Number of interrupts per chip | |
754 | * @num_chips: Number of chips | |
755 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
756 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
757 | * @gc_flags: Generic chip specific setup flags | |
758 | * @gc: Array of pointers to generic interrupt chips | |
759 | */ | |
760 | struct irq_domain_chip_generic { | |
761 | unsigned int irqs_per_chip; | |
762 | unsigned int num_chips; | |
763 | unsigned int irq_flags_to_clear; | |
764 | unsigned int irq_flags_to_set; | |
765 | enum irq_gc_flags gc_flags; | |
766 | struct irq_chip_generic *gc[0]; | |
767 | }; | |
768 | ||
7d828062 TG |
769 | /* Generic chip callback functions */ |
770 | void irq_gc_noop(struct irq_data *d); | |
771 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
772 | void irq_gc_mask_set_bit(struct irq_data *d); | |
773 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
774 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
775 | void irq_gc_ack_set_bit(struct irq_data *d); |
776 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
777 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
778 | void irq_gc_eoi(struct irq_data *d); | |
779 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
780 | ||
781 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
782 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
783 | irq_hw_number_t hw_irq); | |
7d828062 TG |
784 | struct irq_chip_generic * |
785 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
786 | void __iomem *reg_base, irq_flow_handler_t handler); | |
787 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
788 | enum irq_gc_flags flags, unsigned int clr, | |
789 | unsigned int set); | |
790 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
791 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
792 | unsigned int clr, unsigned int set); | |
7d828062 | 793 | |
088f40b7 TG |
794 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
795 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, | |
796 | int num_ct, const char *name, | |
797 | irq_flow_handler_t handler, | |
798 | unsigned int clr, unsigned int set, | |
799 | enum irq_gc_flags flags); | |
800 | ||
801 | ||
7d828062 TG |
802 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
803 | { | |
804 | return container_of(d->chip, struct irq_chip_type, chip); | |
805 | } | |
806 | ||
807 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
808 | ||
809 | #ifdef CONFIG_SMP | |
810 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
811 | { | |
812 | raw_spin_lock(&gc->lock); | |
813 | } | |
814 | ||
815 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
816 | { | |
817 | raw_spin_unlock(&gc->lock); | |
818 | } | |
819 | #else | |
820 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
821 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
822 | #endif | |
823 | ||
06fcb0c6 | 824 | #endif /* _LINUX_IRQ_H */ |