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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
908dcecd | 18 | #include <linux/irqreturn.h> |
dd3a1db9 | 19 | #include <linux/irqnr.h> |
77904fd6 | 20 | #include <linux/errno.h> |
503e5763 | 21 | #include <linux/topology.h> |
3aa551c9 | 22 | #include <linux/wait.h> |
332fd7c4 | 23 | #include <linux/io.h> |
1da177e4 LT |
24 | |
25 | #include <asm/irq.h> | |
26 | #include <asm/ptrace.h> | |
7d12e780 | 27 | #include <asm/irq_regs.h> |
1da177e4 | 28 | |
ab7798ff | 29 | struct seq_file; |
ec53cf23 | 30 | struct module; |
57a58a94 | 31 | struct irq_desc; |
78129576 | 32 | struct irq_data; |
ec701584 | 33 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 34 | struct irq_desc *desc); |
78129576 | 35 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 36 | |
1da177e4 LT |
37 | /* |
38 | * IRQ line status. | |
6e213616 | 39 | * |
5d4d8fc9 TG |
40 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
41 | * | |
42 | * IRQ_TYPE_NONE - default, unspecified type | |
43 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
44 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
45 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
46 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
47 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
48 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
49 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
50 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
51 | * to setup the HW to a sane default (used | |
52 | * by irqdomain map() callbacks to synchronize | |
53 | * the HW state and SW flags for a newly | |
54 | * allocated descriptor). | |
55 | * | |
5d4d8fc9 TG |
56 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
57 | * | |
58 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
59 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
60 | * updated in the code when the above trigger | |
0911f124 | 61 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
62 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
63 | * it from affinity setting | |
64 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
65 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
66 | * request_irq() | |
7f1b1244 | 67 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
68 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
69 | * request/setup_irq() | |
70 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
71 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
72 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
31d9d9b6 | 73 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
74 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
75 | * it from the spurious interrupt detection | |
76 | * mechanism and from core side polling. | |
1da177e4 | 77 | */ |
5d4d8fc9 TG |
78 | enum { |
79 | IRQ_TYPE_NONE = 0x00000000, | |
80 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
81 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
82 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
83 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
84 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
85 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
86 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 87 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
88 | |
89 | IRQ_TYPE_PROBE = 0x00000010, | |
90 | ||
91 | IRQ_LEVEL = (1 << 8), | |
92 | IRQ_PER_CPU = (1 << 9), | |
93 | IRQ_NOPROBE = (1 << 10), | |
94 | IRQ_NOREQUEST = (1 << 11), | |
95 | IRQ_NOAUTOEN = (1 << 12), | |
96 | IRQ_NO_BALANCING = (1 << 13), | |
97 | IRQ_MOVE_PCNTXT = (1 << 14), | |
98 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 99 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 100 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 101 | IRQ_IS_POLLED = (1 << 18), |
5d4d8fc9 | 102 | }; |
950f4427 | 103 | |
44247184 TG |
104 | #define IRQF_MODIFY_MASK \ |
105 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 106 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd TG |
107 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
108 | IRQ_IS_POLLED) | |
44247184 | 109 | |
8f53f924 TG |
110 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
111 | ||
3b8249e7 TG |
112 | /* |
113 | * Return value for chip->irq_set_affinity() | |
114 | * | |
115 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
116 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
117 | */ | |
118 | enum { | |
119 | IRQ_SET_MASK_OK = 0, | |
120 | IRQ_SET_MASK_OK_NOCOPY, | |
121 | }; | |
122 | ||
5b912c10 | 123 | struct msi_desc; |
08a543ad | 124 | struct irq_domain; |
6a6de9ef | 125 | |
ff7dcd44 TG |
126 | /** |
127 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
966dc736 | 128 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 129 | * @irq: interrupt number |
08a543ad | 130 | * @hwirq: hardware interrupt number, local to the interrupt domain |
ff7dcd44 | 131 | * @node: node index useful for balancing |
30398bf6 | 132 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 133 | * Use accessor functions to deal with it |
ff7dcd44 | 134 | * @chip: low level interrupt hardware access |
08a543ad GL |
135 | * @domain: Interrupt translation domain; responsible for mapping |
136 | * between hwirq number and linux irq number. | |
ff7dcd44 TG |
137 | * @handler_data: per-IRQ data for the irq_chip methods |
138 | * @chip_data: platform-specific per-chip private data for the chip | |
139 | * methods, to allow shared chip implementations | |
140 | * @msi_desc: MSI descriptor | |
141 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
142 | * |
143 | * The fields here need to overlay the ones in irq_desc until we | |
144 | * cleaned up the direct references and switched everything over to | |
145 | * irq_data. | |
146 | */ | |
147 | struct irq_data { | |
966dc736 | 148 | u32 mask; |
ff7dcd44 | 149 | unsigned int irq; |
08a543ad | 150 | unsigned long hwirq; |
ff7dcd44 | 151 | unsigned int node; |
91c49917 | 152 | unsigned int state_use_accessors; |
ff7dcd44 | 153 | struct irq_chip *chip; |
08a543ad | 154 | struct irq_domain *domain; |
ff7dcd44 TG |
155 | void *handler_data; |
156 | void *chip_data; | |
157 | struct msi_desc *msi_desc; | |
ff7dcd44 | 158 | cpumask_var_t affinity; |
ff7dcd44 TG |
159 | }; |
160 | ||
f230b6d5 TG |
161 | /* |
162 | * Bit masks for irq_data.state | |
163 | * | |
876dbd4c | 164 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 165 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
166 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
167 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 168 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 169 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
170 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
171 | * from suspend | |
e1ef8241 TG |
172 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
173 | * context | |
32f4125e TG |
174 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
175 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
176 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 177 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
f230b6d5 TG |
178 | */ |
179 | enum { | |
876dbd4c | 180 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
181 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
182 | IRQD_NO_BALANCING = (1 << 10), | |
183 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 184 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 185 | IRQD_LEVEL = (1 << 13), |
7f94226f | 186 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 187 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 188 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
189 | IRQD_IRQ_MASKED = (1 << 17), |
190 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 191 | IRQD_WAKEUP_ARMED = (1 << 19), |
f230b6d5 TG |
192 | }; |
193 | ||
194 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
195 | { | |
196 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
197 | } | |
198 | ||
a005677b TG |
199 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
200 | { | |
201 | return d->state_use_accessors & IRQD_PER_CPU; | |
202 | } | |
203 | ||
204 | static inline bool irqd_can_balance(struct irq_data *d) | |
205 | { | |
206 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
207 | } | |
208 | ||
2bdd1055 TG |
209 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
210 | { | |
211 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
212 | } | |
213 | ||
ee38c04b TG |
214 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
215 | { | |
216 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
217 | } | |
218 | ||
876dbd4c TG |
219 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
220 | { | |
221 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
222 | } | |
223 | ||
224 | /* | |
225 | * Must only be called inside irq_chip.irq_set_type() functions. | |
226 | */ | |
227 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
228 | { | |
229 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
230 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
231 | } | |
232 | ||
233 | static inline bool irqd_is_level_type(struct irq_data *d) | |
234 | { | |
235 | return d->state_use_accessors & IRQD_LEVEL; | |
236 | } | |
237 | ||
7f94226f TG |
238 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
239 | { | |
240 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
241 | } | |
242 | ||
e1ef8241 TG |
243 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
244 | { | |
245 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
246 | } | |
247 | ||
801a0e9a TG |
248 | static inline bool irqd_irq_disabled(struct irq_data *d) |
249 | { | |
250 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
251 | } | |
252 | ||
32f4125e TG |
253 | static inline bool irqd_irq_masked(struct irq_data *d) |
254 | { | |
255 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
256 | } | |
257 | ||
258 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
259 | { | |
260 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
261 | } | |
262 | ||
b76f1674 TG |
263 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
264 | { | |
265 | return d->state_use_accessors & IRQD_WAKEUP_ARMED; | |
266 | } | |
267 | ||
268 | ||
9cff60df TG |
269 | /* |
270 | * Functions for chained handlers which can be enabled/disabled by the | |
271 | * standard disable_irq/enable_irq calls. Must be called with | |
272 | * irq_desc->lock held. | |
273 | */ | |
274 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
275 | { | |
276 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
277 | } | |
278 | ||
279 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
280 | { | |
281 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
282 | } | |
283 | ||
a699e4e4 GL |
284 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
285 | { | |
286 | return d->hwirq; | |
287 | } | |
288 | ||
8fee5c36 | 289 | /** |
6a6de9ef | 290 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
291 | * |
292 | * @name: name for /proc/interrupts | |
f8822657 TG |
293 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
294 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
295 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
296 | * @irq_disable: disable the interrupt | |
297 | * @irq_ack: start of a new interrupt | |
298 | * @irq_mask: mask an interrupt source | |
299 | * @irq_mask_ack: ack and mask an interrupt source | |
300 | * @irq_unmask: unmask an interrupt source | |
301 | * @irq_eoi: end of interrupt | |
302 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
303 | * @irq_retrigger: resend an IRQ to the CPU | |
304 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
305 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
306 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
307 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
308 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
309 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
cfefd21e TG |
310 | * @irq_suspend: function called from core code on suspend once per chip |
311 | * @irq_resume: function called from core code on resume once per chip | |
312 | * @irq_pm_shutdown: function called from core code on shutdown once per chip | |
d0051816 | 313 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 314 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
315 | * @irq_request_resources: optional to request resources before calling |
316 | * any other callback related to this irq | |
317 | * @irq_release_resources: optional to release resources acquired with | |
318 | * irq_request_resources | |
2bff17ad | 319 | * @flags: chip specific flags |
1da177e4 | 320 | */ |
6a6de9ef TG |
321 | struct irq_chip { |
322 | const char *name; | |
f8822657 TG |
323 | unsigned int (*irq_startup)(struct irq_data *data); |
324 | void (*irq_shutdown)(struct irq_data *data); | |
325 | void (*irq_enable)(struct irq_data *data); | |
326 | void (*irq_disable)(struct irq_data *data); | |
327 | ||
328 | void (*irq_ack)(struct irq_data *data); | |
329 | void (*irq_mask)(struct irq_data *data); | |
330 | void (*irq_mask_ack)(struct irq_data *data); | |
331 | void (*irq_unmask)(struct irq_data *data); | |
332 | void (*irq_eoi)(struct irq_data *data); | |
333 | ||
334 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
335 | int (*irq_retrigger)(struct irq_data *data); | |
336 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
337 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
338 | ||
339 | void (*irq_bus_lock)(struct irq_data *data); | |
340 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
341 | ||
0fdb4b25 DD |
342 | void (*irq_cpu_online)(struct irq_data *data); |
343 | void (*irq_cpu_offline)(struct irq_data *data); | |
344 | ||
cfefd21e TG |
345 | void (*irq_suspend)(struct irq_data *data); |
346 | void (*irq_resume)(struct irq_data *data); | |
347 | void (*irq_pm_shutdown)(struct irq_data *data); | |
348 | ||
d0051816 TG |
349 | void (*irq_calc_mask)(struct irq_data *data); |
350 | ||
ab7798ff | 351 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
352 | int (*irq_request_resources)(struct irq_data *data); |
353 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 354 | |
2bff17ad | 355 | unsigned long flags; |
1da177e4 LT |
356 | }; |
357 | ||
d4d5e089 TG |
358 | /* |
359 | * irq_chip specific flags | |
360 | * | |
77694b40 TG |
361 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
362 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 363 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
364 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
365 | * when irq enabled | |
60f96b41 | 366 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 367 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 368 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
369 | */ |
370 | enum { | |
371 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 372 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 373 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 374 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 375 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 376 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 377 | IRQCHIP_EOI_THREADED = (1 << 6), |
d4d5e089 TG |
378 | }; |
379 | ||
e144710b TG |
380 | /* This include will go away once we isolated irq_desc usage to core code */ |
381 | #include <linux/irqdesc.h> | |
0b8f1efa | 382 | |
34ffdb72 IM |
383 | /* |
384 | * Pick up the arch-dependent methods: | |
385 | */ | |
386 | #include <asm/hw_irq.h> | |
1da177e4 | 387 | |
b683de2b TG |
388 | #ifndef NR_IRQS_LEGACY |
389 | # define NR_IRQS_LEGACY 0 | |
390 | #endif | |
391 | ||
1318a481 TG |
392 | #ifndef ARCH_IRQ_INIT_FLAGS |
393 | # define ARCH_IRQ_INIT_FLAGS 0 | |
394 | #endif | |
395 | ||
c1594b77 | 396 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 397 | |
e144710b | 398 | struct irqaction; |
06fcb0c6 | 399 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 400 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
401 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
402 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 403 | |
0fdb4b25 DD |
404 | extern void irq_cpu_online(void); |
405 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
406 | extern int irq_set_affinity_locked(struct irq_data *data, |
407 | const struct cpumask *cpumask, bool force); | |
0fdb4b25 | 408 | |
3a3856d0 | 409 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
410 | void irq_move_irq(struct irq_data *data); |
411 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 412 | #else |
a439520f TG |
413 | static inline void irq_move_irq(struct irq_data *data) { } |
414 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 415 | #endif |
54d5d424 | 416 | |
1da177e4 | 417 | extern int no_irq_affinity; |
1da177e4 | 418 | |
293a7a0a TG |
419 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
420 | int irq_set_parent(int irq, int parent_irq); | |
421 | #else | |
422 | static inline int irq_set_parent(int irq, int parent_irq) | |
423 | { | |
424 | return 0; | |
425 | } | |
426 | #endif | |
427 | ||
6a6de9ef TG |
428 | /* |
429 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 430 | * callable via desc->handle_irq() |
6a6de9ef | 431 | */ |
ec701584 HH |
432 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
433 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
434 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 435 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
436 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
437 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
31d9d9b6 | 438 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 | 439 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
31b47cf7 | 440 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 441 | |
6a6de9ef | 442 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 443 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 444 | irqreturn_t action_ret); |
1da177e4 | 445 | |
a4633adc | 446 | |
6a6de9ef TG |
447 | /* Enable/disable irq debugging output: */ |
448 | extern int noirqdebug_setup(char *str); | |
449 | ||
450 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
451 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
452 | ||
f8b5473f | 453 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 454 | extern struct irq_chip no_irq_chip; |
f8b5473f | 455 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 456 | |
145fc655 | 457 | extern void |
3836ca08 | 458 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
459 | irq_flow_handler_t handle, const char *name); |
460 | ||
3836ca08 TG |
461 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
462 | irq_flow_handler_t handle) | |
463 | { | |
464 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
465 | } | |
466 | ||
31d9d9b6 MZ |
467 | extern int irq_set_percpu_devid(unsigned int irq); |
468 | ||
6a6de9ef | 469 | extern void |
3836ca08 | 470 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 471 | const char *name); |
1da177e4 | 472 | |
6a6de9ef | 473 | static inline void |
3836ca08 | 474 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 475 | { |
3836ca08 | 476 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
477 | } |
478 | ||
479 | /* | |
480 | * Set a highlevel chained flow handler for a given IRQ. | |
481 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 482 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
483 | */ |
484 | static inline void | |
3836ca08 | 485 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 486 | { |
3836ca08 | 487 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
488 | } |
489 | ||
44247184 TG |
490 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
491 | ||
492 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
493 | { | |
494 | irq_modify_status(irq, 0, set); | |
495 | } | |
496 | ||
497 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
498 | { | |
499 | irq_modify_status(irq, clr, 0); | |
500 | } | |
501 | ||
a0cd9ca2 | 502 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
503 | { |
504 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
505 | } | |
506 | ||
a0cd9ca2 | 507 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
508 | { |
509 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
510 | } | |
46f4f8f6 | 511 | |
7f1b1244 PM |
512 | static inline void irq_set_nothread(unsigned int irq) |
513 | { | |
514 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
515 | } | |
516 | ||
517 | static inline void irq_set_thread(unsigned int irq) | |
518 | { | |
519 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
520 | } | |
521 | ||
6f91a52d TG |
522 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
523 | { | |
524 | if (nest) | |
525 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
526 | else | |
527 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
528 | } | |
529 | ||
31d9d9b6 MZ |
530 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
531 | { | |
532 | irq_set_status_flags(irq, | |
533 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
534 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
535 | } | |
536 | ||
3a16d713 | 537 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
538 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
539 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
540 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
541 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
542 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
543 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
544 | struct msi_desc *entry); | |
f303a6dd | 545 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 546 | |
a0cd9ca2 | 547 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
548 | { |
549 | struct irq_data *d = irq_get_irq_data(irq); | |
550 | return d ? d->chip : NULL; | |
551 | } | |
552 | ||
553 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
554 | { | |
555 | return d->chip; | |
556 | } | |
557 | ||
a0cd9ca2 | 558 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
559 | { |
560 | struct irq_data *d = irq_get_irq_data(irq); | |
561 | return d ? d->chip_data : NULL; | |
562 | } | |
563 | ||
564 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
565 | { | |
566 | return d->chip_data; | |
567 | } | |
568 | ||
a0cd9ca2 | 569 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
570 | { |
571 | struct irq_data *d = irq_get_irq_data(irq); | |
572 | return d ? d->handler_data : NULL; | |
573 | } | |
574 | ||
a0cd9ca2 | 575 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
576 | { |
577 | return d->handler_data; | |
578 | } | |
579 | ||
a0cd9ca2 | 580 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
581 | { |
582 | struct irq_data *d = irq_get_irq_data(irq); | |
583 | return d ? d->msi_desc : NULL; | |
584 | } | |
585 | ||
586 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
587 | { | |
588 | return d->msi_desc; | |
589 | } | |
590 | ||
1f6236bf JMC |
591 | static inline u32 irq_get_trigger_type(unsigned int irq) |
592 | { | |
593 | struct irq_data *d = irq_get_irq_data(irq); | |
594 | return d ? irqd_get_trigger_type(d) : 0; | |
595 | } | |
596 | ||
62a08ae2 TG |
597 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
598 | ||
b6873807 SAS |
599 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
600 | struct module *owner); | |
601 | ||
ec53cf23 PG |
602 | /* use macros to avoid needing export.h for THIS_MODULE */ |
603 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
604 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 605 | |
ec53cf23 PG |
606 | #define irq_alloc_desc(node) \ |
607 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 608 | |
ec53cf23 PG |
609 | #define irq_alloc_desc_at(at, node) \ |
610 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 611 | |
ec53cf23 PG |
612 | #define irq_alloc_desc_from(from, node) \ |
613 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 614 | |
51906e77 AG |
615 | #define irq_alloc_descs_from(from, cnt, node) \ |
616 | irq_alloc_descs(-1, from, cnt, node) | |
617 | ||
ec53cf23 | 618 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
619 | static inline void irq_free_desc(unsigned int irq) |
620 | { | |
621 | irq_free_descs(irq, 1); | |
622 | } | |
623 | ||
7b6ef126 TG |
624 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
625 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
626 | static inline unsigned int irq_alloc_hwirq(int node) | |
627 | { | |
628 | return irq_alloc_hwirqs(1, node); | |
629 | } | |
630 | void irq_free_hwirqs(unsigned int from, int cnt); | |
631 | static inline void irq_free_hwirq(unsigned int irq) | |
632 | { | |
633 | return irq_free_hwirqs(irq, 1); | |
634 | } | |
635 | int arch_setup_hwirq(unsigned int irq, int node); | |
636 | void arch_teardown_hwirq(unsigned int irq); | |
637 | #endif | |
638 | ||
c940e01c TG |
639 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
640 | void irq_init_desc(unsigned int irq); | |
641 | #endif | |
642 | ||
7d828062 TG |
643 | /** |
644 | * struct irq_chip_regs - register offsets for struct irq_gci | |
645 | * @enable: Enable register offset to reg_base | |
646 | * @disable: Disable register offset to reg_base | |
647 | * @mask: Mask register offset to reg_base | |
648 | * @ack: Ack register offset to reg_base | |
649 | * @eoi: Eoi register offset to reg_base | |
650 | * @type: Type configuration register offset to reg_base | |
651 | * @polarity: Polarity configuration register offset to reg_base | |
652 | */ | |
653 | struct irq_chip_regs { | |
654 | unsigned long enable; | |
655 | unsigned long disable; | |
656 | unsigned long mask; | |
657 | unsigned long ack; | |
658 | unsigned long eoi; | |
659 | unsigned long type; | |
660 | unsigned long polarity; | |
661 | }; | |
662 | ||
663 | /** | |
664 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
665 | * @chip: The real interrupt chip which provides the callbacks | |
666 | * @regs: Register offsets for this chip | |
667 | * @handler: Flow handler associated with this chip | |
668 | * @type: Chip can handle these flow types | |
899f0e66 GF |
669 | * @mask_cache_priv: Cached mask register private to the chip type |
670 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
671 | * |
672 | * A irq_generic_chip can have several instances of irq_chip_type when | |
673 | * it requires different functions and register offsets for different | |
674 | * flow types. | |
675 | */ | |
676 | struct irq_chip_type { | |
677 | struct irq_chip chip; | |
678 | struct irq_chip_regs regs; | |
679 | irq_flow_handler_t handler; | |
680 | u32 type; | |
899f0e66 GF |
681 | u32 mask_cache_priv; |
682 | u32 *mask_cache; | |
7d828062 TG |
683 | }; |
684 | ||
685 | /** | |
686 | * struct irq_chip_generic - Generic irq chip data structure | |
687 | * @lock: Lock to protect register and cache data access | |
688 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
689 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
690 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
7d828062 TG |
691 | * @irq_base: Interrupt base nr for this chip |
692 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 693 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
694 | * @type_cache: Cached type register |
695 | * @polarity_cache: Cached polarity register | |
696 | * @wake_enabled: Interrupt can wakeup from suspend | |
697 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
698 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
699 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 700 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 701 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 702 | * @domain: irq domain pointer |
cfefd21e | 703 | * @list: List head for keeping track of instances |
7d828062 TG |
704 | * @chip_types: Array of interrupt irq_chip_types |
705 | * | |
706 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
707 | * implementations which can be associated to a particular irq line of | |
708 | * an irq_chip_generic instance. That allows to share and protect | |
709 | * state in an irq_chip_generic instance when we need to implement | |
710 | * different flow mechanisms (level/edge) for it. | |
711 | */ | |
712 | struct irq_chip_generic { | |
713 | raw_spinlock_t lock; | |
714 | void __iomem *reg_base; | |
2b280376 KC |
715 | u32 (*reg_readl)(void __iomem *addr); |
716 | void (*reg_writel)(u32 val, void __iomem *addr); | |
7d828062 TG |
717 | unsigned int irq_base; |
718 | unsigned int irq_cnt; | |
719 | u32 mask_cache; | |
720 | u32 type_cache; | |
721 | u32 polarity_cache; | |
722 | u32 wake_enabled; | |
723 | u32 wake_active; | |
724 | unsigned int num_ct; | |
725 | void *private; | |
088f40b7 | 726 | unsigned long installed; |
e8bd834f | 727 | unsigned long unused; |
088f40b7 | 728 | struct irq_domain *domain; |
cfefd21e | 729 | struct list_head list; |
7d828062 TG |
730 | struct irq_chip_type chip_types[0]; |
731 | }; | |
732 | ||
733 | /** | |
734 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
735 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
736 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
737 | * irq chips which need to call irq_set_wake() on | |
738 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 739 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 740 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
7d828062 TG |
741 | */ |
742 | enum irq_gc_flags { | |
743 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
744 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 745 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 746 | IRQ_GC_NO_MASK = 1 << 3, |
7d828062 TG |
747 | }; |
748 | ||
088f40b7 TG |
749 | /* |
750 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
751 | * @irqs_per_chip: Number of interrupts per chip | |
752 | * @num_chips: Number of chips | |
753 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
754 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
755 | * @gc_flags: Generic chip specific setup flags | |
756 | * @gc: Array of pointers to generic interrupt chips | |
757 | */ | |
758 | struct irq_domain_chip_generic { | |
759 | unsigned int irqs_per_chip; | |
760 | unsigned int num_chips; | |
761 | unsigned int irq_flags_to_clear; | |
762 | unsigned int irq_flags_to_set; | |
763 | enum irq_gc_flags gc_flags; | |
764 | struct irq_chip_generic *gc[0]; | |
765 | }; | |
766 | ||
7d828062 TG |
767 | /* Generic chip callback functions */ |
768 | void irq_gc_noop(struct irq_data *d); | |
769 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
770 | void irq_gc_mask_set_bit(struct irq_data *d); | |
771 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
772 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
773 | void irq_gc_ack_set_bit(struct irq_data *d); |
774 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
775 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
776 | void irq_gc_eoi(struct irq_data *d); | |
777 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
778 | ||
779 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
780 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
781 | irq_hw_number_t hw_irq); | |
7d828062 TG |
782 | struct irq_chip_generic * |
783 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
784 | void __iomem *reg_base, irq_flow_handler_t handler); | |
785 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
786 | enum irq_gc_flags flags, unsigned int clr, | |
787 | unsigned int set); | |
788 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
789 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
790 | unsigned int clr, unsigned int set); | |
7d828062 | 791 | |
088f40b7 TG |
792 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
793 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, | |
794 | int num_ct, const char *name, | |
795 | irq_flow_handler_t handler, | |
796 | unsigned int clr, unsigned int set, | |
797 | enum irq_gc_flags flags); | |
798 | ||
799 | ||
7d828062 TG |
800 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
801 | { | |
802 | return container_of(d->chip, struct irq_chip_type, chip); | |
803 | } | |
804 | ||
805 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
806 | ||
807 | #ifdef CONFIG_SMP | |
808 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
809 | { | |
810 | raw_spin_lock(&gc->lock); | |
811 | } | |
812 | ||
813 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
814 | { | |
815 | raw_spin_unlock(&gc->lock); | |
816 | } | |
817 | #else | |
818 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
819 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
820 | #endif | |
821 | ||
332fd7c4 KC |
822 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
823 | u32 val, int reg_offset) | |
824 | { | |
2b280376 KC |
825 | if (gc->reg_writel) |
826 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
827 | else | |
828 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
829 | } |
830 | ||
831 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
832 | int reg_offset) | |
833 | { | |
2b280376 KC |
834 | if (gc->reg_readl) |
835 | return gc->reg_readl(gc->reg_base + reg_offset); | |
836 | else | |
837 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
838 | } |
839 | ||
06fcb0c6 | 840 | #endif /* _LINUX_IRQ_H */ |