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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
908dcecd | 20 | #include <linux/irqreturn.h> |
1da177e4 LT |
21 | |
22 | #include <asm/irq.h> | |
23 | #include <asm/ptrace.h> | |
24 | ||
25 | /* | |
26 | * IRQ line status. | |
27 | */ | |
28 | #define IRQ_INPROGRESS 1 /* IRQ handler active - do not enter! */ | |
29 | #define IRQ_DISABLED 2 /* IRQ disabled - do not enter! */ | |
30 | #define IRQ_PENDING 4 /* IRQ pending - replay on enable */ | |
31 | #define IRQ_REPLAY 8 /* IRQ has been replayed but not acked yet */ | |
32 | #define IRQ_AUTODETECT 16 /* IRQ is being autodetected */ | |
33 | #define IRQ_WAITING 32 /* IRQ not yet seen - for autodetection */ | |
34 | #define IRQ_LEVEL 64 /* IRQ level triggered */ | |
35 | #define IRQ_MASKED 128 /* IRQ masked - shouldn't be seen again */ | |
0d7012a9 | 36 | #ifdef CONFIG_IRQ_PER_CPU |
f26fdd59 KW |
37 | # define IRQ_PER_CPU 256 /* IRQ is per CPU */ |
38 | # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) | |
39 | #else | |
40 | # define CHECK_IRQ_PER_CPU(var) 0 | |
41 | #endif | |
1da177e4 | 42 | |
3418d724 | 43 | #define IRQ_NOPROBE 512 /* IRQ is not valid for probing */ |
8fee5c36 IM |
44 | /** |
45 | * struct hw_interrupt_type - hardware interrupt type descriptor | |
46 | * | |
47 | * @name: name for /proc/interrupts | |
48 | * @startup: start up the interrupt (defaults to ->enable if NULL) | |
49 | * @shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
50 | * @enable: enable the interrupt (defaults to chip->unmask if NULL) | |
51 | * @disable: disable the interrupt (defaults to chip->mask if NULL) | |
52 | * @handle_irq: irq flow handler called from the arch IRQ glue code | |
53 | * @ack: start of a new interrupt | |
54 | * @mask: mask an interrupt source | |
55 | * @mask_ack: ack and mask an interrupt source | |
56 | * @unmask: unmask an interrupt source | |
57 | * @hold: same interrupt while the handler is running | |
58 | * @end: end of interrupt | |
59 | * @set_affinity: set the CPU affinity on SMP machines | |
60 | * @retrigger: resend an IRQ to the CPU | |
61 | * @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
62 | * @set_wake: enable/disable power-management wake-on of an IRQ | |
63 | * | |
64 | * @release: release function solely used by UML | |
1da177e4 LT |
65 | */ |
66 | struct hw_interrupt_type { | |
71d218b7 IM |
67 | const char *typename; |
68 | unsigned int (*startup)(unsigned int irq); | |
69 | void (*shutdown)(unsigned int irq); | |
70 | void (*enable)(unsigned int irq); | |
71 | void (*disable)(unsigned int irq); | |
72 | void (*ack)(unsigned int irq); | |
73 | void (*end)(unsigned int irq); | |
74 | void (*set_affinity)(unsigned int irq, cpumask_t dest); | |
c0ad90a3 IM |
75 | int (*retrigger)(unsigned int irq); |
76 | ||
b77d6adc PBG |
77 | /* Currently used only by UML, might disappear one day.*/ |
78 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 79 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 80 | #endif |
1da177e4 LT |
81 | }; |
82 | ||
83 | typedef struct hw_interrupt_type hw_irq_controller; | |
84 | ||
4a733ee1 IM |
85 | struct proc_dir_entry; |
86 | ||
8fee5c36 IM |
87 | /** |
88 | * struct irq_desc - interrupt descriptor | |
89 | * | |
90 | * @handler: interrupt type dependent handler functions | |
91 | * @handler_data: data for the type handlers | |
92 | * @action: the irq action chain | |
93 | * @status: status information | |
94 | * @depth: disable-depth, for nested irq_disable() calls | |
95 | * @irq_count: stats field to detect stalled irqs | |
96 | * @irqs_unhandled: stats field for spurious unhandled interrupts | |
97 | * @lock: locking for SMP | |
98 | * @affinity: IRQ affinity on SMP | |
99 | * @pending_mask: pending rebalanced interrupts | |
100 | * @move_irq: need to re-target IRQ destination | |
101 | * @dir: /proc/irq/ procfs entry | |
102 | * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP | |
1da177e4 LT |
103 | * |
104 | * Pad this out to 32 bytes for cache and indexing reasons. | |
105 | */ | |
34ffdb72 | 106 | struct irq_desc { |
71d218b7 IM |
107 | hw_irq_controller *chip; |
108 | void *chip_data; | |
109 | struct irqaction *action; /* IRQ action list */ | |
110 | unsigned int status; /* IRQ status */ | |
111 | unsigned int depth; /* nested irq disables */ | |
112 | unsigned int irq_count; /* For detecting broken IRQs */ | |
113 | unsigned int irqs_unhandled; | |
114 | spinlock_t lock; | |
a53da52f | 115 | #ifdef CONFIG_SMP |
71d218b7 | 116 | cpumask_t affinity; |
a53da52f | 117 | #endif |
06fcb0c6 | 118 | #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) |
cd916d31 | 119 | cpumask_t pending_mask; |
71d218b7 | 120 | unsigned int move_irq; /* need to re-target IRQ dest */ |
54d5d424 | 121 | #endif |
4a733ee1 IM |
122 | #ifdef CONFIG_PROC_FS |
123 | struct proc_dir_entry *dir; | |
124 | #endif | |
34ffdb72 | 125 | } ____cacheline_aligned; |
1da177e4 | 126 | |
34ffdb72 | 127 | extern struct irq_desc irq_desc[NR_IRQS]; |
1da177e4 | 128 | |
34ffdb72 IM |
129 | /* |
130 | * Migration helpers for obsolete names, they will go away: | |
131 | */ | |
132 | typedef struct irq_desc irq_desc_t; | |
133 | ||
134 | /* | |
135 | * Pick up the arch-dependent methods: | |
136 | */ | |
137 | #include <asm/hw_irq.h> | |
1da177e4 | 138 | |
06fcb0c6 | 139 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
1da177e4 LT |
140 | |
141 | #ifdef CONFIG_GENERIC_HARDIRQS | |
06fcb0c6 | 142 | |
54d5d424 AR |
143 | #ifdef CONFIG_SMP |
144 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
145 | { | |
a53da52f | 146 | irq_desc[irq].affinity = mask; |
54d5d424 AR |
147 | } |
148 | #else | |
149 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
150 | { | |
151 | } | |
152 | #endif | |
153 | ||
154 | #ifdef CONFIG_SMP | |
155 | ||
06fcb0c6 | 156 | #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) |
54d5d424 | 157 | |
c777ac55 AM |
158 | void set_pending_irq(unsigned int irq, cpumask_t mask); |
159 | void move_native_irq(int irq); | |
54d5d424 AR |
160 | |
161 | #ifdef CONFIG_PCI_MSI | |
162 | /* | |
163 | * Wonder why these are dummies? | |
164 | * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq() | |
165 | * counter part after translating the vector to irq info. We need to perform | |
166 | * this operation on the real irq, when we dont use vector, i.e when | |
167 | * pci_use_vector() is false. | |
168 | */ | |
169 | static inline void move_irq(int irq) | |
170 | { | |
171 | } | |
172 | ||
173 | static inline void set_irq_info(int irq, cpumask_t mask) | |
174 | { | |
175 | } | |
176 | ||
06fcb0c6 | 177 | #else /* CONFIG_PCI_MSI */ |
54d5d424 AR |
178 | |
179 | static inline void move_irq(int irq) | |
180 | { | |
181 | move_native_irq(irq); | |
182 | } | |
183 | ||
184 | static inline void set_irq_info(int irq, cpumask_t mask) | |
185 | { | |
186 | set_native_irq_info(irq, mask); | |
187 | } | |
54d5d424 | 188 | |
06fcb0c6 IM |
189 | #endif /* CONFIG_PCI_MSI */ |
190 | ||
191 | #else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */ | |
192 | ||
193 | static inline void move_irq(int irq) | |
194 | { | |
195 | } | |
196 | ||
197 | static inline void move_native_irq(int irq) | |
198 | { | |
199 | } | |
200 | ||
201 | static inline void set_pending_irq(unsigned int irq, cpumask_t mask) | |
202 | { | |
203 | } | |
54d5d424 | 204 | |
54d5d424 AR |
205 | static inline void set_irq_info(int irq, cpumask_t mask) |
206 | { | |
207 | set_native_irq_info(irq, mask); | |
208 | } | |
209 | ||
06fcb0c6 | 210 | #endif /* CONFIG_GENERIC_PENDING_IRQ */ |
54d5d424 | 211 | |
06fcb0c6 | 212 | #else /* CONFIG_SMP */ |
54d5d424 AR |
213 | |
214 | #define move_irq(x) | |
215 | #define move_native_irq(x) | |
216 | ||
06fcb0c6 | 217 | #endif /* CONFIG_SMP */ |
54d5d424 | 218 | |
1b61b910 ZY |
219 | #ifdef CONFIG_IRQBALANCE |
220 | extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask); | |
221 | #else | |
222 | static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) | |
223 | { | |
224 | } | |
225 | #endif | |
226 | ||
71d218b7 IM |
227 | #ifdef CONFIG_AUTO_IRQ_AFFINITY |
228 | extern int select_smp_affinity(unsigned int irq); | |
229 | #else | |
230 | static inline int select_smp_affinity(unsigned int irq) | |
231 | { | |
232 | return 1; | |
233 | } | |
234 | #endif | |
235 | ||
1da177e4 LT |
236 | extern int no_irq_affinity; |
237 | extern int noirqdebug_setup(char *str); | |
238 | ||
2e60bbb6 IM |
239 | extern irqreturn_t handle_IRQ_event(unsigned int irq, struct pt_regs *regs, |
240 | struct irqaction *action); | |
241 | /* | |
242 | * Explicit fastcall, because i386 4KSTACKS calls it from assembly: | |
243 | */ | |
1da177e4 | 244 | extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs); |
2e60bbb6 | 245 | |
34ffdb72 | 246 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
2e60bbb6 | 247 | int action_ret, struct pt_regs *regs); |
1da177e4 LT |
248 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); |
249 | ||
a4633adc TG |
250 | /* Resending of interrupts :*/ |
251 | void check_irq_resend(struct irq_desc *desc, unsigned int irq); | |
252 | ||
1da177e4 | 253 | extern void init_irq_proc(void); |
eee45269 | 254 | |
06fcb0c6 | 255 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 LT |
256 | |
257 | extern hw_irq_controller no_irq_type; /* needed in every arch ? */ | |
258 | ||
06fcb0c6 | 259 | #endif /* !CONFIG_S390 */ |
1da177e4 | 260 | |
06fcb0c6 | 261 | #endif /* _LINUX_IRQ_H */ |