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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
75ffc007 | 18 | #include <linux/irqhandler.h> |
908dcecd | 19 | #include <linux/irqreturn.h> |
dd3a1db9 | 20 | #include <linux/irqnr.h> |
77904fd6 | 21 | #include <linux/errno.h> |
503e5763 | 22 | #include <linux/topology.h> |
3aa551c9 | 23 | #include <linux/wait.h> |
332fd7c4 | 24 | #include <linux/io.h> |
1da177e4 LT |
25 | |
26 | #include <asm/irq.h> | |
27 | #include <asm/ptrace.h> | |
7d12e780 | 28 | #include <asm/irq_regs.h> |
1da177e4 | 29 | |
ab7798ff | 30 | struct seq_file; |
ec53cf23 | 31 | struct module; |
515085ef | 32 | struct msi_msg; |
1b7047ed | 33 | enum irqchip_irq_state; |
57a58a94 | 34 | |
1da177e4 LT |
35 | /* |
36 | * IRQ line status. | |
6e213616 | 37 | * |
5d4d8fc9 TG |
38 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
39 | * | |
40 | * IRQ_TYPE_NONE - default, unspecified type | |
41 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
42 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
43 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
44 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
45 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
46 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
47 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
48 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
49 | * to setup the HW to a sane default (used | |
50 | * by irqdomain map() callbacks to synchronize | |
51 | * the HW state and SW flags for a newly | |
52 | * allocated descriptor). | |
53 | * | |
5d4d8fc9 TG |
54 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
55 | * | |
56 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
57 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
58 | * updated in the code when the above trigger | |
0911f124 | 59 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
60 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
61 | * it from affinity setting | |
62 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
63 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
64 | * request_irq() | |
7f1b1244 | 65 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
66 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
67 | * request/setup_irq() | |
68 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
69 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
70 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
31d9d9b6 | 71 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
72 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
73 | * it from the spurious interrupt detection | |
74 | * mechanism and from core side polling. | |
1da177e4 | 75 | */ |
5d4d8fc9 TG |
76 | enum { |
77 | IRQ_TYPE_NONE = 0x00000000, | |
78 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
79 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
80 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
81 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
82 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
83 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
84 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 85 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
86 | |
87 | IRQ_TYPE_PROBE = 0x00000010, | |
88 | ||
89 | IRQ_LEVEL = (1 << 8), | |
90 | IRQ_PER_CPU = (1 << 9), | |
91 | IRQ_NOPROBE = (1 << 10), | |
92 | IRQ_NOREQUEST = (1 << 11), | |
93 | IRQ_NOAUTOEN = (1 << 12), | |
94 | IRQ_NO_BALANCING = (1 << 13), | |
95 | IRQ_MOVE_PCNTXT = (1 << 14), | |
96 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 97 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 98 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 99 | IRQ_IS_POLLED = (1 << 18), |
5d4d8fc9 | 100 | }; |
950f4427 | 101 | |
44247184 TG |
102 | #define IRQF_MODIFY_MASK \ |
103 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 104 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd TG |
105 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
106 | IRQ_IS_POLLED) | |
44247184 | 107 | |
8f53f924 TG |
108 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
109 | ||
3b8249e7 TG |
110 | /* |
111 | * Return value for chip->irq_set_affinity() | |
112 | * | |
113 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
114 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
2cb62547 JL |
115 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
116 | * support stacked irqchips, which indicates skipping | |
117 | * all descendent irqchips. | |
3b8249e7 TG |
118 | */ |
119 | enum { | |
120 | IRQ_SET_MASK_OK = 0, | |
121 | IRQ_SET_MASK_OK_NOCOPY, | |
2cb62547 | 122 | IRQ_SET_MASK_OK_DONE, |
3b8249e7 TG |
123 | }; |
124 | ||
5b912c10 | 125 | struct msi_desc; |
08a543ad | 126 | struct irq_domain; |
6a6de9ef | 127 | |
ff7dcd44 | 128 | /** |
0d0b4c86 JL |
129 | * struct irq_common_data - per irq data shared by all irqchips |
130 | * @state_use_accessors: status information for irq chip functions. | |
131 | * Use accessor functions to deal with it | |
132 | */ | |
133 | struct irq_common_data { | |
134 | unsigned int state_use_accessors; | |
135 | }; | |
136 | ||
137 | /** | |
138 | * struct irq_data - per irq chip data passed down to chip functions | |
966dc736 | 139 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 140 | * @irq: interrupt number |
08a543ad | 141 | * @hwirq: hardware interrupt number, local to the interrupt domain |
ff7dcd44 | 142 | * @node: node index useful for balancing |
0d0b4c86 | 143 | * @common: point to data shared by all irqchips |
ff7dcd44 | 144 | * @chip: low level interrupt hardware access |
08a543ad GL |
145 | * @domain: Interrupt translation domain; responsible for mapping |
146 | * between hwirq number and linux irq number. | |
f8264e34 JL |
147 | * @parent_data: pointer to parent struct irq_data to support hierarchy |
148 | * irq_domain | |
ff7dcd44 TG |
149 | * @handler_data: per-IRQ data for the irq_chip methods |
150 | * @chip_data: platform-specific per-chip private data for the chip | |
151 | * methods, to allow shared chip implementations | |
152 | * @msi_desc: MSI descriptor | |
153 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
154 | */ |
155 | struct irq_data { | |
966dc736 | 156 | u32 mask; |
ff7dcd44 | 157 | unsigned int irq; |
08a543ad | 158 | unsigned long hwirq; |
ff7dcd44 | 159 | unsigned int node; |
0d0b4c86 | 160 | struct irq_common_data *common; |
ff7dcd44 | 161 | struct irq_chip *chip; |
08a543ad | 162 | struct irq_domain *domain; |
f8264e34 JL |
163 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
164 | struct irq_data *parent_data; | |
165 | #endif | |
ff7dcd44 TG |
166 | void *handler_data; |
167 | void *chip_data; | |
168 | struct msi_desc *msi_desc; | |
ff7dcd44 | 169 | cpumask_var_t affinity; |
ff7dcd44 TG |
170 | }; |
171 | ||
f230b6d5 | 172 | /* |
0d0b4c86 | 173 | * Bit masks for irq_common_data.state_use_accessors |
f230b6d5 | 174 | * |
876dbd4c | 175 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 176 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
177 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
178 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 179 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 180 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
181 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
182 | * from suspend | |
e1ef8241 TG |
183 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
184 | * context | |
32f4125e TG |
185 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
186 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
187 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 188 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
fc569712 | 189 | * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU |
f230b6d5 TG |
190 | */ |
191 | enum { | |
876dbd4c | 192 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
193 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
194 | IRQD_NO_BALANCING = (1 << 10), | |
195 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 196 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 197 | IRQD_LEVEL = (1 << 13), |
7f94226f | 198 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 199 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 200 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
201 | IRQD_IRQ_MASKED = (1 << 17), |
202 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 203 | IRQD_WAKEUP_ARMED = (1 << 19), |
fc569712 | 204 | IRQD_FORWARDED_TO_VCPU = (1 << 20), |
f230b6d5 TG |
205 | }; |
206 | ||
0d0b4c86 JL |
207 | #define __irqd_to_state(d) ((d)->common->state_use_accessors) |
208 | ||
f230b6d5 TG |
209 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
210 | { | |
0d0b4c86 | 211 | return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; |
f230b6d5 TG |
212 | } |
213 | ||
a005677b TG |
214 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
215 | { | |
0d0b4c86 | 216 | return __irqd_to_state(d) & IRQD_PER_CPU; |
a005677b TG |
217 | } |
218 | ||
219 | static inline bool irqd_can_balance(struct irq_data *d) | |
220 | { | |
0d0b4c86 | 221 | return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
a005677b TG |
222 | } |
223 | ||
2bdd1055 TG |
224 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
225 | { | |
0d0b4c86 | 226 | return __irqd_to_state(d) & IRQD_AFFINITY_SET; |
2bdd1055 TG |
227 | } |
228 | ||
ee38c04b TG |
229 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
230 | { | |
0d0b4c86 | 231 | __irqd_to_state(d) |= IRQD_AFFINITY_SET; |
ee38c04b TG |
232 | } |
233 | ||
876dbd4c TG |
234 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
235 | { | |
0d0b4c86 | 236 | return __irqd_to_state(d) & IRQD_TRIGGER_MASK; |
876dbd4c TG |
237 | } |
238 | ||
239 | /* | |
240 | * Must only be called inside irq_chip.irq_set_type() functions. | |
241 | */ | |
242 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
243 | { | |
0d0b4c86 JL |
244 | __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; |
245 | __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; | |
876dbd4c TG |
246 | } |
247 | ||
248 | static inline bool irqd_is_level_type(struct irq_data *d) | |
249 | { | |
0d0b4c86 | 250 | return __irqd_to_state(d) & IRQD_LEVEL; |
876dbd4c TG |
251 | } |
252 | ||
7f94226f TG |
253 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
254 | { | |
0d0b4c86 | 255 | return __irqd_to_state(d) & IRQD_WAKEUP_STATE; |
7f94226f TG |
256 | } |
257 | ||
e1ef8241 TG |
258 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
259 | { | |
0d0b4c86 | 260 | return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; |
e1ef8241 TG |
261 | } |
262 | ||
801a0e9a TG |
263 | static inline bool irqd_irq_disabled(struct irq_data *d) |
264 | { | |
0d0b4c86 | 265 | return __irqd_to_state(d) & IRQD_IRQ_DISABLED; |
801a0e9a TG |
266 | } |
267 | ||
32f4125e TG |
268 | static inline bool irqd_irq_masked(struct irq_data *d) |
269 | { | |
0d0b4c86 | 270 | return __irqd_to_state(d) & IRQD_IRQ_MASKED; |
32f4125e TG |
271 | } |
272 | ||
273 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
274 | { | |
0d0b4c86 | 275 | return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; |
32f4125e TG |
276 | } |
277 | ||
b76f1674 TG |
278 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
279 | { | |
0d0b4c86 | 280 | return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; |
b76f1674 TG |
281 | } |
282 | ||
fc569712 TG |
283 | static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) |
284 | { | |
285 | return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; | |
286 | } | |
287 | ||
288 | static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) | |
289 | { | |
290 | __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; | |
291 | } | |
292 | ||
293 | static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) | |
294 | { | |
295 | __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; | |
296 | } | |
b76f1674 | 297 | |
9cff60df TG |
298 | /* |
299 | * Functions for chained handlers which can be enabled/disabled by the | |
300 | * standard disable_irq/enable_irq calls. Must be called with | |
301 | * irq_desc->lock held. | |
302 | */ | |
303 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
304 | { | |
0d0b4c86 | 305 | __irqd_to_state(d) |= IRQD_IRQ_INPROGRESS; |
9cff60df TG |
306 | } |
307 | ||
308 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
309 | { | |
0d0b4c86 | 310 | __irqd_to_state(d) &= ~IRQD_IRQ_INPROGRESS; |
9cff60df TG |
311 | } |
312 | ||
a699e4e4 GL |
313 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
314 | { | |
315 | return d->hwirq; | |
316 | } | |
317 | ||
8fee5c36 | 318 | /** |
6a6de9ef | 319 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
320 | * |
321 | * @name: name for /proc/interrupts | |
f8822657 TG |
322 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
323 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
324 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
325 | * @irq_disable: disable the interrupt | |
326 | * @irq_ack: start of a new interrupt | |
327 | * @irq_mask: mask an interrupt source | |
328 | * @irq_mask_ack: ack and mask an interrupt source | |
329 | * @irq_unmask: unmask an interrupt source | |
330 | * @irq_eoi: end of interrupt | |
331 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
332 | * @irq_retrigger: resend an IRQ to the CPU | |
333 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
334 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
335 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
336 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
337 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
338 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
be9b22b6 BN |
339 | * @irq_suspend: function called from core code on suspend once per |
340 | * chip, when one or more interrupts are installed | |
341 | * @irq_resume: function called from core code on resume once per chip, | |
342 | * when one ore more interrupts are installed | |
cfefd21e | 343 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
d0051816 | 344 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 345 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
346 | * @irq_request_resources: optional to request resources before calling |
347 | * any other callback related to this irq | |
348 | * @irq_release_resources: optional to release resources acquired with | |
349 | * irq_request_resources | |
515085ef | 350 | * @irq_compose_msi_msg: optional to compose message content for MSI |
9dde55b7 | 351 | * @irq_write_msi_msg: optional to write message content for MSI |
1b7047ed MZ |
352 | * @irq_get_irqchip_state: return the internal state of an interrupt |
353 | * @irq_set_irqchip_state: set the internal state of a interrupt | |
0a4377de | 354 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
2bff17ad | 355 | * @flags: chip specific flags |
1da177e4 | 356 | */ |
6a6de9ef TG |
357 | struct irq_chip { |
358 | const char *name; | |
f8822657 TG |
359 | unsigned int (*irq_startup)(struct irq_data *data); |
360 | void (*irq_shutdown)(struct irq_data *data); | |
361 | void (*irq_enable)(struct irq_data *data); | |
362 | void (*irq_disable)(struct irq_data *data); | |
363 | ||
364 | void (*irq_ack)(struct irq_data *data); | |
365 | void (*irq_mask)(struct irq_data *data); | |
366 | void (*irq_mask_ack)(struct irq_data *data); | |
367 | void (*irq_unmask)(struct irq_data *data); | |
368 | void (*irq_eoi)(struct irq_data *data); | |
369 | ||
370 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
371 | int (*irq_retrigger)(struct irq_data *data); | |
372 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
373 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
374 | ||
375 | void (*irq_bus_lock)(struct irq_data *data); | |
376 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
377 | ||
0fdb4b25 DD |
378 | void (*irq_cpu_online)(struct irq_data *data); |
379 | void (*irq_cpu_offline)(struct irq_data *data); | |
380 | ||
cfefd21e TG |
381 | void (*irq_suspend)(struct irq_data *data); |
382 | void (*irq_resume)(struct irq_data *data); | |
383 | void (*irq_pm_shutdown)(struct irq_data *data); | |
384 | ||
d0051816 TG |
385 | void (*irq_calc_mask)(struct irq_data *data); |
386 | ||
ab7798ff | 387 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
388 | int (*irq_request_resources)(struct irq_data *data); |
389 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 390 | |
515085ef | 391 | void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
9dde55b7 | 392 | void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
515085ef | 393 | |
1b7047ed MZ |
394 | int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); |
395 | int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); | |
396 | ||
0a4377de JL |
397 | int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); |
398 | ||
2bff17ad | 399 | unsigned long flags; |
1da177e4 LT |
400 | }; |
401 | ||
d4d5e089 TG |
402 | /* |
403 | * irq_chip specific flags | |
404 | * | |
77694b40 TG |
405 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
406 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 407 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
408 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
409 | * when irq enabled | |
60f96b41 | 410 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 411 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 412 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
413 | */ |
414 | enum { | |
415 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 416 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 417 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 418 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 419 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 420 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 421 | IRQCHIP_EOI_THREADED = (1 << 6), |
d4d5e089 TG |
422 | }; |
423 | ||
e144710b | 424 | #include <linux/irqdesc.h> |
0b8f1efa | 425 | |
34ffdb72 IM |
426 | /* |
427 | * Pick up the arch-dependent methods: | |
428 | */ | |
429 | #include <asm/hw_irq.h> | |
1da177e4 | 430 | |
b683de2b TG |
431 | #ifndef NR_IRQS_LEGACY |
432 | # define NR_IRQS_LEGACY 0 | |
433 | #endif | |
434 | ||
1318a481 TG |
435 | #ifndef ARCH_IRQ_INIT_FLAGS |
436 | # define ARCH_IRQ_INIT_FLAGS 0 | |
437 | #endif | |
438 | ||
c1594b77 | 439 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 440 | |
e144710b | 441 | struct irqaction; |
06fcb0c6 | 442 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 443 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
444 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
445 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 446 | |
0fdb4b25 DD |
447 | extern void irq_cpu_online(void); |
448 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
449 | extern int irq_set_affinity_locked(struct irq_data *data, |
450 | const struct cpumask *cpumask, bool force); | |
0a4377de | 451 | extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); |
0fdb4b25 | 452 | |
3a3856d0 | 453 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
454 | void irq_move_irq(struct irq_data *data); |
455 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 456 | #else |
a439520f TG |
457 | static inline void irq_move_irq(struct irq_data *data) { } |
458 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 459 | #endif |
54d5d424 | 460 | |
1da177e4 | 461 | extern int no_irq_affinity; |
1da177e4 | 462 | |
293a7a0a TG |
463 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
464 | int irq_set_parent(int irq, int parent_irq); | |
465 | #else | |
466 | static inline int irq_set_parent(int irq, int parent_irq) | |
467 | { | |
468 | return 0; | |
469 | } | |
470 | #endif | |
471 | ||
6a6de9ef TG |
472 | /* |
473 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 474 | * callable via desc->handle_irq() |
6a6de9ef | 475 | */ |
ec701584 HH |
476 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
477 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
478 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 479 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
480 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
481 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
31d9d9b6 | 482 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 | 483 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
31b47cf7 | 484 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 485 | |
515085ef | 486 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
85f08c17 | 487 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
3cfeffc2 SA |
488 | extern void irq_chip_enable_parent(struct irq_data *data); |
489 | extern void irq_chip_disable_parent(struct irq_data *data); | |
85f08c17 JL |
490 | extern void irq_chip_ack_parent(struct irq_data *data); |
491 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); | |
56e8abab YC |
492 | extern void irq_chip_mask_parent(struct irq_data *data); |
493 | extern void irq_chip_unmask_parent(struct irq_data *data); | |
494 | extern void irq_chip_eoi_parent(struct irq_data *data); | |
495 | extern int irq_chip_set_affinity_parent(struct irq_data *data, | |
496 | const struct cpumask *dest, | |
497 | bool force); | |
08b55e2a | 498 | extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); |
0a4377de JL |
499 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
500 | void *vcpu_info); | |
b7560de1 | 501 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
85f08c17 JL |
502 | #endif |
503 | ||
6a6de9ef | 504 | /* Handling of unhandled and spurious interrupts: */ |
0dcdbc97 | 505 | extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); |
1da177e4 | 506 | |
a4633adc | 507 | |
6a6de9ef TG |
508 | /* Enable/disable irq debugging output: */ |
509 | extern int noirqdebug_setup(char *str); | |
510 | ||
511 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
512 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
513 | ||
f8b5473f | 514 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 515 | extern struct irq_chip no_irq_chip; |
f8b5473f | 516 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 517 | |
145fc655 | 518 | extern void |
3836ca08 | 519 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
520 | irq_flow_handler_t handle, const char *name); |
521 | ||
3836ca08 TG |
522 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
523 | irq_flow_handler_t handle) | |
524 | { | |
525 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
526 | } | |
527 | ||
31d9d9b6 MZ |
528 | extern int irq_set_percpu_devid(unsigned int irq); |
529 | ||
6a6de9ef | 530 | extern void |
3836ca08 | 531 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 532 | const char *name); |
1da177e4 | 533 | |
6a6de9ef | 534 | static inline void |
3836ca08 | 535 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 536 | { |
3836ca08 | 537 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
538 | } |
539 | ||
540 | /* | |
541 | * Set a highlevel chained flow handler for a given IRQ. | |
542 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 543 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
544 | */ |
545 | static inline void | |
3836ca08 | 546 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 547 | { |
3836ca08 | 548 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
549 | } |
550 | ||
3b0f95be RK |
551 | /* |
552 | * Set a highlevel chained flow handler and its data for a given IRQ. | |
553 | * (a chained handler is automatically enabled and set to | |
554 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) | |
555 | */ | |
556 | void | |
557 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
558 | void *data); | |
559 | ||
44247184 TG |
560 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
561 | ||
562 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
563 | { | |
564 | irq_modify_status(irq, 0, set); | |
565 | } | |
566 | ||
567 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
568 | { | |
569 | irq_modify_status(irq, clr, 0); | |
570 | } | |
571 | ||
a0cd9ca2 | 572 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
573 | { |
574 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
575 | } | |
576 | ||
a0cd9ca2 | 577 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
578 | { |
579 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
580 | } | |
46f4f8f6 | 581 | |
7f1b1244 PM |
582 | static inline void irq_set_nothread(unsigned int irq) |
583 | { | |
584 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
585 | } | |
586 | ||
587 | static inline void irq_set_thread(unsigned int irq) | |
588 | { | |
589 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
590 | } | |
591 | ||
6f91a52d TG |
592 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
593 | { | |
594 | if (nest) | |
595 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
596 | else | |
597 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
598 | } | |
599 | ||
31d9d9b6 MZ |
600 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
601 | { | |
602 | irq_set_status_flags(irq, | |
603 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
604 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
605 | } | |
606 | ||
3a16d713 | 607 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
608 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
609 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
610 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
611 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
612 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
613 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
614 | struct msi_desc *entry); | |
f303a6dd | 615 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 616 | |
a0cd9ca2 | 617 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
618 | { |
619 | struct irq_data *d = irq_get_irq_data(irq); | |
620 | return d ? d->chip : NULL; | |
621 | } | |
622 | ||
623 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
624 | { | |
625 | return d->chip; | |
626 | } | |
627 | ||
a0cd9ca2 | 628 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
629 | { |
630 | struct irq_data *d = irq_get_irq_data(irq); | |
631 | return d ? d->chip_data : NULL; | |
632 | } | |
633 | ||
634 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
635 | { | |
636 | return d->chip_data; | |
637 | } | |
638 | ||
a0cd9ca2 | 639 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
640 | { |
641 | struct irq_data *d = irq_get_irq_data(irq); | |
642 | return d ? d->handler_data : NULL; | |
643 | } | |
644 | ||
a0cd9ca2 | 645 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
646 | { |
647 | return d->handler_data; | |
648 | } | |
649 | ||
a0cd9ca2 | 650 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
651 | { |
652 | struct irq_data *d = irq_get_irq_data(irq); | |
653 | return d ? d->msi_desc : NULL; | |
654 | } | |
655 | ||
c391f262 | 656 | static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) |
f303a6dd TG |
657 | { |
658 | return d->msi_desc; | |
659 | } | |
660 | ||
1f6236bf JMC |
661 | static inline u32 irq_get_trigger_type(unsigned int irq) |
662 | { | |
663 | struct irq_data *d = irq_get_irq_data(irq); | |
664 | return d ? irqd_get_trigger_type(d) : 0; | |
665 | } | |
666 | ||
6783011b JL |
667 | static inline int irq_data_get_node(struct irq_data *d) |
668 | { | |
669 | return d->node; | |
670 | } | |
671 | ||
c64301a2 JL |
672 | static inline struct cpumask *irq_get_affinity_mask(int irq) |
673 | { | |
674 | struct irq_data *d = irq_get_irq_data(irq); | |
675 | ||
676 | return d ? d->affinity : NULL; | |
677 | } | |
678 | ||
679 | static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) | |
680 | { | |
681 | return d->affinity; | |
682 | } | |
683 | ||
62a08ae2 TG |
684 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
685 | ||
b6873807 SAS |
686 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
687 | struct module *owner); | |
688 | ||
ec53cf23 PG |
689 | /* use macros to avoid needing export.h for THIS_MODULE */ |
690 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
691 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 692 | |
ec53cf23 PG |
693 | #define irq_alloc_desc(node) \ |
694 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 695 | |
ec53cf23 PG |
696 | #define irq_alloc_desc_at(at, node) \ |
697 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 698 | |
ec53cf23 PG |
699 | #define irq_alloc_desc_from(from, node) \ |
700 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 701 | |
51906e77 AG |
702 | #define irq_alloc_descs_from(from, cnt, node) \ |
703 | irq_alloc_descs(-1, from, cnt, node) | |
704 | ||
ec53cf23 | 705 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
706 | static inline void irq_free_desc(unsigned int irq) |
707 | { | |
708 | irq_free_descs(irq, 1); | |
709 | } | |
710 | ||
7b6ef126 TG |
711 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
712 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
713 | static inline unsigned int irq_alloc_hwirq(int node) | |
714 | { | |
715 | return irq_alloc_hwirqs(1, node); | |
716 | } | |
717 | void irq_free_hwirqs(unsigned int from, int cnt); | |
718 | static inline void irq_free_hwirq(unsigned int irq) | |
719 | { | |
720 | return irq_free_hwirqs(irq, 1); | |
721 | } | |
722 | int arch_setup_hwirq(unsigned int irq, int node); | |
723 | void arch_teardown_hwirq(unsigned int irq); | |
724 | #endif | |
725 | ||
c940e01c TG |
726 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
727 | void irq_init_desc(unsigned int irq); | |
728 | #endif | |
729 | ||
7d828062 TG |
730 | /** |
731 | * struct irq_chip_regs - register offsets for struct irq_gci | |
732 | * @enable: Enable register offset to reg_base | |
733 | * @disable: Disable register offset to reg_base | |
734 | * @mask: Mask register offset to reg_base | |
735 | * @ack: Ack register offset to reg_base | |
736 | * @eoi: Eoi register offset to reg_base | |
737 | * @type: Type configuration register offset to reg_base | |
738 | * @polarity: Polarity configuration register offset to reg_base | |
739 | */ | |
740 | struct irq_chip_regs { | |
741 | unsigned long enable; | |
742 | unsigned long disable; | |
743 | unsigned long mask; | |
744 | unsigned long ack; | |
745 | unsigned long eoi; | |
746 | unsigned long type; | |
747 | unsigned long polarity; | |
748 | }; | |
749 | ||
750 | /** | |
751 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
752 | * @chip: The real interrupt chip which provides the callbacks | |
753 | * @regs: Register offsets for this chip | |
754 | * @handler: Flow handler associated with this chip | |
755 | * @type: Chip can handle these flow types | |
899f0e66 GF |
756 | * @mask_cache_priv: Cached mask register private to the chip type |
757 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
758 | * |
759 | * A irq_generic_chip can have several instances of irq_chip_type when | |
760 | * it requires different functions and register offsets for different | |
761 | * flow types. | |
762 | */ | |
763 | struct irq_chip_type { | |
764 | struct irq_chip chip; | |
765 | struct irq_chip_regs regs; | |
766 | irq_flow_handler_t handler; | |
767 | u32 type; | |
899f0e66 GF |
768 | u32 mask_cache_priv; |
769 | u32 *mask_cache; | |
7d828062 TG |
770 | }; |
771 | ||
772 | /** | |
773 | * struct irq_chip_generic - Generic irq chip data structure | |
774 | * @lock: Lock to protect register and cache data access | |
775 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
776 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
777 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
be9b22b6 BN |
778 | * @suspend: Function called from core code on suspend once per |
779 | * chip; can be useful instead of irq_chip::suspend to | |
780 | * handle chip details even when no interrupts are in use | |
781 | * @resume: Function called from core code on resume once per chip; | |
782 | * can be useful instead of irq_chip::suspend to handle | |
783 | * chip details even when no interrupts are in use | |
7d828062 TG |
784 | * @irq_base: Interrupt base nr for this chip |
785 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 786 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
787 | * @type_cache: Cached type register |
788 | * @polarity_cache: Cached polarity register | |
789 | * @wake_enabled: Interrupt can wakeup from suspend | |
790 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
791 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
792 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 793 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 794 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 795 | * @domain: irq domain pointer |
cfefd21e | 796 | * @list: List head for keeping track of instances |
7d828062 TG |
797 | * @chip_types: Array of interrupt irq_chip_types |
798 | * | |
799 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
800 | * implementations which can be associated to a particular irq line of | |
801 | * an irq_chip_generic instance. That allows to share and protect | |
802 | * state in an irq_chip_generic instance when we need to implement | |
803 | * different flow mechanisms (level/edge) for it. | |
804 | */ | |
805 | struct irq_chip_generic { | |
806 | raw_spinlock_t lock; | |
807 | void __iomem *reg_base; | |
2b280376 KC |
808 | u32 (*reg_readl)(void __iomem *addr); |
809 | void (*reg_writel)(u32 val, void __iomem *addr); | |
be9b22b6 BN |
810 | void (*suspend)(struct irq_chip_generic *gc); |
811 | void (*resume)(struct irq_chip_generic *gc); | |
7d828062 TG |
812 | unsigned int irq_base; |
813 | unsigned int irq_cnt; | |
814 | u32 mask_cache; | |
815 | u32 type_cache; | |
816 | u32 polarity_cache; | |
817 | u32 wake_enabled; | |
818 | u32 wake_active; | |
819 | unsigned int num_ct; | |
820 | void *private; | |
088f40b7 | 821 | unsigned long installed; |
e8bd834f | 822 | unsigned long unused; |
088f40b7 | 823 | struct irq_domain *domain; |
cfefd21e | 824 | struct list_head list; |
7d828062 TG |
825 | struct irq_chip_type chip_types[0]; |
826 | }; | |
827 | ||
828 | /** | |
829 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
830 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
831 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
832 | * irq chips which need to call irq_set_wake() on | |
833 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 834 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 835 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
b7905595 | 836 | * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) |
7d828062 TG |
837 | */ |
838 | enum irq_gc_flags { | |
839 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
840 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 841 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 842 | IRQ_GC_NO_MASK = 1 << 3, |
b7905595 | 843 | IRQ_GC_BE_IO = 1 << 4, |
7d828062 TG |
844 | }; |
845 | ||
088f40b7 TG |
846 | /* |
847 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
848 | * @irqs_per_chip: Number of interrupts per chip | |
849 | * @num_chips: Number of chips | |
850 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
851 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
852 | * @gc_flags: Generic chip specific setup flags | |
853 | * @gc: Array of pointers to generic interrupt chips | |
854 | */ | |
855 | struct irq_domain_chip_generic { | |
856 | unsigned int irqs_per_chip; | |
857 | unsigned int num_chips; | |
858 | unsigned int irq_flags_to_clear; | |
859 | unsigned int irq_flags_to_set; | |
860 | enum irq_gc_flags gc_flags; | |
861 | struct irq_chip_generic *gc[0]; | |
862 | }; | |
863 | ||
7d828062 TG |
864 | /* Generic chip callback functions */ |
865 | void irq_gc_noop(struct irq_data *d); | |
866 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
867 | void irq_gc_mask_set_bit(struct irq_data *d); | |
868 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
869 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
870 | void irq_gc_ack_set_bit(struct irq_data *d); |
871 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
872 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
873 | void irq_gc_eoi(struct irq_data *d); | |
874 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
875 | ||
876 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
877 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
878 | irq_hw_number_t hw_irq); | |
7d828062 TG |
879 | struct irq_chip_generic * |
880 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
881 | void __iomem *reg_base, irq_flow_handler_t handler); | |
882 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
883 | enum irq_gc_flags flags, unsigned int clr, | |
884 | unsigned int set); | |
885 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
886 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
887 | unsigned int clr, unsigned int set); | |
7d828062 | 888 | |
088f40b7 TG |
889 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
890 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, | |
891 | int num_ct, const char *name, | |
892 | irq_flow_handler_t handler, | |
893 | unsigned int clr, unsigned int set, | |
894 | enum irq_gc_flags flags); | |
895 | ||
896 | ||
7d828062 TG |
897 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
898 | { | |
899 | return container_of(d->chip, struct irq_chip_type, chip); | |
900 | } | |
901 | ||
902 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
903 | ||
904 | #ifdef CONFIG_SMP | |
905 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
906 | { | |
907 | raw_spin_lock(&gc->lock); | |
908 | } | |
909 | ||
910 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
911 | { | |
912 | raw_spin_unlock(&gc->lock); | |
913 | } | |
914 | #else | |
915 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
916 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
917 | #endif | |
918 | ||
332fd7c4 KC |
919 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
920 | u32 val, int reg_offset) | |
921 | { | |
2b280376 KC |
922 | if (gc->reg_writel) |
923 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
924 | else | |
925 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
926 | } |
927 | ||
928 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
929 | int reg_offset) | |
930 | { | |
2b280376 KC |
931 | if (gc->reg_readl) |
932 | return gc->reg_readl(gc->reg_base + reg_offset); | |
933 | else | |
934 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
935 | } |
936 | ||
06fcb0c6 | 937 | #endif /* _LINUX_IRQ_H */ |