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1da177e4 LT |
1 | #ifndef __irq_h |
2 | #define __irq_h | |
3 | ||
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
347a8dc3 | 14 | #if !defined(CONFIG_S390) |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
908dcecd | 20 | #include <linux/irqreturn.h> |
1da177e4 LT |
21 | |
22 | #include <asm/irq.h> | |
23 | #include <asm/ptrace.h> | |
24 | ||
25 | /* | |
26 | * IRQ line status. | |
27 | */ | |
28 | #define IRQ_INPROGRESS 1 /* IRQ handler active - do not enter! */ | |
29 | #define IRQ_DISABLED 2 /* IRQ disabled - do not enter! */ | |
30 | #define IRQ_PENDING 4 /* IRQ pending - replay on enable */ | |
31 | #define IRQ_REPLAY 8 /* IRQ has been replayed but not acked yet */ | |
32 | #define IRQ_AUTODETECT 16 /* IRQ is being autodetected */ | |
33 | #define IRQ_WAITING 32 /* IRQ not yet seen - for autodetection */ | |
34 | #define IRQ_LEVEL 64 /* IRQ level triggered */ | |
35 | #define IRQ_MASKED 128 /* IRQ masked - shouldn't be seen again */ | |
f26fdd59 KW |
36 | #if defined(ARCH_HAS_IRQ_PER_CPU) |
37 | # define IRQ_PER_CPU 256 /* IRQ is per CPU */ | |
38 | # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) | |
39 | #else | |
40 | # define CHECK_IRQ_PER_CPU(var) 0 | |
41 | #endif | |
1da177e4 LT |
42 | |
43 | /* | |
44 | * Interrupt controller descriptor. This is all we need | |
45 | * to describe about the low-level hardware. | |
46 | */ | |
47 | struct hw_interrupt_type { | |
48 | const char * typename; | |
49 | unsigned int (*startup)(unsigned int irq); | |
50 | void (*shutdown)(unsigned int irq); | |
51 | void (*enable)(unsigned int irq); | |
52 | void (*disable)(unsigned int irq); | |
53 | void (*ack)(unsigned int irq); | |
54 | void (*end)(unsigned int irq); | |
55 | void (*set_affinity)(unsigned int irq, cpumask_t dest); | |
b77d6adc PBG |
56 | /* Currently used only by UML, might disappear one day.*/ |
57 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
dbce706e | 58 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 59 | #endif |
1da177e4 LT |
60 | }; |
61 | ||
62 | typedef struct hw_interrupt_type hw_irq_controller; | |
63 | ||
64 | /* | |
65 | * This is the "IRQ descriptor", which contains various information | |
66 | * about the irq, including what kind of hardware handling it has, | |
67 | * whether it is disabled etc etc. | |
68 | * | |
69 | * Pad this out to 32 bytes for cache and indexing reasons. | |
70 | */ | |
71 | typedef struct irq_desc { | |
72 | hw_irq_controller *handler; | |
73 | void *handler_data; | |
74 | struct irqaction *action; /* IRQ action list */ | |
75 | unsigned int status; /* IRQ status */ | |
76 | unsigned int depth; /* nested irq disables */ | |
77 | unsigned int irq_count; /* For detecting broken interrupts */ | |
78 | unsigned int irqs_unhandled; | |
79 | spinlock_t lock; | |
54d5d424 AR |
80 | #if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE) |
81 | unsigned int move_irq; /* Flag need to re-target intr dest*/ | |
82 | #endif | |
1da177e4 LT |
83 | } ____cacheline_aligned irq_desc_t; |
84 | ||
85 | extern irq_desc_t irq_desc [NR_IRQS]; | |
86 | ||
54d5d424 AR |
87 | /* Return a pointer to the irq descriptor for IRQ. */ |
88 | static inline irq_desc_t * | |
89 | irq_descp (int irq) | |
90 | { | |
91 | return irq_desc + irq; | |
92 | } | |
93 | ||
1da177e4 LT |
94 | #include <asm/hw_irq.h> /* the arch dependent stuff */ |
95 | ||
96 | extern int setup_irq(unsigned int irq, struct irqaction * new); | |
97 | ||
98 | #ifdef CONFIG_GENERIC_HARDIRQS | |
99 | extern cpumask_t irq_affinity[NR_IRQS]; | |
54d5d424 AR |
100 | |
101 | #ifdef CONFIG_SMP | |
102 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
103 | { | |
104 | irq_affinity[irq] = mask; | |
105 | } | |
106 | #else | |
107 | static inline void set_native_irq_info(int irq, cpumask_t mask) | |
108 | { | |
109 | } | |
110 | #endif | |
111 | ||
112 | #ifdef CONFIG_SMP | |
113 | ||
114 | #if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE) | |
115 | extern cpumask_t pending_irq_cpumask[NR_IRQS]; | |
116 | ||
c777ac55 AM |
117 | void set_pending_irq(unsigned int irq, cpumask_t mask); |
118 | void move_native_irq(int irq); | |
54d5d424 AR |
119 | |
120 | #ifdef CONFIG_PCI_MSI | |
121 | /* | |
122 | * Wonder why these are dummies? | |
123 | * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq() | |
124 | * counter part after translating the vector to irq info. We need to perform | |
125 | * this operation on the real irq, when we dont use vector, i.e when | |
126 | * pci_use_vector() is false. | |
127 | */ | |
128 | static inline void move_irq(int irq) | |
129 | { | |
130 | } | |
131 | ||
132 | static inline void set_irq_info(int irq, cpumask_t mask) | |
133 | { | |
134 | } | |
135 | ||
136 | #else // CONFIG_PCI_MSI | |
137 | ||
138 | static inline void move_irq(int irq) | |
139 | { | |
140 | move_native_irq(irq); | |
141 | } | |
142 | ||
143 | static inline void set_irq_info(int irq, cpumask_t mask) | |
144 | { | |
145 | set_native_irq_info(irq, mask); | |
146 | } | |
147 | #endif // CONFIG_PCI_MSI | |
148 | ||
149 | #else // CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE | |
150 | ||
151 | #define move_irq(x) | |
152 | #define move_native_irq(x) | |
153 | #define set_pending_irq(x,y) | |
154 | static inline void set_irq_info(int irq, cpumask_t mask) | |
155 | { | |
156 | set_native_irq_info(irq, mask); | |
157 | } | |
158 | ||
159 | #endif // CONFIG_GENERIC_PENDING_IRQ | |
160 | ||
161 | #else // CONFIG_SMP | |
162 | ||
163 | #define move_irq(x) | |
164 | #define move_native_irq(x) | |
165 | ||
166 | #endif // CONFIG_SMP | |
167 | ||
1b61b910 ZY |
168 | #ifdef CONFIG_IRQBALANCE |
169 | extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask); | |
170 | #else | |
171 | static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) | |
172 | { | |
173 | } | |
174 | #endif | |
175 | ||
1da177e4 LT |
176 | extern int no_irq_affinity; |
177 | extern int noirqdebug_setup(char *str); | |
178 | ||
908dcecd | 179 | extern fastcall irqreturn_t handle_IRQ_event(unsigned int irq, struct pt_regs *regs, |
200803df | 180 | struct irqaction *action); |
1da177e4 | 181 | extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs); |
200803df AC |
182 | extern void note_interrupt(unsigned int irq, irq_desc_t *desc, |
183 | int action_ret, struct pt_regs *regs); | |
1da177e4 LT |
184 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); |
185 | ||
186 | extern void init_irq_proc(void); | |
eee45269 IK |
187 | |
188 | #ifdef CONFIG_AUTO_IRQ_AFFINITY | |
189 | extern int select_smp_affinity(unsigned int irq); | |
190 | #else | |
191 | static inline int | |
192 | select_smp_affinity(unsigned int irq) | |
193 | { | |
194 | return 1; | |
195 | } | |
196 | #endif | |
197 | ||
1da177e4 LT |
198 | #endif |
199 | ||
200 | extern hw_irq_controller no_irq_type; /* needed in every arch ? */ | |
201 | ||
202 | #endif | |
203 | ||
204 | #endif /* __irq_h */ |