[mirror_ubuntu-bionic-kernel.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>

#include <asm/irq.h>
#include <asm/ptrace.h>

/*
 * IRQ line status.
 */
#define IRQ_INPROGRESS	1	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED	2	/* IRQ disabled - do not enter! */
#define IRQ_PENDING	4	/* IRQ pending - replay on enable */
#define IRQ_REPLAY	8	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT	16	/* IRQ is being autodetected */
#define IRQ_WAITING	32	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL	64	/* IRQ level triggered */
#define IRQ_MASKED	128	/* IRQ masked - shouldn't be seen again */
#ifdef CONFIG_IRQ_PER_CPU
# define IRQ_PER_CPU	256	/* IRQ is per CPU */
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
#else
# define CHECK_IRQ_PER_CPU(var) 0
#endif

#define IRQ_NOPROBE	512	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST	1024	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN	2048	/* IRQ will not be enabled on request irq */
#define IRQ_DELAYED_DISABLE \
			4096	/* IRQ disable (masking) happens delayed. */

/*
 * IRQ types, see also include/linux/interrupt.h
 */
#define IRQ_TYPE_NONE		0x0000		/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x0001		/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x0002		/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x0004		/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x0008		/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x000f		/* Mask of the above */
#define IRQ_TYPE_SIMPLE		0x0010		/* Simple type */
#define IRQ_TYPE_PERCPU		0x0020		/* Per CPU type */
#define IRQ_TYPE_PROBE		0x0040		/* Probing in progress */

struct proc_dir_entry;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq, cpumask_t dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

/**
 * struct irq_desc - interrupt descriptor
 *
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @irq_count:		stats field to detect stalled irqs
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @move_irq:		need to re-target IRQ destination
 * @dir:		/proc/irq/ procfs entry
 * @affinity_entry:	/proc/irq/smp_affinity procfs entry on SMP
 *
 * Pad this out to 32 bytes for cache and indexing reasons.
 */
struct irq_desc {
	void fastcall		(*handle_irq)(unsigned int irq,
					      struct irq_desc *desc,
					      struct pt_regs *regs);
	struct irq_chip		*chip;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_t		affinity;
	unsigned int		cpu;
#endif
#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
	cpumask_t		pending_mask;
	unsigned int		move_irq;	/* need to re-target IRQ dest */
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *dir;
#endif
} ____cacheline_aligned;

extern struct irq_desc irq_desc[NR_IRQS];

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
typedef struct irq_chip		hw_irq_controller;
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
	irq_desc[irq].affinity = mask;
}
#else
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_SMP

#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)

void set_pending_irq(unsigned int irq, cpumask_t mask);
void move_native_irq(int irq);

#ifdef CONFIG_PCI_MSI
/*
 * Wonder why these are dummies?
 * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
 * counter part after translating the vector to irq info. We need to perform
 * this operation on the real irq, when we dont use vector, i.e when
 * pci_use_vector() is false.
 */
static inline void move_irq(int irq)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
}

#else /* CONFIG_PCI_MSI */

static inline void move_irq(int irq)
{
	move_native_irq(irq);
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_PCI_MSI */

#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_irq(x)
#define move_native_irq(x)

#endif /* CONFIG_SMP */

#ifdef CONFIG_IRQBALANCE
extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
#else
static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_AUTO_IRQ_AFFINITY
extern int select_smp_affinity(unsigned int irq);
#else
static inline int select_smp_affinity(unsigned int irq)
{
	return 1;
}
#endif

extern int no_irq_affinity;

/* Handle irq action chains: */
extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
			    struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void fastcall
handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
			 struct pt_regs *regs);
extern void fastcall
handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_simple_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_bad_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);

/*
 * Get a descriptive string for the highlevel handler, for
 * /proc/interrupts output:
 */
extern const char *
handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *));

/*
 * Monolithic do_IRQ implementation.
 * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
 */
extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
{
	struct irq_desc *desc = irq_desc + irq;

	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc, regs);
	else
		__do_IRQ(irq, regs);
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   int action_ret, struct pt_regs *regs);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Initialize /proc/irq/ */
extern void init_irq_proc(void);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementation: */
extern struct irq_chip no_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 void fastcall (*handle)(unsigned int,
						 struct irq_desc *,
						 struct pt_regs *));
extern void
__set_irq_handler(unsigned int irq,
		  void fastcall (*handle)(unsigned int, struct irq_desc *,
					  struct pt_regs *),
		  int is_chained);

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq,
		void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *))
{
	__set_irq_handler(irq, handle, 0);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			void fastcall (*handle)(unsigned int, struct irq_desc *,
						struct pt_regs *))
{
	__set_irq_handler(irq, handle, 1);
}

/* Set/get chip/data for an IRQ: */

extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);

#define get_irq_chip(irq)	(irq_desc[irq].chip)
#define get_irq_chip_data(irq)	(irq_desc[irq].chip_data)
#define get_irq_data(irq)	(irq_desc[irq].handler_data)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
1da177e4 LT	21
	22	#include <asm/irq.h>
	23	#include <asm/ptrace.h>
	24
	25	/*
	26	* IRQ line status.
	27	*/
	28	#define IRQ_INPROGRESS 1 /* IRQ handler active - do not enter! */
	29	#define IRQ_DISABLED 2 /* IRQ disabled - do not enter! */
	30	#define IRQ_PENDING 4 /* IRQ pending - replay on enable */
	31	#define IRQ_REPLAY 8 /* IRQ has been replayed but not acked yet */
	32	#define IRQ_AUTODETECT 16 /* IRQ is being autodetected */
	33	#define IRQ_WAITING 32 /* IRQ not yet seen - for autodetection */
	34	#define IRQ_LEVEL 64 /* IRQ level triggered */
	35	#define IRQ_MASKED 128 /* IRQ masked - shouldn't be seen again */
0d7012a9	36	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 KW	37	# define IRQ_PER_CPU 256 /* IRQ is per CPU */
	38	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
	39	#else
	40	# define CHECK_IRQ_PER_CPU(var) 0
	41	#endif
1da177e4	42
3418d724	43	#define IRQ_NOPROBE 512 /* IRQ is not valid for probing */
6550c775	44	#define IRQ_NOREQUEST 1024 /* IRQ cannot be requested */
94d39e1f	45	#define IRQ_NOAUTOEN 2048 /* IRQ will not be enabled on request irq */
6a6de9ef TG	46	#define IRQ_DELAYED_DISABLE \
	47	4096 /* IRQ disable (masking) happens delayed. */
	48
	49	/*
	50	* IRQ types, see also include/linux/interrupt.h
	51	*/
	52	#define IRQ_TYPE_NONE 0x0000 /* Default, unspecified type */
	53	#define IRQ_TYPE_EDGE_RISING 0x0001 /* Edge rising type */
	54	#define IRQ_TYPE_EDGE_FALLING 0x0002 /* Edge falling type */
	55	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	56	#define IRQ_TYPE_LEVEL_HIGH 0x0004 /* Level high type */
	57	#define IRQ_TYPE_LEVEL_LOW 0x0008 /* Level low type */
f210be19	58	#define IRQ_TYPE_SENSE_MASK 0x000f /* Mask of the above */
6a6de9ef TG	59	#define IRQ_TYPE_SIMPLE 0x0010 /* Simple type */
	60	#define IRQ_TYPE_PERCPU 0x0020 /* Per CPU type */
	61	#define IRQ_TYPE_PROBE 0x0040 /* Probing in progress */
	62
	63	struct proc_dir_entry;
	64
8fee5c36	65	/**
6a6de9ef	66	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	67	*
	68	* @name: name for /proc/interrupts
	69	* @startup: start up the interrupt (defaults to ->enable if NULL)
	70	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	71	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	72	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	73	* @ack: start of a new interrupt
	74	* @mask: mask an interrupt source
	75	* @mask_ack: ack and mask an interrupt source
	76	* @unmask: unmask an interrupt source
47c2a3aa IM	77	* @eoi: end of interrupt - chip level
47c2a3aa IM	78	* @end: end of interrupt - flow level
8fee5c36 IM	79	* @set_affinity: set the CPU affinity on SMP machines
	80	* @retrigger: resend an IRQ to the CPU
	81	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	82	* @set_wake: enable/disable power-management wake-on of an IRQ
	83	*
	84	* @release: release function solely used by UML
6a6de9ef	85	* @typename: obsoleted by name, kept as migration helper
1da177e4	86	*/
6a6de9ef TG	87	struct irq_chip {
6a6de9ef TG	88	const char *name;
71d218b7 IM	89	unsigned int (*startup)(unsigned int irq);
	90	void (*shutdown)(unsigned int irq);
	91	void (*enable)(unsigned int irq);
	92	void (*disable)(unsigned int irq);
6a6de9ef	93
71d218b7	94	void (*ack)(unsigned int irq);
6a6de9ef TG	95	void (*mask)(unsigned int irq);
	96	void (*mask_ack)(unsigned int irq);
	97	void (*unmask)(unsigned int irq);
47c2a3aa	98	void (*eoi)(unsigned int irq);
6a6de9ef	99
71d218b7 IM	100	void (*end)(unsigned int irq);
71d218b7 IM	101	void (*set_affinity)(unsigned int irq, cpumask_t dest);
c0ad90a3	102	int (*retrigger)(unsigned int irq);
6a6de9ef TG	103	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	104	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	105
b77d6adc PBG	106	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	107	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	108	void (release)(unsigned int irq, void dev_id);
b77d6adc	109	#endif
6a6de9ef TG	110	/*
	111	* For compatibility, ->typename is copied into ->name.
	112	* Will disappear.
	113	*/
	114	const char *typename;
1da177e4 LT	115	};
1da177e4 LT	116
8fee5c36 IM	117	/**
	118	* struct irq_desc - interrupt descriptor
	119	*
6a6de9ef TG	120	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
	121	* @chip: low level interrupt hardware access
	122	* @handler_data: per-IRQ data for the irq_chip methods
	123	* @chip_data: platform-specific per-chip private data for the chip
	124	* methods, to allow shared chip implementations
8fee5c36 IM	125	* @action: the irq action chain
	126	* @status: status information
	127	* @depth: disable-depth, for nested irq_disable() calls
	128	* @irq_count: stats field to detect stalled irqs
	129	* @irqs_unhandled: stats field for spurious unhandled interrupts
	130	* @lock: locking for SMP
	131	* @affinity: IRQ affinity on SMP
6a6de9ef	132	* @cpu: cpu index useful for balancing
8fee5c36 IM	133	* @pending_mask: pending rebalanced interrupts
	134	* @move_irq: need to re-target IRQ destination
	135	* @dir: /proc/irq/ procfs entry
	136	* @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
1da177e4 LT	137	*
	138	* Pad this out to 32 bytes for cache and indexing reasons.
	139	*/
34ffdb72	140	struct irq_desc {
6a6de9ef TG	141	void fastcall (*handle_irq)(unsigned int irq,
	142	struct irq_desc *desc,
	143	struct pt_regs *regs);
	144	struct irq_chip *chip;
	145	void *handler_data;
71d218b7 IM	146	void *chip_data;
	147	struct irqaction action; / IRQ action list */
	148	unsigned int status; /* IRQ status */
6a6de9ef	149
71d218b7 IM	150	unsigned int depth; /* nested irq disables */
	151	unsigned int irq_count; /* For detecting broken IRQs */
	152	unsigned int irqs_unhandled;
	153	spinlock_t lock;
a53da52f	154	#ifdef CONFIG_SMP
71d218b7	155	cpumask_t affinity;
6a6de9ef	156	unsigned int cpu;
a53da52f	157	#endif
06fcb0c6	158	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
cd916d31	159	cpumask_t pending_mask;
71d218b7	160	unsigned int move_irq; /* need to re-target IRQ dest */
54d5d424	161	#endif
4a733ee1 IM	162	#ifdef CONFIG_PROC_FS
	163	struct proc_dir_entry *dir;
	164	#endif
34ffdb72	165	} ____cacheline_aligned;
1da177e4	166
34ffdb72	167	extern struct irq_desc irq_desc[NR_IRQS];
1da177e4	168
34ffdb72 IM	169	/*
	170	* Migration helpers for obsolete names, they will go away:
	171	*/
6a6de9ef TG	172	#define hw_interrupt_type irq_chip
	173	typedef struct irq_chip hw_irq_controller;
	174	#define no_irq_type no_irq_chip
34ffdb72 IM	175	typedef struct irq_desc irq_desc_t;
	176
	177	/*
	178	* Pick up the arch-dependent methods:
	179	*/
	180	#include <asm/hw_irq.h>
1da177e4	181
06fcb0c6	182	extern int setup_irq(unsigned int irq, struct irqaction *new);
1da177e4 LT	183
1da177e4 LT	184	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	185
54d5d424 AR	186	#ifdef CONFIG_SMP
	187	static inline void set_native_irq_info(int irq, cpumask_t mask)
	188	{
a53da52f	189	irq_desc[irq].affinity = mask;
54d5d424 AR	190	}
	191	#else
	192	static inline void set_native_irq_info(int irq, cpumask_t mask)
	193	{
	194	}
	195	#endif
	196
	197	#ifdef CONFIG_SMP
	198
06fcb0c6	199	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
54d5d424	200
c777ac55 AM	201	void set_pending_irq(unsigned int irq, cpumask_t mask);
c777ac55 AM	202	void move_native_irq(int irq);
54d5d424 AR	203
	204	#ifdef CONFIG_PCI_MSI
	205	/*
	206	* Wonder why these are dummies?
	207	* For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
	208	* counter part after translating the vector to irq info. We need to perform
	209	* this operation on the real irq, when we dont use vector, i.e when
	210	* pci_use_vector() is false.
	211	*/
	212	static inline void move_irq(int irq)
	213	{
	214	}
	215
	216	static inline void set_irq_info(int irq, cpumask_t mask)
	217	{
	218	}
	219
06fcb0c6	220	#else /* CONFIG_PCI_MSI */
54d5d424 AR	221
	222	static inline void move_irq(int irq)
	223	{
	224	move_native_irq(irq);
	225	}
	226
	227	static inline void set_irq_info(int irq, cpumask_t mask)
	228	{
	229	set_native_irq_info(irq, mask);
	230	}
54d5d424	231
06fcb0c6 IM	232	#endif /* CONFIG_PCI_MSI */
	233
	234	#else /* CONFIG_GENERIC_PENDING_IRQ \|\| CONFIG_IRQBALANCE */
	235
	236	static inline void move_irq(int irq)
	237	{
	238	}
	239
	240	static inline void move_native_irq(int irq)
	241	{
	242	}
	243
	244	static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
	245	{
	246	}
54d5d424	247
54d5d424 AR	248	static inline void set_irq_info(int irq, cpumask_t mask)
	249	{
	250	set_native_irq_info(irq, mask);
	251	}
	252
06fcb0c6	253	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	254
06fcb0c6	255	#else /* CONFIG_SMP */
54d5d424 AR	256
	257	#define move_irq(x)
	258	#define move_native_irq(x)
	259
06fcb0c6	260	#endif /* CONFIG_SMP */
54d5d424	261
1b61b910 ZY	262	#ifdef CONFIG_IRQBALANCE
	263	extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
	264	#else
	265	static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
	266	{
	267	}
	268	#endif
	269
71d218b7 IM	270	#ifdef CONFIG_AUTO_IRQ_AFFINITY
	271	extern int select_smp_affinity(unsigned int irq);
	272	#else
	273	static inline int select_smp_affinity(unsigned int irq)
	274	{
	275	return 1;
	276	}
	277	#endif
	278
1da177e4	279	extern int no_irq_affinity;
1da177e4	280
6a6de9ef TG	281	/* Handle irq action chains: */
	282	extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
	283	struct irqaction *action);
	284
	285	/*
	286	* Built-in IRQ handlers for various IRQ types,
	287	* callable via desc->chip->handle_irq()
	288	*/
	289	extern void fastcall
	290	handle_level_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	291	extern void fastcall
47c2a3aa	292	handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
6a6de9ef TG	293	struct pt_regs *regs);
	294	extern void fastcall
	295	handle_edge_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	296	extern void fastcall
	297	handle_simple_irq(unsigned int irq, struct irq_desc *desc,
	298	struct pt_regs *regs);
	299	extern void fastcall
	300	handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
	301	struct pt_regs *regs);
	302	extern void fastcall
	303	handle_bad_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	304
	305	/*
	306	* Get a descriptive string for the highlevel handler, for
	307	* /proc/interrupts output:
	308	*/
	309	extern const char *
	310	handle_irq_name(void fastcall (handle)(unsigned int, struct irq_desc ,
	311	struct pt_regs *));
	312
2e60bbb6	313	/*
6a6de9ef TG	314	* Monolithic do_IRQ implementation.
6a6de9ef TG	315	* (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
2e60bbb6	316	*/
1da177e4	317	extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
2e60bbb6	318
dae86204 IM	319	/*
	320	* Architectures call this to let the generic IRQ layer
	321	* handle an interrupt. If the descriptor is attached to an
	322	* irqchip-style controller then we call the ->handle_irq() handler,
	323	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	324	*/
	325	static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
	326	{
	327	struct irq_desc *desc = irq_desc + irq;
	328
	329	if (likely(desc->handle_irq))
	330	desc->handle_irq(irq, desc, regs);
	331	else
	332	__do_IRQ(irq, regs);
	333	}
	334
6a6de9ef	335	/* Handling of unhandled and spurious interrupts: */
34ffdb72	336	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
2e60bbb6	337	int action_ret, struct pt_regs *regs);
1da177e4	338
a4633adc TG	339	/* Resending of interrupts :*/
	340	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	341
6a6de9ef	342	/* Initialize /proc/irq/ */
1da177e4	343	extern void init_irq_proc(void);
eee45269	344
6a6de9ef TG	345	/* Enable/disable irq debugging output: */
	346	extern int noirqdebug_setup(char *str);
	347
	348	/* Checks whether the interrupt can be requested by request_irq(): */
	349	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	350
	351	/* Dummy irq-chip implementation: */
	352	extern struct irq_chip no_irq_chip;
	353
	354	extern void
	355	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	356	void fastcall (*handle)(unsigned int,
	357	struct irq_desc *,
	358	struct pt_regs *));
	359	extern void
	360	__set_irq_handler(unsigned int irq,
	361	void fastcall (handle)(unsigned int, struct irq_desc ,
	362	struct pt_regs *),
	363	int is_chained);
1da177e4	364
6a6de9ef TG	365	/*
	366	* Set a highlevel flow handler for a given IRQ:
	367	*/
	368	static inline void
	369	set_irq_handler(unsigned int irq,
	370	void fastcall (handle)(unsigned int, struct irq_desc ,
	371	struct pt_regs *))
	372	{
	373	__set_irq_handler(irq, handle, 0);
	374	}
	375
	376	/*
	377	* Set a highlevel chained flow handler for a given IRQ.
	378	* (a chained handler is automatically enabled and set to
	379	* IRQ_NOREQUEST and IRQ_NOPROBE)
	380	*/
	381	static inline void
	382	set_irq_chained_handler(unsigned int irq,
	383	void fastcall (handle)(unsigned int, struct irq_desc ,
	384	struct pt_regs *))
	385	{
	386	__set_irq_handler(irq, handle, 1);
	387	}
	388
dd87eb3a TG	389	/* Set/get chip/data for an IRQ: */
	390
	391	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	392	extern int set_irq_data(unsigned int irq, void *data);
	393	extern int set_irq_chip_data(unsigned int irq, void *data);
	394	extern int set_irq_type(unsigned int irq, unsigned int type);
	395
	396	#define get_irq_chip(irq) (irq_desc[irq].chip)
	397	#define get_irq_chip_data(irq) (irq_desc[irq].chip_data)
	398	#define get_irq_data(irq) (irq_desc[irq].handler_data)
	399
6a6de9ef	400	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	401
06fcb0c6	402	#endif /* !CONFIG_S390 */
1da177e4	403
06fcb0c6	404	#endif /* _LINUX_IRQ_H */