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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
3aa551c9 | 25 | #include <linux/wait.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
ab7798ff | 31 | struct seq_file; |
ec53cf23 | 32 | struct module; |
57a58a94 | 33 | struct irq_desc; |
78129576 | 34 | struct irq_data; |
ec701584 | 35 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 36 | struct irq_desc *desc); |
78129576 | 37 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 38 | |
1da177e4 LT |
39 | /* |
40 | * IRQ line status. | |
6e213616 | 41 | * |
5d4d8fc9 TG |
42 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
43 | * | |
44 | * IRQ_TYPE_NONE - default, unspecified type | |
45 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
46 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
47 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
48 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
49 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
50 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
51 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
52 | * IRQ_TYPE_PROBE - Special flag for probing in progress | |
53 | * | |
54 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
55 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
56 | * updated in the code when the above trigger | |
0911f124 | 57 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
58 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
59 | * it from affinity setting | |
60 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
61 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
62 | * request_irq() | |
7f1b1244 | 63 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
64 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
65 | * request/setup_irq() | |
66 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
67 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
68 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
31d9d9b6 | 69 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
1da177e4 | 70 | */ |
5d4d8fc9 TG |
71 | enum { |
72 | IRQ_TYPE_NONE = 0x00000000, | |
73 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
74 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
75 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
76 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
77 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
78 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
79 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
80 | ||
81 | IRQ_TYPE_PROBE = 0x00000010, | |
82 | ||
83 | IRQ_LEVEL = (1 << 8), | |
84 | IRQ_PER_CPU = (1 << 9), | |
85 | IRQ_NOPROBE = (1 << 10), | |
86 | IRQ_NOREQUEST = (1 << 11), | |
87 | IRQ_NOAUTOEN = (1 << 12), | |
88 | IRQ_NO_BALANCING = (1 << 13), | |
89 | IRQ_MOVE_PCNTXT = (1 << 14), | |
90 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 91 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 92 | IRQ_PER_CPU_DEVID = (1 << 17), |
5d4d8fc9 | 93 | }; |
950f4427 | 94 | |
44247184 TG |
95 | #define IRQF_MODIFY_MASK \ |
96 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 97 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
31d9d9b6 | 98 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) |
44247184 | 99 | |
8f53f924 TG |
100 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
101 | ||
3b8249e7 TG |
102 | /* |
103 | * Return value for chip->irq_set_affinity() | |
104 | * | |
105 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
106 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
107 | */ | |
108 | enum { | |
109 | IRQ_SET_MASK_OK = 0, | |
110 | IRQ_SET_MASK_OK_NOCOPY, | |
111 | }; | |
112 | ||
5b912c10 | 113 | struct msi_desc; |
08a543ad | 114 | struct irq_domain; |
6a6de9ef | 115 | |
ff7dcd44 TG |
116 | /** |
117 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
118 | * @irq: interrupt number | |
08a543ad | 119 | * @hwirq: hardware interrupt number, local to the interrupt domain |
ff7dcd44 | 120 | * @node: node index useful for balancing |
30398bf6 | 121 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 122 | * Use accessor functions to deal with it |
ff7dcd44 | 123 | * @chip: low level interrupt hardware access |
08a543ad GL |
124 | * @domain: Interrupt translation domain; responsible for mapping |
125 | * between hwirq number and linux irq number. | |
ff7dcd44 TG |
126 | * @handler_data: per-IRQ data for the irq_chip methods |
127 | * @chip_data: platform-specific per-chip private data for the chip | |
128 | * methods, to allow shared chip implementations | |
129 | * @msi_desc: MSI descriptor | |
130 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
131 | * |
132 | * The fields here need to overlay the ones in irq_desc until we | |
133 | * cleaned up the direct references and switched everything over to | |
134 | * irq_data. | |
135 | */ | |
136 | struct irq_data { | |
137 | unsigned int irq; | |
08a543ad | 138 | unsigned long hwirq; |
ff7dcd44 | 139 | unsigned int node; |
91c49917 | 140 | unsigned int state_use_accessors; |
ff7dcd44 | 141 | struct irq_chip *chip; |
08a543ad | 142 | struct irq_domain *domain; |
ff7dcd44 TG |
143 | void *handler_data; |
144 | void *chip_data; | |
145 | struct msi_desc *msi_desc; | |
146 | #ifdef CONFIG_SMP | |
147 | cpumask_var_t affinity; | |
148 | #endif | |
ff7dcd44 TG |
149 | }; |
150 | ||
f230b6d5 TG |
151 | /* |
152 | * Bit masks for irq_data.state | |
153 | * | |
876dbd4c | 154 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 155 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
156 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
157 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 158 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 159 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
160 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
161 | * from suspend | |
e1ef8241 TG |
162 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
163 | * context | |
32f4125e TG |
164 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
165 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
166 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
f230b6d5 TG |
167 | */ |
168 | enum { | |
876dbd4c | 169 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
170 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
171 | IRQD_NO_BALANCING = (1 << 10), | |
172 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 173 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 174 | IRQD_LEVEL = (1 << 13), |
7f94226f | 175 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 176 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 177 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
178 | IRQD_IRQ_MASKED = (1 << 17), |
179 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
f230b6d5 TG |
180 | }; |
181 | ||
182 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
183 | { | |
184 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
185 | } | |
186 | ||
a005677b TG |
187 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
188 | { | |
189 | return d->state_use_accessors & IRQD_PER_CPU; | |
190 | } | |
191 | ||
192 | static inline bool irqd_can_balance(struct irq_data *d) | |
193 | { | |
194 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
195 | } | |
196 | ||
2bdd1055 TG |
197 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
198 | { | |
199 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
200 | } | |
201 | ||
ee38c04b TG |
202 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
203 | { | |
204 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
205 | } | |
206 | ||
876dbd4c TG |
207 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
208 | { | |
209 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
210 | } | |
211 | ||
212 | /* | |
213 | * Must only be called inside irq_chip.irq_set_type() functions. | |
214 | */ | |
215 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
216 | { | |
217 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
218 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
219 | } | |
220 | ||
221 | static inline bool irqd_is_level_type(struct irq_data *d) | |
222 | { | |
223 | return d->state_use_accessors & IRQD_LEVEL; | |
224 | } | |
225 | ||
7f94226f TG |
226 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
227 | { | |
228 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
229 | } | |
230 | ||
e1ef8241 TG |
231 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
232 | { | |
233 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
234 | } | |
235 | ||
801a0e9a TG |
236 | static inline bool irqd_irq_disabled(struct irq_data *d) |
237 | { | |
238 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
239 | } | |
240 | ||
32f4125e TG |
241 | static inline bool irqd_irq_masked(struct irq_data *d) |
242 | { | |
243 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
244 | } | |
245 | ||
246 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
247 | { | |
248 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
249 | } | |
250 | ||
9cff60df TG |
251 | /* |
252 | * Functions for chained handlers which can be enabled/disabled by the | |
253 | * standard disable_irq/enable_irq calls. Must be called with | |
254 | * irq_desc->lock held. | |
255 | */ | |
256 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
257 | { | |
258 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
259 | } | |
260 | ||
261 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
262 | { | |
263 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
264 | } | |
265 | ||
8fee5c36 | 266 | /** |
6a6de9ef | 267 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
268 | * |
269 | * @name: name for /proc/interrupts | |
f8822657 TG |
270 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
271 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
272 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
273 | * @irq_disable: disable the interrupt | |
274 | * @irq_ack: start of a new interrupt | |
275 | * @irq_mask: mask an interrupt source | |
276 | * @irq_mask_ack: ack and mask an interrupt source | |
277 | * @irq_unmask: unmask an interrupt source | |
278 | * @irq_eoi: end of interrupt | |
279 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
280 | * @irq_retrigger: resend an IRQ to the CPU | |
281 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
282 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
283 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
284 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
285 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
286 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
cfefd21e TG |
287 | * @irq_suspend: function called from core code on suspend once per chip |
288 | * @irq_resume: function called from core code on resume once per chip | |
289 | * @irq_pm_shutdown: function called from core code on shutdown once per chip | |
ab7798ff | 290 | * @irq_print_chip: optional to print special chip info in show_interrupts |
2bff17ad | 291 | * @flags: chip specific flags |
70aedd24 | 292 | * |
8fee5c36 | 293 | * @release: release function solely used by UML |
1da177e4 | 294 | */ |
6a6de9ef TG |
295 | struct irq_chip { |
296 | const char *name; | |
f8822657 TG |
297 | unsigned int (*irq_startup)(struct irq_data *data); |
298 | void (*irq_shutdown)(struct irq_data *data); | |
299 | void (*irq_enable)(struct irq_data *data); | |
300 | void (*irq_disable)(struct irq_data *data); | |
301 | ||
302 | void (*irq_ack)(struct irq_data *data); | |
303 | void (*irq_mask)(struct irq_data *data); | |
304 | void (*irq_mask_ack)(struct irq_data *data); | |
305 | void (*irq_unmask)(struct irq_data *data); | |
306 | void (*irq_eoi)(struct irq_data *data); | |
307 | ||
308 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
309 | int (*irq_retrigger)(struct irq_data *data); | |
310 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
311 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
312 | ||
313 | void (*irq_bus_lock)(struct irq_data *data); | |
314 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
315 | ||
0fdb4b25 DD |
316 | void (*irq_cpu_online)(struct irq_data *data); |
317 | void (*irq_cpu_offline)(struct irq_data *data); | |
318 | ||
cfefd21e TG |
319 | void (*irq_suspend)(struct irq_data *data); |
320 | void (*irq_resume)(struct irq_data *data); | |
321 | void (*irq_pm_shutdown)(struct irq_data *data); | |
322 | ||
ab7798ff TG |
323 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
324 | ||
2bff17ad TG |
325 | unsigned long flags; |
326 | ||
b77d6adc PBG |
327 | /* Currently used only by UML, might disappear one day.*/ |
328 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 329 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 330 | #endif |
1da177e4 LT |
331 | }; |
332 | ||
d4d5e089 TG |
333 | /* |
334 | * irq_chip specific flags | |
335 | * | |
77694b40 TG |
336 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
337 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 338 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
339 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
340 | * when irq enabled | |
60f96b41 | 341 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
d4d5e089 TG |
342 | */ |
343 | enum { | |
344 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 345 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 346 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 347 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 348 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
d4d5e089 TG |
349 | }; |
350 | ||
e144710b TG |
351 | /* This include will go away once we isolated irq_desc usage to core code */ |
352 | #include <linux/irqdesc.h> | |
0b8f1efa | 353 | |
34ffdb72 IM |
354 | /* |
355 | * Pick up the arch-dependent methods: | |
356 | */ | |
357 | #include <asm/hw_irq.h> | |
1da177e4 | 358 | |
b683de2b TG |
359 | #ifndef NR_IRQS_LEGACY |
360 | # define NR_IRQS_LEGACY 0 | |
361 | #endif | |
362 | ||
1318a481 TG |
363 | #ifndef ARCH_IRQ_INIT_FLAGS |
364 | # define ARCH_IRQ_INIT_FLAGS 0 | |
365 | #endif | |
366 | ||
c1594b77 | 367 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 368 | |
e144710b | 369 | struct irqaction; |
06fcb0c6 | 370 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 371 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
372 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
373 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 374 | |
0fdb4b25 DD |
375 | extern void irq_cpu_online(void); |
376 | extern void irq_cpu_offline(void); | |
c2d0c555 | 377 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
0fdb4b25 | 378 | |
1da177e4 | 379 | #ifdef CONFIG_GENERIC_HARDIRQS |
06fcb0c6 | 380 | |
3a3856d0 | 381 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
382 | void irq_move_irq(struct irq_data *data); |
383 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 384 | #else |
a439520f TG |
385 | static inline void irq_move_irq(struct irq_data *data) { } |
386 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 387 | #endif |
54d5d424 | 388 | |
1da177e4 | 389 | extern int no_irq_affinity; |
1da177e4 | 390 | |
6a6de9ef TG |
391 | /* |
392 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 393 | * callable via desc->handle_irq() |
6a6de9ef | 394 | */ |
ec701584 HH |
395 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
396 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
397 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 398 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
399 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
400 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
31d9d9b6 | 401 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 | 402 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
31b47cf7 | 403 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 404 | |
6a6de9ef | 405 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 406 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 407 | irqreturn_t action_ret); |
1da177e4 | 408 | |
a4633adc | 409 | |
6a6de9ef TG |
410 | /* Enable/disable irq debugging output: */ |
411 | extern int noirqdebug_setup(char *str); | |
412 | ||
413 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
414 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
415 | ||
f8b5473f | 416 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 417 | extern struct irq_chip no_irq_chip; |
f8b5473f | 418 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 419 | |
145fc655 | 420 | extern void |
3836ca08 | 421 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
422 | irq_flow_handler_t handle, const char *name); |
423 | ||
3836ca08 TG |
424 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
425 | irq_flow_handler_t handle) | |
426 | { | |
427 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
428 | } | |
429 | ||
31d9d9b6 MZ |
430 | extern int irq_set_percpu_devid(unsigned int irq); |
431 | ||
6a6de9ef | 432 | extern void |
3836ca08 | 433 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 434 | const char *name); |
1da177e4 | 435 | |
6a6de9ef | 436 | static inline void |
3836ca08 | 437 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 438 | { |
3836ca08 | 439 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
440 | } |
441 | ||
442 | /* | |
443 | * Set a highlevel chained flow handler for a given IRQ. | |
444 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 445 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
446 | */ |
447 | static inline void | |
3836ca08 | 448 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 449 | { |
3836ca08 | 450 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
451 | } |
452 | ||
44247184 TG |
453 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
454 | ||
455 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
456 | { | |
457 | irq_modify_status(irq, 0, set); | |
458 | } | |
459 | ||
460 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
461 | { | |
462 | irq_modify_status(irq, clr, 0); | |
463 | } | |
464 | ||
a0cd9ca2 | 465 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
466 | { |
467 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
468 | } | |
469 | ||
a0cd9ca2 | 470 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
471 | { |
472 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
473 | } | |
46f4f8f6 | 474 | |
7f1b1244 PM |
475 | static inline void irq_set_nothread(unsigned int irq) |
476 | { | |
477 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
478 | } | |
479 | ||
480 | static inline void irq_set_thread(unsigned int irq) | |
481 | { | |
482 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
483 | } | |
484 | ||
6f91a52d TG |
485 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
486 | { | |
487 | if (nest) | |
488 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
489 | else | |
490 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
491 | } | |
492 | ||
31d9d9b6 MZ |
493 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
494 | { | |
495 | irq_set_status_flags(irq, | |
496 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
497 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
498 | } | |
499 | ||
3a16d713 | 500 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 501 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
3a16d713 EB |
502 | extern int create_irq(void); |
503 | extern void destroy_irq(unsigned int irq); | |
504 | ||
b7b29338 TG |
505 | /* |
506 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and | |
507 | * irq_free_desc instead. | |
508 | */ | |
3a16d713 | 509 | extern void dynamic_irq_cleanup(unsigned int irq); |
b7b29338 TG |
510 | static inline void dynamic_irq_init(unsigned int irq) |
511 | { | |
512 | dynamic_irq_cleanup(irq); | |
513 | } | |
dd87eb3a | 514 | |
3a16d713 | 515 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
516 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
517 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
518 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
519 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
520 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
f303a6dd | 521 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 522 | |
a0cd9ca2 | 523 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
524 | { |
525 | struct irq_data *d = irq_get_irq_data(irq); | |
526 | return d ? d->chip : NULL; | |
527 | } | |
528 | ||
529 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
530 | { | |
531 | return d->chip; | |
532 | } | |
533 | ||
a0cd9ca2 | 534 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
535 | { |
536 | struct irq_data *d = irq_get_irq_data(irq); | |
537 | return d ? d->chip_data : NULL; | |
538 | } | |
539 | ||
540 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
541 | { | |
542 | return d->chip_data; | |
543 | } | |
544 | ||
a0cd9ca2 | 545 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
546 | { |
547 | struct irq_data *d = irq_get_irq_data(irq); | |
548 | return d ? d->handler_data : NULL; | |
549 | } | |
550 | ||
a0cd9ca2 | 551 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
552 | { |
553 | return d->handler_data; | |
554 | } | |
555 | ||
a0cd9ca2 | 556 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
557 | { |
558 | struct irq_data *d = irq_get_irq_data(irq); | |
559 | return d ? d->msi_desc : NULL; | |
560 | } | |
561 | ||
562 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
563 | { | |
564 | return d->msi_desc; | |
565 | } | |
566 | ||
b6873807 SAS |
567 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
568 | struct module *owner); | |
569 | ||
ec53cf23 PG |
570 | /* use macros to avoid needing export.h for THIS_MODULE */ |
571 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
572 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 573 | |
ec53cf23 PG |
574 | #define irq_alloc_desc(node) \ |
575 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 576 | |
ec53cf23 PG |
577 | #define irq_alloc_desc_at(at, node) \ |
578 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 579 | |
ec53cf23 PG |
580 | #define irq_alloc_desc_from(from, node) \ |
581 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 582 | |
ec53cf23 PG |
583 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
584 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); | |
1f5a5b87 TG |
585 | |
586 | static inline void irq_free_desc(unsigned int irq) | |
587 | { | |
588 | irq_free_descs(irq, 1); | |
589 | } | |
590 | ||
639bd12f PM |
591 | static inline int irq_reserve_irq(unsigned int irq) |
592 | { | |
593 | return irq_reserve_irqs(irq, 1); | |
594 | } | |
595 | ||
7d828062 TG |
596 | #ifndef irq_reg_writel |
597 | # define irq_reg_writel(val, addr) writel(val, addr) | |
598 | #endif | |
599 | #ifndef irq_reg_readl | |
600 | # define irq_reg_readl(addr) readl(addr) | |
601 | #endif | |
602 | ||
603 | /** | |
604 | * struct irq_chip_regs - register offsets for struct irq_gci | |
605 | * @enable: Enable register offset to reg_base | |
606 | * @disable: Disable register offset to reg_base | |
607 | * @mask: Mask register offset to reg_base | |
608 | * @ack: Ack register offset to reg_base | |
609 | * @eoi: Eoi register offset to reg_base | |
610 | * @type: Type configuration register offset to reg_base | |
611 | * @polarity: Polarity configuration register offset to reg_base | |
612 | */ | |
613 | struct irq_chip_regs { | |
614 | unsigned long enable; | |
615 | unsigned long disable; | |
616 | unsigned long mask; | |
617 | unsigned long ack; | |
618 | unsigned long eoi; | |
619 | unsigned long type; | |
620 | unsigned long polarity; | |
621 | }; | |
622 | ||
623 | /** | |
624 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
625 | * @chip: The real interrupt chip which provides the callbacks | |
626 | * @regs: Register offsets for this chip | |
627 | * @handler: Flow handler associated with this chip | |
628 | * @type: Chip can handle these flow types | |
629 | * | |
630 | * A irq_generic_chip can have several instances of irq_chip_type when | |
631 | * it requires different functions and register offsets for different | |
632 | * flow types. | |
633 | */ | |
634 | struct irq_chip_type { | |
635 | struct irq_chip chip; | |
636 | struct irq_chip_regs regs; | |
637 | irq_flow_handler_t handler; | |
638 | u32 type; | |
639 | }; | |
640 | ||
641 | /** | |
642 | * struct irq_chip_generic - Generic irq chip data structure | |
643 | * @lock: Lock to protect register and cache data access | |
644 | * @reg_base: Register base address (virtual) | |
645 | * @irq_base: Interrupt base nr for this chip | |
646 | * @irq_cnt: Number of interrupts handled by this chip | |
647 | * @mask_cache: Cached mask register | |
648 | * @type_cache: Cached type register | |
649 | * @polarity_cache: Cached polarity register | |
650 | * @wake_enabled: Interrupt can wakeup from suspend | |
651 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
652 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
653 | * @private: Private data for non generic chip callbacks | |
cfefd21e | 654 | * @list: List head for keeping track of instances |
7d828062 TG |
655 | * @chip_types: Array of interrupt irq_chip_types |
656 | * | |
657 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
658 | * implementations which can be associated to a particular irq line of | |
659 | * an irq_chip_generic instance. That allows to share and protect | |
660 | * state in an irq_chip_generic instance when we need to implement | |
661 | * different flow mechanisms (level/edge) for it. | |
662 | */ | |
663 | struct irq_chip_generic { | |
664 | raw_spinlock_t lock; | |
665 | void __iomem *reg_base; | |
666 | unsigned int irq_base; | |
667 | unsigned int irq_cnt; | |
668 | u32 mask_cache; | |
669 | u32 type_cache; | |
670 | u32 polarity_cache; | |
671 | u32 wake_enabled; | |
672 | u32 wake_active; | |
673 | unsigned int num_ct; | |
674 | void *private; | |
cfefd21e | 675 | struct list_head list; |
7d828062 TG |
676 | struct irq_chip_type chip_types[0]; |
677 | }; | |
678 | ||
679 | /** | |
680 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
681 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
682 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
683 | * irq chips which need to call irq_set_wake() on | |
684 | * the parent irq. Usually GPIO implementations | |
685 | */ | |
686 | enum irq_gc_flags { | |
687 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
688 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
689 | }; | |
690 | ||
691 | /* Generic chip callback functions */ | |
692 | void irq_gc_noop(struct irq_data *d); | |
693 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
694 | void irq_gc_mask_set_bit(struct irq_data *d); | |
695 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
696 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
697 | void irq_gc_ack_set_bit(struct irq_data *d); |
698 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
699 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
700 | void irq_gc_eoi(struct irq_data *d); | |
701 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
702 | ||
703 | /* Setup functions for irq_chip_generic */ | |
704 | struct irq_chip_generic * | |
705 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
706 | void __iomem *reg_base, irq_flow_handler_t handler); | |
707 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
708 | enum irq_gc_flags flags, unsigned int clr, | |
709 | unsigned int set); | |
710 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
711 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
712 | unsigned int clr, unsigned int set); | |
7d828062 TG |
713 | |
714 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) | |
715 | { | |
716 | return container_of(d->chip, struct irq_chip_type, chip); | |
717 | } | |
718 | ||
719 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
720 | ||
721 | #ifdef CONFIG_SMP | |
722 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
723 | { | |
724 | raw_spin_lock(&gc->lock); | |
725 | } | |
726 | ||
727 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
728 | { | |
729 | raw_spin_unlock(&gc->lock); | |
730 | } | |
731 | #else | |
732 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
733 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
734 | #endif | |
735 | ||
6a6de9ef | 736 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 737 | |
06fcb0c6 | 738 | #endif /* !CONFIG_S390 */ |
1da177e4 | 739 | |
06fcb0c6 | 740 | #endif /* _LINUX_IRQ_H */ |