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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
021f6537 MZ |
2 | /* |
3 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
021f6537 MZ |
5 | */ |
6 | #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H | |
7 | #define __LINUX_IRQCHIP_ARM_GIC_V3_H | |
8 | ||
9 | /* | |
10 | * Distributor registers. We assume we're running non-secure, with ARE | |
11 | * being set. Secure-only and non-ARE registers are not described. | |
12 | */ | |
13 | #define GICD_CTLR 0x0000 | |
14 | #define GICD_TYPER 0x0004 | |
15 | #define GICD_IIDR 0x0008 | |
f2d83409 | 16 | #define GICD_TYPER2 0x000C |
021f6537 MZ |
17 | #define GICD_STATUSR 0x0010 |
18 | #define GICD_SETSPI_NSR 0x0040 | |
19 | #define GICD_CLRSPI_NSR 0x0048 | |
20 | #define GICD_SETSPI_SR 0x0050 | |
21 | #define GICD_CLRSPI_SR 0x0058 | |
22 | #define GICD_SEIR 0x0068 | |
a0675c25 | 23 | #define GICD_IGROUPR 0x0080 |
021f6537 MZ |
24 | #define GICD_ISENABLER 0x0100 |
25 | #define GICD_ICENABLER 0x0180 | |
26 | #define GICD_ISPENDR 0x0200 | |
27 | #define GICD_ICPENDR 0x0280 | |
28 | #define GICD_ISACTIVER 0x0300 | |
29 | #define GICD_ICACTIVER 0x0380 | |
30 | #define GICD_IPRIORITYR 0x0400 | |
31 | #define GICD_ICFGR 0x0C00 | |
a0675c25 AP |
32 | #define GICD_IGRPMODR 0x0D00 |
33 | #define GICD_NSACR 0x0E00 | |
211bddd2 MZ |
34 | #define GICD_IGROUPRnE 0x1000 |
35 | #define GICD_ISENABLERnE 0x1200 | |
36 | #define GICD_ICENABLERnE 0x1400 | |
37 | #define GICD_ISPENDRnE 0x1600 | |
38 | #define GICD_ICPENDRnE 0x1800 | |
39 | #define GICD_ISACTIVERnE 0x1A00 | |
40 | #define GICD_ICACTIVERnE 0x1C00 | |
41 | #define GICD_IPRIORITYRnE 0x2000 | |
42 | #define GICD_ICFGRnE 0x3000 | |
021f6537 | 43 | #define GICD_IROUTER 0x6000 |
211bddd2 | 44 | #define GICD_IROUTERnE 0x8000 |
a0675c25 | 45 | #define GICD_IDREGS 0xFFD0 |
021f6537 MZ |
46 | #define GICD_PIDR2 0xFFE8 |
47 | ||
211bddd2 MZ |
48 | #define ESPI_BASE_INTID 4096 |
49 | ||
a0675c25 AP |
50 | /* |
51 | * Those registers are actually from GICv2, but the spec demands that they | |
52 | * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). | |
53 | */ | |
54 | #define GICD_ITARGETSR 0x0800 | |
55 | #define GICD_SGIR 0x0F00 | |
56 | #define GICD_CPENDSGIR 0x0F10 | |
57 | #define GICD_SPENDSGIR 0x0F20 | |
58 | ||
021f6537 | 59 | #define GICD_CTLR_RWP (1U << 31) |
0b04758b | 60 | #define GICD_CTLR_nASSGIreq (1U << 8) |
a0675c25 | 61 | #define GICD_CTLR_DS (1U << 6) |
021f6537 MZ |
62 | #define GICD_CTLR_ARE_NS (1U << 4) |
63 | #define GICD_CTLR_ENABLE_G1A (1U << 1) | |
64 | #define GICD_CTLR_ENABLE_G1 (1U << 0) | |
65 | ||
a2dca217 CD |
66 | #define GICD_IIDR_IMPLEMENTER_SHIFT 0 |
67 | #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) | |
68 | #define GICD_IIDR_REVISION_SHIFT 12 | |
69 | #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) | |
70 | #define GICD_IIDR_VARIANT_SHIFT 16 | |
71 | #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) | |
72 | #define GICD_IIDR_PRODUCT_ID_SHIFT 24 | |
73 | #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) | |
74 | ||
75 | ||
a0675c25 AP |
76 | /* |
77 | * In systems with a single security state (what we emulate in KVM) | |
78 | * the meaning of the interrupt group enable bits is slightly different | |
79 | */ | |
80 | #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) | |
81 | #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) | |
82 | ||
eda0d04a | 83 | #define GICD_TYPER_RSS (1U << 26) |
a0675c25 AP |
84 | #define GICD_TYPER_LPIS (1U << 17) |
85 | #define GICD_TYPER_MBIS (1U << 16) | |
211bddd2 | 86 | #define GICD_TYPER_ESPI (1U << 8) |
a0675c25 | 87 | |
f5c1434c | 88 | #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) |
12b2905a | 89 | #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) |
211bddd2 MZ |
90 | #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) |
91 | #define GICD_TYPER_ESPIS(typer) \ | |
92 | (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) | |
f5c1434c | 93 | |
0b04758b | 94 | #define GICD_TYPER2_nASSGIcap (1U << 8) |
f2d83409 MZ |
95 | #define GICD_TYPER2_VIL (1U << 7) |
96 | #define GICD_TYPER2_VID GENMASK(4, 0) | |
97 | ||
021f6537 MZ |
98 | #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) |
99 | #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) | |
100 | ||
101 | #define GIC_PIDR2_ARCH_MASK 0xf0 | |
102 | #define GIC_PIDR2_ARCH_GICv3 0x30 | |
103 | #define GIC_PIDR2_ARCH_GICv4 0x40 | |
104 | ||
a0675c25 AP |
105 | #define GIC_V3_DIST_SIZE 0x10000 |
106 | ||
5e516846 MZ |
107 | #define GIC_PAGE_SIZE_4K 0ULL |
108 | #define GIC_PAGE_SIZE_16K 1ULL | |
109 | #define GIC_PAGE_SIZE_64K 2ULL | |
110 | #define GIC_PAGE_SIZE_MASK 3ULL | |
111 | ||
021f6537 MZ |
112 | /* |
113 | * Re-Distributor registers, offsets from RD_base | |
114 | */ | |
115 | #define GICR_CTLR GICD_CTLR | |
116 | #define GICR_IIDR 0x0004 | |
117 | #define GICR_TYPER 0x0008 | |
118 | #define GICR_STATUSR GICD_STATUSR | |
119 | #define GICR_WAKER 0x0014 | |
120 | #define GICR_SETLPIR 0x0040 | |
121 | #define GICR_CLRLPIR 0x0048 | |
122 | #define GICR_SEIR GICD_SEIR | |
123 | #define GICR_PROPBASER 0x0070 | |
124 | #define GICR_PENDBASER 0x0078 | |
125 | #define GICR_INVLPIR 0x00A0 | |
126 | #define GICR_INVALLR 0x00B0 | |
127 | #define GICR_SYNCR 0x00C0 | |
128 | #define GICR_MOVLPIR 0x0100 | |
129 | #define GICR_MOVALLR 0x0110 | |
a0675c25 | 130 | #define GICR_IDREGS GICD_IDREGS |
021f6537 MZ |
131 | #define GICR_PIDR2 GICD_PIDR2 |
132 | ||
cc2d3216 | 133 | #define GICR_CTLR_ENABLE_LPIS (1UL << 0) |
6eb486b6 | 134 | #define GICR_CTLR_RWP (1UL << 3) |
cc2d3216 MZ |
135 | |
136 | #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) | |
137 | ||
5f51f803 MZ |
138 | #define EPPI_BASE_INTID 1056 |
139 | ||
140 | #define GICR_TYPER_NR_PPIS(r) \ | |
141 | ({ \ | |
142 | unsigned int __ppinum = ((r) >> 27) & 0x1f; \ | |
143 | unsigned int __nr_ppis = 16; \ | |
144 | if (__ppinum == 1 || __ppinum == 2) \ | |
145 | __nr_ppis += __ppinum * 32; \ | |
146 | \ | |
147 | __nr_ppis; \ | |
148 | }) | |
149 | ||
021f6537 MZ |
150 | #define GICR_WAKER_ProcessorSleep (1U << 1) |
151 | #define GICR_WAKER_ChildrenAsleep (1U << 2) | |
152 | ||
645b9e49 AP |
153 | #define GIC_BASER_CACHE_nCnB 0ULL |
154 | #define GIC_BASER_CACHE_SameAsInner 0ULL | |
155 | #define GIC_BASER_CACHE_nC 1ULL | |
156 | #define GIC_BASER_CACHE_RaWt 2ULL | |
157 | #define GIC_BASER_CACHE_RaWb 3ULL | |
158 | #define GIC_BASER_CACHE_WaWt 4ULL | |
159 | #define GIC_BASER_CACHE_WaWb 5ULL | |
160 | #define GIC_BASER_CACHE_RaWaWt 6ULL | |
161 | #define GIC_BASER_CACHE_RaWaWb 7ULL | |
162 | #define GIC_BASER_CACHE_MASK 7ULL | |
163 | #define GIC_BASER_NonShareable 0ULL | |
164 | #define GIC_BASER_InnerShareable 1ULL | |
165 | #define GIC_BASER_OuterShareable 2ULL | |
166 | #define GIC_BASER_SHAREABILITY_MASK 3ULL | |
167 | ||
168 | #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ | |
169 | (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) | |
170 | ||
171 | #define GIC_BASER_SHAREABILITY(reg, type) \ | |
172 | (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) | |
173 | ||
71afe470 EA |
174 | /* encode a size field of width @w containing @n - 1 units */ |
175 | #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) | |
176 | ||
645b9e49 AP |
177 | #define GICR_PROPBASER_SHAREABILITY_SHIFT (10) |
178 | #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) | |
179 | #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) | |
180 | #define GICR_PROPBASER_SHAREABILITY_MASK \ | |
181 | GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) | |
182 | #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ | |
183 | GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) | |
184 | #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ | |
185 | GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) | |
186 | #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK | |
187 | ||
188 | #define GICR_PROPBASER_InnerShareable \ | |
189 | GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) | |
8c828a53 MZ |
190 | |
191 | #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB) | |
192 | #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC) | |
193 | #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) | |
0f29456d | 194 | #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) |
8c828a53 MZ |
195 | #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt) |
196 | #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb) | |
197 | #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt) | |
198 | #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb) | |
199 | ||
645b9e49 | 200 | #define GICR_PROPBASER_IDBITS_MASK (0x1f) |
44de9d68 EA |
201 | #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) |
202 | #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) | |
645b9e49 AP |
203 | |
204 | #define GICR_PENDBASER_SHAREABILITY_SHIFT (10) | |
205 | #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) | |
206 | #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) | |
207 | #define GICR_PENDBASER_SHAREABILITY_MASK \ | |
208 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) | |
209 | #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ | |
210 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) | |
211 | #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ | |
212 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) | |
213 | #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK | |
214 | ||
215 | #define GICR_PENDBASER_InnerShareable \ | |
216 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) | |
8c828a53 MZ |
217 | |
218 | #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB) | |
219 | #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC) | |
220 | #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) | |
0f29456d | 221 | #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) |
8c828a53 MZ |
222 | #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt) |
223 | #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb) | |
224 | #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt) | |
225 | #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb) | |
226 | ||
645b9e49 | 227 | #define GICR_PENDBASER_PTZ BIT_ULL(62) |
4ad3e363 | 228 | |
021f6537 MZ |
229 | /* |
230 | * Re-Distributor registers, offsets from SGI_base | |
231 | */ | |
a0675c25 | 232 | #define GICR_IGROUPR0 GICD_IGROUPR |
021f6537 MZ |
233 | #define GICR_ISENABLER0 GICD_ISENABLER |
234 | #define GICR_ICENABLER0 GICD_ICENABLER | |
235 | #define GICR_ISPENDR0 GICD_ISPENDR | |
236 | #define GICR_ICPENDR0 GICD_ICPENDR | |
237 | #define GICR_ISACTIVER0 GICD_ISACTIVER | |
238 | #define GICR_ICACTIVER0 GICD_ICACTIVER | |
239 | #define GICR_IPRIORITYR0 GICD_IPRIORITYR | |
240 | #define GICR_ICFGR0 GICD_ICFGR | |
a0675c25 AP |
241 | #define GICR_IGRPMODR0 GICD_IGRPMODR |
242 | #define GICR_NSACR GICD_NSACR | |
021f6537 | 243 | |
cc2d3216 | 244 | #define GICR_TYPER_PLPIS (1U << 0) |
021f6537 | 245 | #define GICR_TYPER_VLPIS (1U << 1) |
96806229 | 246 | #define GICR_TYPER_DIRTY (1U << 2) |
0edc23ea | 247 | #define GICR_TYPER_DirectLPIS (1U << 3) |
021f6537 | 248 | #define GICR_TYPER_LAST (1U << 4) |
b25319d2 | 249 | #define GICR_TYPER_RVPEID (1U << 7) |
5e516846 MZ |
250 | #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) |
251 | #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) | |
021f6537 | 252 | |
f4a81f5a | 253 | #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0) |
b4a4bd0f MZ |
254 | #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) |
255 | #define GICR_INVLPIR_V GENMASK_ULL(63, 63) | |
256 | ||
257 | #define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID | |
258 | #define GICR_INVALLR_V GICR_INVLPIR_V | |
259 | ||
a0675c25 AP |
260 | #define GIC_V3_REDIST_SIZE 0x20000 |
261 | ||
cc2d3216 MZ |
262 | #define LPI_PROP_GROUP1 (1 << 1) |
263 | #define LPI_PROP_ENABLED (1 << 0) | |
264 | ||
e643d803 MZ |
265 | /* |
266 | * Re-Distributor registers, offsets from VLPI_base | |
267 | */ | |
268 | #define GICR_VPROPBASER 0x0070 | |
269 | ||
270 | #define GICR_VPROPBASER_IDBITS_MASK 0x1f | |
271 | ||
272 | #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10) | |
273 | #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7) | |
274 | #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56) | |
275 | ||
276 | #define GICR_VPROPBASER_SHAREABILITY_MASK \ | |
277 | GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK) | |
278 | #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \ | |
279 | GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK) | |
280 | #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \ | |
281 | GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK) | |
282 | #define GICR_VPROPBASER_CACHEABILITY_MASK \ | |
283 | GICR_VPROPBASER_INNER_CACHEABILITY_MASK | |
284 | ||
285 | #define GICR_VPROPBASER_InnerShareable \ | |
286 | GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable) | |
287 | ||
288 | #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB) | |
289 | #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC) | |
290 | #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt) | |
0f29456d | 291 | #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb) |
e643d803 MZ |
292 | #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt) |
293 | #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb) | |
294 | #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt) | |
295 | #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb) | |
296 | ||
5e516846 MZ |
297 | /* |
298 | * GICv4.1 VPROPBASER reinvention. A subtle mix between the old | |
299 | * VPROPBASER and ITS_BASER. Just not quite any of the two. | |
300 | */ | |
301 | #define GICR_VPROPBASER_4_1_VALID (1ULL << 63) | |
302 | #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59) | |
303 | #define GICR_VPROPBASER_4_1_INDIRECT (1ULL << 55) | |
304 | #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53) | |
305 | #define GICR_VPROPBASER_4_1_Z (1ULL << 52) | |
306 | #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12) | |
307 | #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0) | |
308 | ||
e643d803 MZ |
309 | #define GICR_VPENDBASER 0x0078 |
310 | ||
311 | #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10) | |
312 | #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7) | |
313 | #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56) | |
314 | #define GICR_VPENDBASER_SHAREABILITY_MASK \ | |
315 | GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK) | |
316 | #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \ | |
317 | GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK) | |
318 | #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \ | |
319 | GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK) | |
320 | #define GICR_VPENDBASER_CACHEABILITY_MASK \ | |
321 | GICR_VPENDBASER_INNER_CACHEABILITY_MASK | |
322 | ||
323 | #define GICR_VPENDBASER_NonShareable \ | |
324 | GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable) | |
325 | ||
b2cb11f4 HG |
326 | #define GICR_VPENDBASER_InnerShareable \ |
327 | GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable) | |
328 | ||
e643d803 MZ |
329 | #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB) |
330 | #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC) | |
331 | #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt) | |
0f29456d | 332 | #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb) |
e643d803 MZ |
333 | #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt) |
334 | #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb) | |
335 | #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt) | |
336 | #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb) | |
337 | ||
3ca63f36 MZ |
338 | #define GICR_VPENDBASER_Dirty (1ULL << 60) |
339 | #define GICR_VPENDBASER_PendingLast (1ULL << 61) | |
340 | #define GICR_VPENDBASER_IDAI (1ULL << 62) | |
341 | #define GICR_VPENDBASER_Valid (1ULL << 63) | |
342 | ||
91bf6395 MZ |
343 | /* |
344 | * GICv4.1 VPENDBASER, used for VPE residency. On top of these fields, | |
345 | * also use the above Valid, PendingLast and Dirty. | |
346 | */ | |
347 | #define GICR_VPENDBASER_4_1_DB (1ULL << 62) | |
348 | #define GICR_VPENDBASER_4_1_VGRP0EN (1ULL << 59) | |
349 | #define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58) | |
350 | #define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0) | |
351 | ||
7017ff0e MZ |
352 | #define GICR_VSGIR 0x0080 |
353 | ||
354 | #define GICR_VSGIR_VPEID GENMASK(15, 0) | |
355 | ||
356 | #define GICR_VSGIPENDR 0x0088 | |
357 | ||
358 | #define GICR_VSGIPENDR_BUSY (1U << 31) | |
359 | #define GICR_VSGIPENDR_PENDING GENMASK(15, 0) | |
360 | ||
cc2d3216 MZ |
361 | /* |
362 | * ITS registers, offsets from ITS_base | |
363 | */ | |
364 | #define GITS_CTLR 0x0000 | |
365 | #define GITS_IIDR 0x0004 | |
366 | #define GITS_TYPER 0x0008 | |
5e516846 | 367 | #define GITS_MPIDR 0x0018 |
cc2d3216 MZ |
368 | #define GITS_CBASER 0x0080 |
369 | #define GITS_CWRITER 0x0088 | |
370 | #define GITS_CREADR 0x0090 | |
371 | #define GITS_BASER 0x0100 | |
645b9e49 AP |
372 | #define GITS_IDREGS_BASE 0xffd0 |
373 | #define GITS_PIDR0 0xffe0 | |
374 | #define GITS_PIDR1 0xffe4 | |
cc2d3216 | 375 | #define GITS_PIDR2 GICR_PIDR2 |
645b9e49 AP |
376 | #define GITS_PIDR4 0xffd0 |
377 | #define GITS_CIDR0 0xfff0 | |
378 | #define GITS_CIDR1 0xfff4 | |
379 | #define GITS_CIDR2 0xfff8 | |
380 | #define GITS_CIDR3 0xfffc | |
cc2d3216 MZ |
381 | |
382 | #define GITS_TRANSLATER 0x10040 | |
383 | ||
7017ff0e MZ |
384 | #define GITS_SGIR 0x20020 |
385 | ||
386 | #define GITS_SGIR_VPEID GENMASK_ULL(47, 32) | |
387 | #define GITS_SGIR_VINTID GENMASK_ULL(3, 0) | |
388 | ||
7cb99116 | 389 | #define GITS_CTLR_ENABLE (1U << 0) |
d51c4b4d | 390 | #define GITS_CTLR_ImDe (1U << 1) |
3dfa576b MZ |
391 | #define GITS_CTLR_ITS_NUMBER_SHIFT 4 |
392 | #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) | |
7cb99116 YW |
393 | #define GITS_CTLR_QUIESCENT (1U << 31) |
394 | ||
645b9e49 | 395 | #define GITS_TYPER_PLPIS (1UL << 0) |
3dfa576b | 396 | #define GITS_TYPER_VLPIS (1UL << 1) |
71afe470 | 397 | #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 |
ffedbf0c | 398 | #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) |
645b9e49 | 399 | #define GITS_TYPER_IDBITS_SHIFT 8 |
f54b97ed | 400 | #define GITS_TYPER_DEVBITS_SHIFT 13 |
576a8342 | 401 | #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13) |
cc2d3216 | 402 | #define GITS_TYPER_PTA (1UL << 19) |
dba0bc7b DB |
403 | #define GITS_TYPER_HCC_SHIFT 24 |
404 | #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) | |
3dfa576b | 405 | #define GITS_TYPER_VMOVP (1ULL << 37) |
5e516846 MZ |
406 | #define GITS_TYPER_VMAPP (1ULL << 40) |
407 | #define GITS_TYPER_SVPET GENMASK_ULL(42, 41) | |
645b9e49 | 408 | |
ab01c6bd EA |
409 | #define GITS_IIDR_REV_SHIFT 12 |
410 | #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT) | |
411 | #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf) | |
412 | #define GITS_IIDR_PRODUCTID_SHIFT 24 | |
413 | ||
b11283eb | 414 | #define GITS_CBASER_VALID (1ULL << 63) |
645b9e49 AP |
415 | #define GITS_CBASER_SHAREABILITY_SHIFT (10) |
416 | #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) | |
417 | #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) | |
418 | #define GITS_CBASER_SHAREABILITY_MASK \ | |
419 | GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) | |
420 | #define GITS_CBASER_INNER_CACHEABILITY_MASK \ | |
421 | GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) | |
422 | #define GITS_CBASER_OUTER_CACHEABILITY_MASK \ | |
423 | GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) | |
424 | #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK | |
425 | ||
426 | #define GITS_CBASER_InnerShareable \ | |
427 | GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) | |
8c828a53 MZ |
428 | |
429 | #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) | |
430 | #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) | |
431 | #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) | |
0f29456d | 432 | #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb) |
8c828a53 MZ |
433 | #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) |
434 | #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) | |
435 | #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) | |
436 | #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) | |
cc2d3216 | 437 | |
8ad50c89 KM |
438 | #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12)) |
439 | ||
cc2d3216 MZ |
440 | #define GITS_BASER_NR_REGS 8 |
441 | ||
b11283eb | 442 | #define GITS_BASER_VALID (1ULL << 63) |
645b9e49 | 443 | #define GITS_BASER_INDIRECT (1ULL << 62) |
8c828a53 | 444 | |
645b9e49 AP |
445 | #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) |
446 | #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) | |
447 | #define GITS_BASER_INNER_CACHEABILITY_MASK \ | |
448 | GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) | |
8c828a53 | 449 | #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK |
645b9e49 AP |
450 | #define GITS_BASER_OUTER_CACHEABILITY_MASK \ |
451 | GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) | |
452 | #define GITS_BASER_SHAREABILITY_MASK \ | |
453 | GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK) | |
454 | ||
8c828a53 MZ |
455 | #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) |
456 | #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC) | |
457 | #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) | |
0f29456d | 458 | #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) |
8c828a53 MZ |
459 | #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt) |
460 | #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb) | |
461 | #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt) | |
462 | #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb) | |
463 | ||
645b9e49 | 464 | #define GITS_BASER_TYPE_SHIFT (56) |
cc2d3216 | 465 | #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) |
645b9e49 | 466 | #define GITS_BASER_ENTRY_SIZE_SHIFT (48) |
9224eb77 | 467 | #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) |
71afe470 | 468 | #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) |
30ae9610 SD |
469 | #define GITS_BASER_PHYS_52_to_48(phys) \ |
470 | (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) | |
8ad50c89 KM |
471 | #define GITS_BASER_ADDR_48_to_52(baser) \ |
472 | (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) | |
473 | ||
cc2d3216 | 474 | #define GITS_BASER_SHAREABILITY_SHIFT (10) |
645b9e49 AP |
475 | #define GITS_BASER_InnerShareable \ |
476 | GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | |
cc2d3216 | 477 | #define GITS_BASER_PAGE_SIZE_SHIFT (8) |
5e516846 MZ |
478 | #define __GITS_BASER_PSZ(sz) (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT) |
479 | #define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K) | |
480 | #define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K) | |
481 | #define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K) | |
482 | #define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK) | |
30f21363 | 483 | #define GITS_BASER_PAGES_MAX 256 |
9347359a | 484 | #define GITS_BASER_PAGES_SHIFT (0) |
645b9e49 | 485 | #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) |
cc2d3216 MZ |
486 | |
487 | #define GITS_BASER_TYPE_NONE 0 | |
488 | #define GITS_BASER_TYPE_DEVICE 1 | |
489 | #define GITS_BASER_TYPE_VCPU 2 | |
4f46de9d | 490 | #define GITS_BASER_TYPE_RESERVED3 3 |
cc2d3216 MZ |
491 | #define GITS_BASER_TYPE_COLLECTION 4 |
492 | #define GITS_BASER_TYPE_RESERVED5 5 | |
493 | #define GITS_BASER_TYPE_RESERVED6 6 | |
494 | #define GITS_BASER_TYPE_RESERVED7 7 | |
495 | ||
3faf24ea SD |
496 | #define GITS_LVL1_ENTRY_SIZE (8UL) |
497 | ||
cc2d3216 MZ |
498 | /* |
499 | * ITS commands | |
500 | */ | |
501 | #define GITS_CMD_MAPD 0x08 | |
502 | #define GITS_CMD_MAPC 0x09 | |
645b9e49 | 503 | #define GITS_CMD_MAPTI 0x0a |
645b9e49 | 504 | #define GITS_CMD_MAPI 0x0b |
cc2d3216 MZ |
505 | #define GITS_CMD_MOVI 0x01 |
506 | #define GITS_CMD_DISCARD 0x0f | |
507 | #define GITS_CMD_INV 0x0c | |
508 | #define GITS_CMD_MOVALL 0x0e | |
509 | #define GITS_CMD_INVALL 0x0d | |
510 | #define GITS_CMD_INT 0x03 | |
511 | #define GITS_CMD_CLEAR 0x04 | |
512 | #define GITS_CMD_SYNC 0x05 | |
513 | ||
d7276b80 MZ |
514 | /* |
515 | * GICv4 ITS specific commands | |
516 | */ | |
517 | #define GITS_CMD_GICv4(x) ((x) | 0x20) | |
518 | #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL) | |
519 | #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC) | |
520 | #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI) | |
521 | #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI) | |
522 | #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC) | |
e252cf8a | 523 | /* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */ |
d7276b80 | 524 | #define GITS_CMD_VMOVP GITS_CMD_GICv4(2) |
e252cf8a | 525 | #define GITS_CMD_VSGI GITS_CMD_GICv4(3) |
d97c97ba | 526 | #define GITS_CMD_INVDB GITS_CMD_GICv4(0xe) |
d7276b80 | 527 | |
645b9e49 AP |
528 | /* |
529 | * ITS error numbers | |
530 | */ | |
531 | #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 | |
532 | #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 | |
fd837b08 | 533 | #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307 |
645b9e49 AP |
534 | #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 |
535 | #define E_ITS_MAPD_DEVICE_OOR 0x010801 | |
0d44cdb6 | 536 | #define E_ITS_MAPD_ITTSIZE_OOR 0x010802 |
645b9e49 AP |
537 | #define E_ITS_MAPC_PROCNUM_OOR 0x010902 |
538 | #define E_ITS_MAPC_COLLECTION_OOR 0x010903 | |
539 | #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 | |
0d44cdb6 | 540 | #define E_ITS_MAPTI_ID_OOR 0x010a05 |
645b9e49 AP |
541 | #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 |
542 | #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 | |
543 | #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 | |
544 | #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 | |
545 | #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 | |
546 | ||
021f6537 MZ |
547 | /* |
548 | * CPU interface registers | |
549 | */ | |
5c341537 VK |
550 | #define ICC_CTLR_EL1_EOImode_SHIFT (1) |
551 | #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) | |
552 | #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) | |
553 | #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT) | |
554 | #define ICC_CTLR_EL1_CBPR_SHIFT 0 | |
555 | #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) | |
f2266504 MZ |
556 | #define ICC_CTLR_EL1_PMHE_SHIFT 6 |
557 | #define ICC_CTLR_EL1_PMHE_MASK (1 << ICC_CTLR_EL1_PMHE_SHIFT) | |
5c341537 VK |
558 | #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8 |
559 | #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) | |
560 | #define ICC_CTLR_EL1_ID_BITS_SHIFT 11 | |
561 | #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT) | |
562 | #define ICC_CTLR_EL1_SEIS_SHIFT 14 | |
563 | #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT) | |
564 | #define ICC_CTLR_EL1_A3V_SHIFT 15 | |
565 | #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) | |
eda0d04a | 566 | #define ICC_CTLR_EL1_RSS (0x1 << 18) |
ad5a78d3 | 567 | #define ICC_CTLR_EL1_ExtRange (0x1 << 19) |
5c341537 VK |
568 | #define ICC_PMR_EL1_SHIFT 0 |
569 | #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) | |
570 | #define ICC_BPR0_EL1_SHIFT 0 | |
571 | #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT) | |
572 | #define ICC_BPR1_EL1_SHIFT 0 | |
573 | #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT) | |
574 | #define ICC_IGRPEN0_EL1_SHIFT 0 | |
575 | #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT) | |
576 | #define ICC_IGRPEN1_EL1_SHIFT 0 | |
577 | #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT) | |
4dfc0505 MZ |
578 | #define ICC_SRE_EL1_DIB (1U << 2) |
579 | #define ICC_SRE_EL1_DFB (1U << 1) | |
021f6537 MZ |
580 | #define ICC_SRE_EL1_SRE (1U << 0) |
581 | ||
582 | /* | |
583 | * Hypervisor interface registers (SRE only) | |
584 | */ | |
f6c86a41 JPB |
585 | #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) |
586 | ||
587 | #define ICH_LR_EOI (1ULL << 41) | |
588 | #define ICH_LR_GROUP (1ULL << 60) | |
589 | #define ICH_LR_HW (1ULL << 61) | |
590 | #define ICH_LR_STATE (3ULL << 62) | |
591 | #define ICH_LR_PENDING_BIT (1ULL << 62) | |
592 | #define ICH_LR_ACTIVE_BIT (1ULL << 63) | |
fb182cf8 | 593 | #define ICH_LR_PHYS_ID_SHIFT 32 |
f6c86a41 | 594 | #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) |
59529f69 | 595 | #define ICH_LR_PRIORITY_SHIFT 48 |
132a324a | 596 | #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) |
021f6537 | 597 | |
44bfc42e AP |
598 | /* These are for GICv2 emulation only */ |
599 | #define GICH_LR_VIRTUALID (0x3ffUL << 0) | |
600 | #define GICH_LR_PHYSID_CPUID_SHIFT (10) | |
601 | #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) | |
021f6537 MZ |
602 | |
603 | #define ICH_MISR_EOI (1 << 0) | |
604 | #define ICH_MISR_U (1 << 1) | |
605 | ||
606 | #define ICH_HCR_EN (1 << 0) | |
607 | #define ICH_HCR_UIE (1 << 1) | |
16ca6a60 | 608 | #define ICH_HCR_NPIE (1 << 3) |
ff89511e | 609 | #define ICH_HCR_TC (1 << 10) |
abf55766 | 610 | #define ICH_HCR_TALL0 (1 << 11) |
9c7bfc28 | 611 | #define ICH_HCR_TALL1 (1 << 12) |
b6f49035 MZ |
612 | #define ICH_HCR_EOIcount_SHIFT 27 |
613 | #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) | |
021f6537 | 614 | |
28232a43 CD |
615 | #define ICH_VMCR_ACK_CTL_SHIFT 2 |
616 | #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) | |
617 | #define ICH_VMCR_FIQ_EN_SHIFT 3 | |
618 | #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) | |
5c341537 VK |
619 | #define ICH_VMCR_CBPR_SHIFT 4 |
620 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) | |
621 | #define ICH_VMCR_EOIM_SHIFT 9 | |
622 | #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) | |
021f6537 MZ |
623 | #define ICH_VMCR_BPR1_SHIFT 18 |
624 | #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) | |
625 | #define ICH_VMCR_BPR0_SHIFT 21 | |
626 | #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) | |
627 | #define ICH_VMCR_PMR_SHIFT 24 | |
628 | #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) | |
5c341537 VK |
629 | #define ICH_VMCR_ENG0_SHIFT 0 |
630 | #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) | |
631 | #define ICH_VMCR_ENG1_SHIFT 1 | |
632 | #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) | |
633 | ||
634 | #define ICH_VTR_PRI_BITS_SHIFT 29 | |
635 | #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) | |
636 | #define ICH_VTR_ID_BITS_SHIFT 23 | |
637 | #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) | |
638 | #define ICH_VTR_SEIS_SHIFT 22 | |
639 | #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) | |
640 | #define ICH_VTR_A3V_SHIFT 21 | |
641 | #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) | |
021f6537 | 642 | |
021f6537 MZ |
643 | #define ICC_IAR1_EL1_SPURIOUS 0x3ff |
644 | ||
021f6537 MZ |
645 | #define ICC_SRE_EL2_SRE (1 << 0) |
646 | #define ICC_SRE_EL2_ENABLE (1 << 3) | |
647 | ||
7e580278 AP |
648 | #define ICC_SGI1R_TARGET_LIST_SHIFT 0 |
649 | #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) | |
650 | #define ICC_SGI1R_AFFINITY_1_SHIFT 16 | |
651 | #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) | |
652 | #define ICC_SGI1R_SGI_ID_SHIFT 24 | |
dd5f1b04 | 653 | #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) |
7e580278 | 654 | #define ICC_SGI1R_AFFINITY_2_SHIFT 32 |
fab0cdc3 | 655 | #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) |
7e580278 | 656 | #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 |
eda0d04a SD |
657 | #define ICC_SGI1R_RS_SHIFT 44 |
658 | #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT) | |
7e580278 | 659 | #define ICC_SGI1R_AFFINITY_3_SHIFT 48 |
fab0cdc3 | 660 | #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) |
7e580278 | 661 | |
7936e914 | 662 | #include <asm/arch_gicv3.h> |
021f6537 MZ |
663 | |
664 | #ifndef __ASSEMBLY__ | |
665 | ||
b48ac83d MZ |
666 | /* |
667 | * We need a value to serve as a irq-type for LPIs. Choose one that will | |
668 | * hopefully pique the interest of the reviewer. | |
669 | */ | |
670 | #define GIC_IRQ_TYPE_LPI 0xa110c8ed | |
671 | ||
f5c1434c MZ |
672 | struct rdists { |
673 | struct { | |
9058a4e9 | 674 | raw_spinlock_t rd_lock; |
f5c1434c MZ |
675 | void __iomem *rd_base; |
676 | struct page *pend_page; | |
677 | phys_addr_t phys_base; | |
11e37d35 | 678 | bool lpi_enabled; |
5e516846 | 679 | cpumask_t *vpe_table_mask; |
8b718d40 | 680 | void *vpe_l1_base; |
f5c1434c | 681 | } __percpu *rdist; |
e1a2e201 MZ |
682 | phys_addr_t prop_table_pa; |
683 | void *prop_table_va; | |
f5c1434c | 684 | u64 flags; |
a4f9edb2 | 685 | u32 gicd_typer; |
f2d83409 | 686 | u32 gicd_typer2; |
0edc23ea | 687 | bool has_vlpis; |
b25319d2 | 688 | bool has_rvpeid; |
0edc23ea | 689 | bool has_direct_lpi; |
96806229 | 690 | bool has_vpend_valid_dirty; |
f5c1434c MZ |
691 | }; |
692 | ||
7936e914 | 693 | struct irq_domain; |
db40f0a7 | 694 | struct fwnode_handle; |
7936e914 | 695 | int its_cpu_init(void); |
db40f0a7 | 696 | int its_init(struct fwnode_handle *handle, struct rdists *rdists, |
7936e914 | 697 | struct irq_domain *domain); |
50528752 | 698 | int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent); |
0b6a3da9 | 699 | |
7cabd008 MZ |
700 | static inline bool gic_enable_sre(void) |
701 | { | |
7936e914 | 702 | u32 val; |
7cabd008 | 703 | |
7936e914 | 704 | val = gic_read_sre(); |
7cabd008 MZ |
705 | if (val & ICC_SRE_EL1_SRE) |
706 | return true; | |
707 | ||
708 | val |= ICC_SRE_EL1_SRE; | |
7936e914 JPB |
709 | gic_write_sre(val); |
710 | val = gic_read_sre(); | |
7cabd008 MZ |
711 | |
712 | return !!(val & ICC_SRE_EL1_SRE); | |
713 | } | |
714 | ||
021f6537 MZ |
715 | #endif |
716 | ||
717 | #endif |