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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H | |
19 | #define __LINUX_IRQCHIP_ARM_GIC_V3_H | |
20 | ||
21 | /* | |
22 | * Distributor registers. We assume we're running non-secure, with ARE | |
23 | * being set. Secure-only and non-ARE registers are not described. | |
24 | */ | |
25 | #define GICD_CTLR 0x0000 | |
26 | #define GICD_TYPER 0x0004 | |
27 | #define GICD_IIDR 0x0008 | |
28 | #define GICD_STATUSR 0x0010 | |
29 | #define GICD_SETSPI_NSR 0x0040 | |
30 | #define GICD_CLRSPI_NSR 0x0048 | |
31 | #define GICD_SETSPI_SR 0x0050 | |
32 | #define GICD_CLRSPI_SR 0x0058 | |
33 | #define GICD_SEIR 0x0068 | |
a0675c25 | 34 | #define GICD_IGROUPR 0x0080 |
021f6537 MZ |
35 | #define GICD_ISENABLER 0x0100 |
36 | #define GICD_ICENABLER 0x0180 | |
37 | #define GICD_ISPENDR 0x0200 | |
38 | #define GICD_ICPENDR 0x0280 | |
39 | #define GICD_ISACTIVER 0x0300 | |
40 | #define GICD_ICACTIVER 0x0380 | |
41 | #define GICD_IPRIORITYR 0x0400 | |
42 | #define GICD_ICFGR 0x0C00 | |
a0675c25 AP |
43 | #define GICD_IGRPMODR 0x0D00 |
44 | #define GICD_NSACR 0x0E00 | |
021f6537 | 45 | #define GICD_IROUTER 0x6000 |
a0675c25 | 46 | #define GICD_IDREGS 0xFFD0 |
021f6537 MZ |
47 | #define GICD_PIDR2 0xFFE8 |
48 | ||
a0675c25 AP |
49 | /* |
50 | * Those registers are actually from GICv2, but the spec demands that they | |
51 | * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). | |
52 | */ | |
53 | #define GICD_ITARGETSR 0x0800 | |
54 | #define GICD_SGIR 0x0F00 | |
55 | #define GICD_CPENDSGIR 0x0F10 | |
56 | #define GICD_SPENDSGIR 0x0F20 | |
57 | ||
021f6537 | 58 | #define GICD_CTLR_RWP (1U << 31) |
a0675c25 | 59 | #define GICD_CTLR_DS (1U << 6) |
021f6537 MZ |
60 | #define GICD_CTLR_ARE_NS (1U << 4) |
61 | #define GICD_CTLR_ENABLE_G1A (1U << 1) | |
62 | #define GICD_CTLR_ENABLE_G1 (1U << 0) | |
63 | ||
a0675c25 AP |
64 | /* |
65 | * In systems with a single security state (what we emulate in KVM) | |
66 | * the meaning of the interrupt group enable bits is slightly different | |
67 | */ | |
68 | #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) | |
69 | #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) | |
70 | ||
71 | #define GICD_TYPER_LPIS (1U << 17) | |
72 | #define GICD_TYPER_MBIS (1U << 16) | |
73 | ||
f5c1434c MZ |
74 | #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) |
75 | #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) | |
f5c1434c | 76 | |
021f6537 MZ |
77 | #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) |
78 | #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) | |
79 | ||
80 | #define GIC_PIDR2_ARCH_MASK 0xf0 | |
81 | #define GIC_PIDR2_ARCH_GICv3 0x30 | |
82 | #define GIC_PIDR2_ARCH_GICv4 0x40 | |
83 | ||
a0675c25 AP |
84 | #define GIC_V3_DIST_SIZE 0x10000 |
85 | ||
021f6537 MZ |
86 | /* |
87 | * Re-Distributor registers, offsets from RD_base | |
88 | */ | |
89 | #define GICR_CTLR GICD_CTLR | |
90 | #define GICR_IIDR 0x0004 | |
91 | #define GICR_TYPER 0x0008 | |
92 | #define GICR_STATUSR GICD_STATUSR | |
93 | #define GICR_WAKER 0x0014 | |
94 | #define GICR_SETLPIR 0x0040 | |
95 | #define GICR_CLRLPIR 0x0048 | |
96 | #define GICR_SEIR GICD_SEIR | |
97 | #define GICR_PROPBASER 0x0070 | |
98 | #define GICR_PENDBASER 0x0078 | |
99 | #define GICR_INVLPIR 0x00A0 | |
100 | #define GICR_INVALLR 0x00B0 | |
101 | #define GICR_SYNCR 0x00C0 | |
102 | #define GICR_MOVLPIR 0x0100 | |
103 | #define GICR_MOVALLR 0x0110 | |
a0675c25 | 104 | #define GICR_IDREGS GICD_IDREGS |
021f6537 MZ |
105 | #define GICR_PIDR2 GICD_PIDR2 |
106 | ||
cc2d3216 MZ |
107 | #define GICR_CTLR_ENABLE_LPIS (1UL << 0) |
108 | ||
109 | #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) | |
110 | ||
021f6537 MZ |
111 | #define GICR_WAKER_ProcessorSleep (1U << 1) |
112 | #define GICR_WAKER_ChildrenAsleep (1U << 2) | |
113 | ||
645b9e49 AP |
114 | #define GIC_BASER_CACHE_nCnB 0ULL |
115 | #define GIC_BASER_CACHE_SameAsInner 0ULL | |
116 | #define GIC_BASER_CACHE_nC 1ULL | |
117 | #define GIC_BASER_CACHE_RaWt 2ULL | |
118 | #define GIC_BASER_CACHE_RaWb 3ULL | |
119 | #define GIC_BASER_CACHE_WaWt 4ULL | |
120 | #define GIC_BASER_CACHE_WaWb 5ULL | |
121 | #define GIC_BASER_CACHE_RaWaWt 6ULL | |
122 | #define GIC_BASER_CACHE_RaWaWb 7ULL | |
123 | #define GIC_BASER_CACHE_MASK 7ULL | |
124 | #define GIC_BASER_NonShareable 0ULL | |
125 | #define GIC_BASER_InnerShareable 1ULL | |
126 | #define GIC_BASER_OuterShareable 2ULL | |
127 | #define GIC_BASER_SHAREABILITY_MASK 3ULL | |
128 | ||
129 | #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ | |
130 | (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) | |
131 | ||
132 | #define GIC_BASER_SHAREABILITY(reg, type) \ | |
133 | (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) | |
134 | ||
71afe470 EA |
135 | /* encode a size field of width @w containing @n - 1 units */ |
136 | #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) | |
137 | ||
645b9e49 AP |
138 | #define GICR_PROPBASER_SHAREABILITY_SHIFT (10) |
139 | #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) | |
140 | #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) | |
141 | #define GICR_PROPBASER_SHAREABILITY_MASK \ | |
142 | GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) | |
143 | #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ | |
144 | GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) | |
145 | #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ | |
146 | GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) | |
147 | #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK | |
148 | ||
149 | #define GICR_PROPBASER_InnerShareable \ | |
150 | GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) | |
8c828a53 MZ |
151 | |
152 | #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB) | |
153 | #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC) | |
154 | #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) | |
155 | #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) | |
156 | #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt) | |
157 | #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb) | |
158 | #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt) | |
159 | #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb) | |
160 | ||
645b9e49 | 161 | #define GICR_PROPBASER_IDBITS_MASK (0x1f) |
44de9d68 EA |
162 | #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) |
163 | #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) | |
645b9e49 AP |
164 | |
165 | #define GICR_PENDBASER_SHAREABILITY_SHIFT (10) | |
166 | #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) | |
167 | #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) | |
168 | #define GICR_PENDBASER_SHAREABILITY_MASK \ | |
169 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) | |
170 | #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ | |
171 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) | |
172 | #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ | |
173 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) | |
174 | #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK | |
175 | ||
176 | #define GICR_PENDBASER_InnerShareable \ | |
177 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) | |
8c828a53 MZ |
178 | |
179 | #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB) | |
180 | #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC) | |
181 | #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) | |
182 | #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) | |
183 | #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt) | |
184 | #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb) | |
185 | #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt) | |
186 | #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb) | |
187 | ||
645b9e49 | 188 | #define GICR_PENDBASER_PTZ BIT_ULL(62) |
4ad3e363 | 189 | |
021f6537 MZ |
190 | /* |
191 | * Re-Distributor registers, offsets from SGI_base | |
192 | */ | |
a0675c25 | 193 | #define GICR_IGROUPR0 GICD_IGROUPR |
021f6537 MZ |
194 | #define GICR_ISENABLER0 GICD_ISENABLER |
195 | #define GICR_ICENABLER0 GICD_ICENABLER | |
196 | #define GICR_ISPENDR0 GICD_ISPENDR | |
197 | #define GICR_ICPENDR0 GICD_ICPENDR | |
198 | #define GICR_ISACTIVER0 GICD_ISACTIVER | |
199 | #define GICR_ICACTIVER0 GICD_ICACTIVER | |
200 | #define GICR_IPRIORITYR0 GICD_IPRIORITYR | |
201 | #define GICR_ICFGR0 GICD_ICFGR | |
a0675c25 AP |
202 | #define GICR_IGRPMODR0 GICD_IGRPMODR |
203 | #define GICR_NSACR GICD_NSACR | |
021f6537 | 204 | |
cc2d3216 | 205 | #define GICR_TYPER_PLPIS (1U << 0) |
021f6537 | 206 | #define GICR_TYPER_VLPIS (1U << 1) |
0edc23ea | 207 | #define GICR_TYPER_DirectLPIS (1U << 3) |
021f6537 MZ |
208 | #define GICR_TYPER_LAST (1U << 4) |
209 | ||
a0675c25 AP |
210 | #define GIC_V3_REDIST_SIZE 0x20000 |
211 | ||
cc2d3216 MZ |
212 | #define LPI_PROP_GROUP1 (1 << 1) |
213 | #define LPI_PROP_ENABLED (1 << 0) | |
214 | ||
215 | /* | |
216 | * ITS registers, offsets from ITS_base | |
217 | */ | |
218 | #define GITS_CTLR 0x0000 | |
219 | #define GITS_IIDR 0x0004 | |
220 | #define GITS_TYPER 0x0008 | |
221 | #define GITS_CBASER 0x0080 | |
222 | #define GITS_CWRITER 0x0088 | |
223 | #define GITS_CREADR 0x0090 | |
224 | #define GITS_BASER 0x0100 | |
645b9e49 AP |
225 | #define GITS_IDREGS_BASE 0xffd0 |
226 | #define GITS_PIDR0 0xffe0 | |
227 | #define GITS_PIDR1 0xffe4 | |
cc2d3216 | 228 | #define GITS_PIDR2 GICR_PIDR2 |
645b9e49 AP |
229 | #define GITS_PIDR4 0xffd0 |
230 | #define GITS_CIDR0 0xfff0 | |
231 | #define GITS_CIDR1 0xfff4 | |
232 | #define GITS_CIDR2 0xfff8 | |
233 | #define GITS_CIDR3 0xfffc | |
cc2d3216 MZ |
234 | |
235 | #define GITS_TRANSLATER 0x10040 | |
236 | ||
7cb99116 YW |
237 | #define GITS_CTLR_ENABLE (1U << 0) |
238 | #define GITS_CTLR_QUIESCENT (1U << 31) | |
239 | ||
645b9e49 | 240 | #define GITS_TYPER_PLPIS (1UL << 0) |
71afe470 | 241 | #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 |
645b9e49 | 242 | #define GITS_TYPER_IDBITS_SHIFT 8 |
f54b97ed MZ |
243 | #define GITS_TYPER_DEVBITS_SHIFT 13 |
244 | #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) | |
cc2d3216 | 245 | #define GITS_TYPER_PTA (1UL << 19) |
645b9e49 AP |
246 | #define GITS_TYPER_HWCOLLCNT_SHIFT 24 |
247 | ||
ab01c6bd EA |
248 | #define GITS_IIDR_REV_SHIFT 12 |
249 | #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT) | |
250 | #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf) | |
251 | #define GITS_IIDR_PRODUCTID_SHIFT 24 | |
252 | ||
b11283eb | 253 | #define GITS_CBASER_VALID (1ULL << 63) |
645b9e49 AP |
254 | #define GITS_CBASER_SHAREABILITY_SHIFT (10) |
255 | #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) | |
256 | #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) | |
257 | #define GITS_CBASER_SHAREABILITY_MASK \ | |
258 | GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) | |
259 | #define GITS_CBASER_INNER_CACHEABILITY_MASK \ | |
260 | GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) | |
261 | #define GITS_CBASER_OUTER_CACHEABILITY_MASK \ | |
262 | GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) | |
263 | #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK | |
264 | ||
265 | #define GITS_CBASER_InnerShareable \ | |
266 | GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) | |
8c828a53 MZ |
267 | |
268 | #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) | |
269 | #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) | |
270 | #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) | |
271 | #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) | |
272 | #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) | |
273 | #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) | |
274 | #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) | |
275 | #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) | |
cc2d3216 MZ |
276 | |
277 | #define GITS_BASER_NR_REGS 8 | |
278 | ||
b11283eb | 279 | #define GITS_BASER_VALID (1ULL << 63) |
645b9e49 | 280 | #define GITS_BASER_INDIRECT (1ULL << 62) |
8c828a53 | 281 | |
645b9e49 AP |
282 | #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) |
283 | #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) | |
284 | #define GITS_BASER_INNER_CACHEABILITY_MASK \ | |
285 | GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) | |
8c828a53 | 286 | #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK |
645b9e49 AP |
287 | #define GITS_BASER_OUTER_CACHEABILITY_MASK \ |
288 | GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) | |
289 | #define GITS_BASER_SHAREABILITY_MASK \ | |
290 | GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK) | |
291 | ||
8c828a53 MZ |
292 | #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) |
293 | #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC) | |
294 | #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) | |
295 | #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) | |
296 | #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt) | |
297 | #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb) | |
298 | #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt) | |
299 | #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb) | |
300 | ||
645b9e49 | 301 | #define GITS_BASER_TYPE_SHIFT (56) |
cc2d3216 | 302 | #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) |
645b9e49 | 303 | #define GITS_BASER_ENTRY_SIZE_SHIFT (48) |
9224eb77 | 304 | #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) |
71afe470 | 305 | #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) |
cc2d3216 | 306 | #define GITS_BASER_SHAREABILITY_SHIFT (10) |
645b9e49 AP |
307 | #define GITS_BASER_InnerShareable \ |
308 | GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | |
cc2d3216 | 309 | #define GITS_BASER_PAGE_SIZE_SHIFT (8) |
e29bd6f2 VM |
310 | #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT) |
311 | #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT) | |
312 | #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT) | |
313 | #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT) | |
30f21363 | 314 | #define GITS_BASER_PAGES_MAX 256 |
9347359a | 315 | #define GITS_BASER_PAGES_SHIFT (0) |
645b9e49 | 316 | #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) |
cc2d3216 MZ |
317 | |
318 | #define GITS_BASER_TYPE_NONE 0 | |
319 | #define GITS_BASER_TYPE_DEVICE 1 | |
320 | #define GITS_BASER_TYPE_VCPU 2 | |
4f46de9d | 321 | #define GITS_BASER_TYPE_RESERVED3 3 |
cc2d3216 MZ |
322 | #define GITS_BASER_TYPE_COLLECTION 4 |
323 | #define GITS_BASER_TYPE_RESERVED5 5 | |
324 | #define GITS_BASER_TYPE_RESERVED6 6 | |
325 | #define GITS_BASER_TYPE_RESERVED7 7 | |
326 | ||
3faf24ea SD |
327 | #define GITS_LVL1_ENTRY_SIZE (8UL) |
328 | ||
cc2d3216 MZ |
329 | /* |
330 | * ITS commands | |
331 | */ | |
332 | #define GITS_CMD_MAPD 0x08 | |
333 | #define GITS_CMD_MAPC 0x09 | |
645b9e49 | 334 | #define GITS_CMD_MAPTI 0x0a |
645b9e49 | 335 | #define GITS_CMD_MAPI 0x0b |
cc2d3216 MZ |
336 | #define GITS_CMD_MOVI 0x01 |
337 | #define GITS_CMD_DISCARD 0x0f | |
338 | #define GITS_CMD_INV 0x0c | |
339 | #define GITS_CMD_MOVALL 0x0e | |
340 | #define GITS_CMD_INVALL 0x0d | |
341 | #define GITS_CMD_INT 0x03 | |
342 | #define GITS_CMD_CLEAR 0x04 | |
343 | #define GITS_CMD_SYNC 0x05 | |
344 | ||
645b9e49 AP |
345 | /* |
346 | * ITS error numbers | |
347 | */ | |
348 | #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 | |
349 | #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 | |
fd837b08 | 350 | #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307 |
645b9e49 AP |
351 | #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 |
352 | #define E_ITS_MAPD_DEVICE_OOR 0x010801 | |
0d44cdb6 | 353 | #define E_ITS_MAPD_ITTSIZE_OOR 0x010802 |
645b9e49 AP |
354 | #define E_ITS_MAPC_PROCNUM_OOR 0x010902 |
355 | #define E_ITS_MAPC_COLLECTION_OOR 0x010903 | |
356 | #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 | |
0d44cdb6 | 357 | #define E_ITS_MAPTI_ID_OOR 0x010a05 |
645b9e49 AP |
358 | #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 |
359 | #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 | |
360 | #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 | |
361 | #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 | |
362 | #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 | |
363 | ||
021f6537 MZ |
364 | /* |
365 | * CPU interface registers | |
366 | */ | |
5c341537 VK |
367 | #define ICC_CTLR_EL1_EOImode_SHIFT (1) |
368 | #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) | |
369 | #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) | |
370 | #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT) | |
371 | #define ICC_CTLR_EL1_CBPR_SHIFT 0 | |
372 | #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) | |
373 | #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8 | |
374 | #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) | |
375 | #define ICC_CTLR_EL1_ID_BITS_SHIFT 11 | |
376 | #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT) | |
377 | #define ICC_CTLR_EL1_SEIS_SHIFT 14 | |
378 | #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT) | |
379 | #define ICC_CTLR_EL1_A3V_SHIFT 15 | |
380 | #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) | |
381 | #define ICC_PMR_EL1_SHIFT 0 | |
382 | #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) | |
383 | #define ICC_BPR0_EL1_SHIFT 0 | |
384 | #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT) | |
385 | #define ICC_BPR1_EL1_SHIFT 0 | |
386 | #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT) | |
387 | #define ICC_IGRPEN0_EL1_SHIFT 0 | |
388 | #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT) | |
389 | #define ICC_IGRPEN1_EL1_SHIFT 0 | |
390 | #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT) | |
4dfc0505 MZ |
391 | #define ICC_SRE_EL1_DIB (1U << 2) |
392 | #define ICC_SRE_EL1_DFB (1U << 1) | |
021f6537 MZ |
393 | #define ICC_SRE_EL1_SRE (1U << 0) |
394 | ||
395 | /* | |
396 | * Hypervisor interface registers (SRE only) | |
397 | */ | |
f6c86a41 JPB |
398 | #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) |
399 | ||
400 | #define ICH_LR_EOI (1ULL << 41) | |
401 | #define ICH_LR_GROUP (1ULL << 60) | |
402 | #define ICH_LR_HW (1ULL << 61) | |
403 | #define ICH_LR_STATE (3ULL << 62) | |
404 | #define ICH_LR_PENDING_BIT (1ULL << 62) | |
405 | #define ICH_LR_ACTIVE_BIT (1ULL << 63) | |
fb182cf8 | 406 | #define ICH_LR_PHYS_ID_SHIFT 32 |
f6c86a41 | 407 | #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) |
59529f69 | 408 | #define ICH_LR_PRIORITY_SHIFT 48 |
132a324a | 409 | #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) |
021f6537 | 410 | |
44bfc42e AP |
411 | /* These are for GICv2 emulation only */ |
412 | #define GICH_LR_VIRTUALID (0x3ffUL << 0) | |
413 | #define GICH_LR_PHYSID_CPUID_SHIFT (10) | |
414 | #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) | |
021f6537 MZ |
415 | |
416 | #define ICH_MISR_EOI (1 << 0) | |
417 | #define ICH_MISR_U (1 << 1) | |
418 | ||
419 | #define ICH_HCR_EN (1 << 0) | |
420 | #define ICH_HCR_UIE (1 << 1) | |
ff89511e | 421 | #define ICH_HCR_TC (1 << 10) |
abf55766 | 422 | #define ICH_HCR_TALL0 (1 << 11) |
9c7bfc28 | 423 | #define ICH_HCR_TALL1 (1 << 12) |
b6f49035 MZ |
424 | #define ICH_HCR_EOIcount_SHIFT 27 |
425 | #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) | |
021f6537 | 426 | |
28232a43 CD |
427 | #define ICH_VMCR_ACK_CTL_SHIFT 2 |
428 | #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) | |
429 | #define ICH_VMCR_FIQ_EN_SHIFT 3 | |
430 | #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) | |
5c341537 VK |
431 | #define ICH_VMCR_CBPR_SHIFT 4 |
432 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) | |
433 | #define ICH_VMCR_EOIM_SHIFT 9 | |
434 | #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) | |
021f6537 MZ |
435 | #define ICH_VMCR_BPR1_SHIFT 18 |
436 | #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) | |
437 | #define ICH_VMCR_BPR0_SHIFT 21 | |
438 | #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) | |
439 | #define ICH_VMCR_PMR_SHIFT 24 | |
440 | #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) | |
5c341537 VK |
441 | #define ICH_VMCR_ENG0_SHIFT 0 |
442 | #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) | |
443 | #define ICH_VMCR_ENG1_SHIFT 1 | |
444 | #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) | |
445 | ||
446 | #define ICH_VTR_PRI_BITS_SHIFT 29 | |
447 | #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) | |
448 | #define ICH_VTR_ID_BITS_SHIFT 23 | |
449 | #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) | |
450 | #define ICH_VTR_SEIS_SHIFT 22 | |
451 | #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) | |
452 | #define ICH_VTR_A3V_SHIFT 21 | |
453 | #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) | |
021f6537 | 454 | |
021f6537 MZ |
455 | #define ICC_IAR1_EL1_SPURIOUS 0x3ff |
456 | ||
021f6537 MZ |
457 | #define ICC_SRE_EL2_SRE (1 << 0) |
458 | #define ICC_SRE_EL2_ENABLE (1 << 3) | |
459 | ||
7e580278 AP |
460 | #define ICC_SGI1R_TARGET_LIST_SHIFT 0 |
461 | #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) | |
462 | #define ICC_SGI1R_AFFINITY_1_SHIFT 16 | |
463 | #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) | |
464 | #define ICC_SGI1R_SGI_ID_SHIFT 24 | |
dd5f1b04 | 465 | #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) |
7e580278 | 466 | #define ICC_SGI1R_AFFINITY_2_SHIFT 32 |
fab0cdc3 | 467 | #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) |
7e580278 AP |
468 | #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 |
469 | #define ICC_SGI1R_AFFINITY_3_SHIFT 48 | |
fab0cdc3 | 470 | #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) |
7e580278 | 471 | |
7936e914 | 472 | #include <asm/arch_gicv3.h> |
021f6537 MZ |
473 | |
474 | #ifndef __ASSEMBLY__ | |
475 | ||
b48ac83d MZ |
476 | /* |
477 | * We need a value to serve as a irq-type for LPIs. Choose one that will | |
478 | * hopefully pique the interest of the reviewer. | |
479 | */ | |
480 | #define GIC_IRQ_TYPE_LPI 0xa110c8ed | |
481 | ||
f5c1434c MZ |
482 | struct rdists { |
483 | struct { | |
484 | void __iomem *rd_base; | |
485 | struct page *pend_page; | |
486 | phys_addr_t phys_base; | |
487 | } __percpu *rdist; | |
488 | struct page *prop_page; | |
489 | int id_bits; | |
490 | u64 flags; | |
0edc23ea MZ |
491 | bool has_vlpis; |
492 | bool has_direct_lpi; | |
f5c1434c MZ |
493 | }; |
494 | ||
7936e914 | 495 | struct irq_domain; |
db40f0a7 | 496 | struct fwnode_handle; |
7936e914 | 497 | int its_cpu_init(void); |
db40f0a7 | 498 | int its_init(struct fwnode_handle *handle, struct rdists *rdists, |
7936e914 | 499 | struct irq_domain *domain); |
0b6a3da9 | 500 | |
7cabd008 MZ |
501 | static inline bool gic_enable_sre(void) |
502 | { | |
7936e914 | 503 | u32 val; |
7cabd008 | 504 | |
7936e914 | 505 | val = gic_read_sre(); |
7cabd008 MZ |
506 | if (val & ICC_SRE_EL1_SRE) |
507 | return true; | |
508 | ||
509 | val |= ICC_SRE_EL1_SRE; | |
7936e914 JPB |
510 | gic_write_sre(val); |
511 | val = gic_read_sre(); | |
7cabd008 MZ |
512 | |
513 | return !!(val & ICC_SRE_EL1_SRE); | |
514 | } | |
515 | ||
021f6537 MZ |
516 | #endif |
517 | ||
518 | #endif |