[mirror_ubuntu-bionic-kernel.git] / include / linux / irqchip / arm-gic-v3.h

/*
 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
#define __LINUX_IRQCHIP_ARM_GIC_V3_H

/*
 * Distributor registers. We assume we're running non-secure, with ARE
 * being set. Secure-only and non-ARE registers are not described.
 */
#define GICD_CTLR			0x0000
#define GICD_TYPER			0x0004
#define GICD_IIDR			0x0008
#define GICD_STATUSR			0x0010
#define GICD_SETSPI_NSR			0x0040
#define GICD_CLRSPI_NSR			0x0048
#define GICD_SETSPI_SR			0x0050
#define GICD_CLRSPI_SR			0x0058
#define GICD_SEIR			0x0068
#define GICD_IGROUPR			0x0080
#define GICD_ISENABLER			0x0100
#define GICD_ICENABLER			0x0180
#define GICD_ISPENDR			0x0200
#define GICD_ICPENDR			0x0280
#define GICD_ISACTIVER			0x0300
#define GICD_ICACTIVER			0x0380
#define GICD_IPRIORITYR			0x0400
#define GICD_ICFGR			0x0C00
#define GICD_IGRPMODR			0x0D00
#define GICD_NSACR			0x0E00
#define GICD_IROUTER			0x6000
#define GICD_IDREGS			0xFFD0
#define GICD_PIDR2			0xFFE8

/*
 * Those registers are actually from GICv2, but the spec demands that they
 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
 */
#define GICD_ITARGETSR			0x0800
#define GICD_SGIR			0x0F00
#define GICD_CPENDSGIR			0x0F10
#define GICD_SPENDSGIR			0x0F20

#define GICD_CTLR_RWP			(1U << 31)
#define GICD_CTLR_DS			(1U << 6)
#define GICD_CTLR_ARE_NS		(1U << 4)
#define GICD_CTLR_ENABLE_G1A		(1U << 1)
#define GICD_CTLR_ENABLE_G1		(1U << 0)

/*
 * In systems with a single security state (what we emulate in KVM)
 * the meaning of the interrupt group enable bits is slightly different
 */
#define GICD_CTLR_ENABLE_SS_G1		(1U << 1)
#define GICD_CTLR_ENABLE_SS_G0		(1U << 0)

#define GICD_TYPER_LPIS			(1U << 17)
#define GICD_TYPER_MBIS			(1U << 16)

#define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)
#define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)

#define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
#define GICD_IROUTER_SPI_MODE_ANY	(1U << 31)

#define GIC_PIDR2_ARCH_MASK		0xf0
#define GIC_PIDR2_ARCH_GICv3		0x30
#define GIC_PIDR2_ARCH_GICv4		0x40

#define GIC_V3_DIST_SIZE		0x10000

/*
 * Re-Distributor registers, offsets from RD_base
 */
#define GICR_CTLR			GICD_CTLR
#define GICR_IIDR			0x0004
#define GICR_TYPER			0x0008
#define GICR_STATUSR			GICD_STATUSR
#define GICR_WAKER			0x0014
#define GICR_SETLPIR			0x0040
#define GICR_CLRLPIR			0x0048
#define GICR_SEIR			GICD_SEIR
#define GICR_PROPBASER			0x0070
#define GICR_PENDBASER			0x0078
#define GICR_INVLPIR			0x00A0
#define GICR_INVALLR			0x00B0
#define GICR_SYNCR			0x00C0
#define GICR_MOVLPIR			0x0100
#define GICR_MOVALLR			0x0110
#define GICR_IDREGS			GICD_IDREGS
#define GICR_PIDR2			GICD_PIDR2

#define GICR_CTLR_ENABLE_LPIS		(1UL << 0)

#define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)

#define GICR_WAKER_ProcessorSleep	(1U << 1)
#define GICR_WAKER_ChildrenAsleep	(1U << 2)

#define GIC_BASER_CACHE_nCnB		0ULL
#define GIC_BASER_CACHE_SameAsInner	0ULL
#define GIC_BASER_CACHE_nC		1ULL
#define GIC_BASER_CACHE_RaWt		2ULL
#define GIC_BASER_CACHE_RaWb		3ULL
#define GIC_BASER_CACHE_WaWt		4ULL
#define GIC_BASER_CACHE_WaWb		5ULL
#define GIC_BASER_CACHE_RaWaWt		6ULL
#define GIC_BASER_CACHE_RaWaWb		7ULL
#define GIC_BASER_CACHE_MASK		7ULL
#define GIC_BASER_NonShareable		0ULL
#define GIC_BASER_InnerShareable	1ULL
#define GIC_BASER_OuterShareable	2ULL
#define GIC_BASER_SHAREABILITY_MASK	3ULL

#define GIC_BASER_CACHEABILITY(reg, inner_outer, type)			\
	(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)

#define GIC_BASER_SHAREABILITY(reg, type)				\
	(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)

#define GICR_PROPBASER_SHAREABILITY_SHIFT		(10)
#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT		(7)
#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT		(56)
#define GICR_PROPBASER_SHAREABILITY_MASK				\
	GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
#define GICR_PROPBASER_INNER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK

#define GICR_PROPBASER_InnerShareable					\
	GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)

#define GICR_PROPBASER_nCnB	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
#define GICR_PROPBASER_nC 	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
#define GICR_PROPBASER_RaWt	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
#define GICR_PROPBASER_RaWb	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
#define GICR_PROPBASER_WaWt	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
#define GICR_PROPBASER_WaWb	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
#define GICR_PROPBASER_RaWaWt	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
#define GICR_PROPBASER_RaWaWb	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)

#define GICR_PROPBASER_IDBITS_MASK			(0x1f)

#define GICR_PENDBASER_SHAREABILITY_SHIFT		(10)
#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT		(7)
#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT		(56)
#define GICR_PENDBASER_SHAREABILITY_MASK				\
	GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
#define GICR_PENDBASER_INNER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK

#define GICR_PENDBASER_InnerShareable					\
	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)

#define GICR_PENDBASER_nCnB	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
#define GICR_PENDBASER_nC 	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
#define GICR_PENDBASER_RaWt	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
#define GICR_PENDBASER_RaWb	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
#define GICR_PENDBASER_WaWt	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
#define GICR_PENDBASER_WaWb	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
#define GICR_PENDBASER_RaWaWt	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
#define GICR_PENDBASER_RaWaWb	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)

#define GICR_PENDBASER_PTZ				BIT_ULL(62)

/*
 * Re-Distributor registers, offsets from SGI_base
 */
#define GICR_IGROUPR0			GICD_IGROUPR
#define GICR_ISENABLER0			GICD_ISENABLER
#define GICR_ICENABLER0			GICD_ICENABLER
#define GICR_ISPENDR0			GICD_ISPENDR
#define GICR_ICPENDR0			GICD_ICPENDR
#define GICR_ISACTIVER0			GICD_ISACTIVER
#define GICR_ICACTIVER0			GICD_ICACTIVER
#define GICR_IPRIORITYR0		GICD_IPRIORITYR
#define GICR_ICFGR0			GICD_ICFGR
#define GICR_IGRPMODR0			GICD_IGRPMODR
#define GICR_NSACR			GICD_NSACR

#define GICR_TYPER_PLPIS		(1U << 0)
#define GICR_TYPER_VLPIS		(1U << 1)
#define GICR_TYPER_LAST			(1U << 4)

#define GIC_V3_REDIST_SIZE		0x20000

#define LPI_PROP_GROUP1			(1 << 1)
#define LPI_PROP_ENABLED		(1 << 0)

/*
 * ITS registers, offsets from ITS_base
 */
#define GITS_CTLR			0x0000
#define GITS_IIDR			0x0004
#define GITS_TYPER			0x0008
#define GITS_CBASER			0x0080
#define GITS_CWRITER			0x0088
#define GITS_CREADR			0x0090
#define GITS_BASER			0x0100
#define GITS_IDREGS_BASE		0xffd0
#define GITS_PIDR0			0xffe0
#define GITS_PIDR1			0xffe4
#define GITS_PIDR2			GICR_PIDR2
#define GITS_PIDR4			0xffd0
#define GITS_CIDR0			0xfff0
#define GITS_CIDR1			0xfff4
#define GITS_CIDR2			0xfff8
#define GITS_CIDR3			0xfffc

#define GITS_TRANSLATER			0x10040

#define GITS_CTLR_ENABLE		(1U << 0)
#define GITS_CTLR_QUIESCENT		(1U << 31)

#define GITS_TYPER_PLPIS		(1UL << 0)
#define GITS_TYPER_IDBITS_SHIFT		8
#define GITS_TYPER_DEVBITS_SHIFT	13
#define GITS_TYPER_DEVBITS(r)		((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
#define GITS_TYPER_PTA			(1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT	24

#define GITS_CBASER_VALID			(1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT		(10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT	(59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT	(53)
#define GITS_CBASER_SHAREABILITY_MASK					\
	GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
#define GITS_CBASER_INNER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
#define GITS_CBASER_OUTER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK

#define GITS_CBASER_InnerShareable					\
	GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)

#define GITS_CBASER_nCnB	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
#define GITS_CBASER_nC		GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
#define GITS_CBASER_RaWt	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
#define GITS_CBASER_RaWb	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
#define GITS_CBASER_WaWt	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
#define GITS_CBASER_WaWb	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
#define GITS_CBASER_RaWaWt	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
#define GITS_CBASER_RaWaWb	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)

#define GITS_BASER_NR_REGS		8

#define GITS_BASER_VALID			(1ULL << 63)
#define GITS_BASER_INDIRECT			(1ULL << 62)

#define GITS_BASER_INNER_CACHEABILITY_SHIFT	(59)
#define GITS_BASER_OUTER_CACHEABILITY_SHIFT	(53)
#define GITS_BASER_INNER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
#define GITS_BASER_CACHEABILITY_MASK		GITS_BASER_INNER_CACHEABILITY_MASK
#define GITS_BASER_OUTER_CACHEABILITY_MASK				\
	GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
#define GITS_BASER_SHAREABILITY_MASK					\
	GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)

#define GITS_BASER_nCnB		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
#define GITS_BASER_nC		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
#define GITS_BASER_RaWt		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
#define GITS_BASER_RaWb		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
#define GITS_BASER_WaWt		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
#define GITS_BASER_WaWb		GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
#define GITS_BASER_RaWaWt	GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
#define GITS_BASER_RaWaWb	GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)

#define GITS_BASER_TYPE_SHIFT			(56)
#define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
#define GITS_BASER_ENTRY_SIZE_SHIFT		(48)
#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
#define GITS_BASER_SHAREABILITY_SHIFT	(10)
#define GITS_BASER_InnerShareable					\
	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
#define GITS_BASER_PAGE_SIZE_SHIFT	(8)
#define GITS_BASER_PAGE_SIZE_4K		(0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_16K	(1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_64K	(2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_MASK	(3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGES_MAX		256
#define GITS_BASER_PAGES_SHIFT		(0)
#define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)

#define GITS_BASER_TYPE_NONE		0
#define GITS_BASER_TYPE_DEVICE		1
#define GITS_BASER_TYPE_VCPU		2
#define GITS_BASER_TYPE_RESERVED3	3
#define GITS_BASER_TYPE_COLLECTION	4
#define GITS_BASER_TYPE_RESERVED5	5
#define GITS_BASER_TYPE_RESERVED6	6
#define GITS_BASER_TYPE_RESERVED7	7

#define GITS_LVL1_ENTRY_SIZE           (8UL)

/*
 * ITS commands
 */
#define GITS_CMD_MAPD			0x08
#define GITS_CMD_MAPC			0x09
#define GITS_CMD_MAPTI			0x0a
#define GITS_CMD_MAPI			0x0b
#define GITS_CMD_MOVI			0x01
#define GITS_CMD_DISCARD		0x0f
#define GITS_CMD_INV			0x0c
#define GITS_CMD_MOVALL			0x0e
#define GITS_CMD_INVALL			0x0d
#define GITS_CMD_INT			0x03
#define GITS_CMD_CLEAR			0x04
#define GITS_CMD_SYNC			0x05

/*
 * ITS error numbers
 */
#define E_ITS_MOVI_UNMAPPED_INTERRUPT		0x010107
#define E_ITS_MOVI_UNMAPPED_COLLECTION		0x010109
#define E_ITS_INT_UNMAPPED_INTERRUPT		0x010307
#define E_ITS_CLEAR_UNMAPPED_INTERRUPT		0x010507
#define E_ITS_MAPD_DEVICE_OOR			0x010801
#define E_ITS_MAPC_PROCNUM_OOR			0x010902
#define E_ITS_MAPC_COLLECTION_OOR		0x010903
#define E_ITS_MAPTI_UNMAPPED_DEVICE		0x010a04
#define E_ITS_MAPTI_PHYSICALID_OOR		0x010a06
#define E_ITS_INV_UNMAPPED_INTERRUPT		0x010c07
#define E_ITS_INVALL_UNMAPPED_COLLECTION	0x010d09
#define E_ITS_MOVALL_PROCNUM_OOR		0x010e01
#define E_ITS_DISCARD_UNMAPPED_INTERRUPT	0x010f07

/*
 * CPU interface registers
 */
#define ICC_CTLR_EL1_EOImode_SHIFT	(1)
#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << ICC_CTLR_EL1_EOImode_SHIFT)
#define ICC_CTLR_EL1_EOImode_drop	(1U << ICC_CTLR_EL1_EOImode_SHIFT)
#define ICC_CTLR_EL1_EOImode_MASK	(1 << ICC_CTLR_EL1_EOImode_SHIFT)
#define ICC_CTLR_EL1_CBPR_SHIFT		0
#define ICC_CTLR_EL1_CBPR_MASK		(1 << ICC_CTLR_EL1_CBPR_SHIFT)
#define ICC_CTLR_EL1_PRI_BITS_SHIFT	8
#define ICC_CTLR_EL1_PRI_BITS_MASK	(0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
#define ICC_CTLR_EL1_ID_BITS_SHIFT	11
#define ICC_CTLR_EL1_ID_BITS_MASK	(0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
#define ICC_CTLR_EL1_SEIS_SHIFT		14
#define ICC_CTLR_EL1_SEIS_MASK		(0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
#define ICC_CTLR_EL1_A3V_SHIFT		15
#define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
#define ICC_PMR_EL1_SHIFT		0
#define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
#define ICC_BPR0_EL1_SHIFT		0
#define ICC_BPR0_EL1_MASK		(0x7 << ICC_BPR0_EL1_SHIFT)
#define ICC_BPR1_EL1_SHIFT		0
#define ICC_BPR1_EL1_MASK		(0x7 << ICC_BPR1_EL1_SHIFT)
#define ICC_IGRPEN0_EL1_SHIFT		0
#define ICC_IGRPEN0_EL1_MASK		(1 << ICC_IGRPEN0_EL1_SHIFT)
#define ICC_IGRPEN1_EL1_SHIFT		0
#define ICC_IGRPEN1_EL1_MASK		(1 << ICC_IGRPEN1_EL1_SHIFT)
#define ICC_SRE_EL1_DIB			(1U << 2)
#define ICC_SRE_EL1_DFB			(1U << 1)
#define ICC_SRE_EL1_SRE			(1U << 0)

/*
 * Hypervisor interface registers (SRE only)
 */
#define ICH_LR_VIRTUAL_ID_MASK		((1ULL << 32) - 1)

#define ICH_LR_EOI			(1ULL << 41)
#define ICH_LR_GROUP			(1ULL << 60)
#define ICH_LR_HW			(1ULL << 61)
#define ICH_LR_STATE			(3ULL << 62)
#define ICH_LR_PENDING_BIT		(1ULL << 62)
#define ICH_LR_ACTIVE_BIT		(1ULL << 63)
#define ICH_LR_PHYS_ID_SHIFT		32
#define ICH_LR_PHYS_ID_MASK		(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
#define ICH_LR_PRIORITY_SHIFT		48

/* These are for GICv2 emulation only */
#define GICH_LR_VIRTUALID		(0x3ffUL << 0)
#define GICH_LR_PHYSID_CPUID_SHIFT	(10)
#define GICH_LR_PHYSID_CPUID		(7UL << GICH_LR_PHYSID_CPUID_SHIFT)

#define ICH_MISR_EOI			(1 << 0)
#define ICH_MISR_U			(1 << 1)

#define ICH_HCR_EN			(1 << 0)
#define ICH_HCR_UIE			(1 << 1)

#define ICH_VMCR_CBPR_SHIFT		4
#define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)
#define ICH_VMCR_EOIM_SHIFT		9
#define ICH_VMCR_EOIM_MASK		(1 << ICH_VMCR_EOIM_SHIFT)
#define ICH_VMCR_BPR1_SHIFT		18
#define ICH_VMCR_BPR1_MASK		(7 << ICH_VMCR_BPR1_SHIFT)
#define ICH_VMCR_BPR0_SHIFT		21
#define ICH_VMCR_BPR0_MASK		(7 << ICH_VMCR_BPR0_SHIFT)
#define ICH_VMCR_PMR_SHIFT		24
#define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)
#define ICH_VMCR_ENG0_SHIFT		0
#define ICH_VMCR_ENG0_MASK		(1 << ICH_VMCR_ENG0_SHIFT)
#define ICH_VMCR_ENG1_SHIFT		1
#define ICH_VMCR_ENG1_MASK		(1 << ICH_VMCR_ENG1_SHIFT)

#define ICH_VTR_PRI_BITS_SHIFT		29
#define ICH_VTR_PRI_BITS_MASK		(7 << ICH_VTR_PRI_BITS_SHIFT)
#define ICH_VTR_ID_BITS_SHIFT		23
#define ICH_VTR_ID_BITS_MASK		(7 << ICH_VTR_ID_BITS_SHIFT)
#define ICH_VTR_SEIS_SHIFT		22
#define ICH_VTR_SEIS_MASK		(1 << ICH_VTR_SEIS_SHIFT)
#define ICH_VTR_A3V_SHIFT		21
#define ICH_VTR_A3V_MASK		(1 << ICH_VTR_A3V_SHIFT)

#define ICC_IAR1_EL1_SPURIOUS		0x3ff

#define ICC_SRE_EL2_SRE			(1 << 0)
#define ICC_SRE_EL2_ENABLE		(1 << 3)

#define ICC_SGI1R_TARGET_LIST_SHIFT	0
#define ICC_SGI1R_TARGET_LIST_MASK	(0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
#define ICC_SGI1R_AFFINITY_1_SHIFT	16
#define ICC_SGI1R_AFFINITY_1_MASK	(0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
#define ICC_SGI1R_SGI_ID_SHIFT		24
#define ICC_SGI1R_SGI_ID_MASK		(0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
#define ICC_SGI1R_AFFINITY_2_SHIFT	32
#define ICC_SGI1R_AFFINITY_2_MASK	(0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT	40
#define ICC_SGI1R_AFFINITY_3_SHIFT	48
#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)

#include <asm/arch_gicv3.h>

#ifndef __ASSEMBLY__

/*
 * We need a value to serve as a irq-type for LPIs. Choose one that will
 * hopefully pique the interest of the reviewer.
 */
#define GIC_IRQ_TYPE_LPI		0xa110c8ed

struct rdists {
	struct {
		void __iomem	*rd_base;
		struct page	*pend_page;
		phys_addr_t	phys_base;
	} __percpu		*rdist;
	struct page		*prop_page;
	int			id_bits;
	u64			flags;
};

struct irq_domain;
struct fwnode_handle;
int its_cpu_init(void);
int its_init(struct fwnode_handle *handle, struct rdists *rdists,
	     struct irq_domain *domain);

static inline bool gic_enable_sre(void)
{
	u32 val;

	val = gic_read_sre();
	if (val & ICC_SRE_EL1_SRE)
		return true;

	val |= ICC_SRE_EL1_SRE;
	gic_write_sre(val);
	val = gic_read_sre();

	return !!(val & ICC_SRE_EL1_SRE);
}

#endif

#endif
Commit	Line	Data
021f6537 MZ	1	/*
	2	* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18	#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
	19	#define __LINUX_IRQCHIP_ARM_GIC_V3_H
	20
	21	/*
	22	* Distributor registers. We assume we're running non-secure, with ARE
	23	* being set. Secure-only and non-ARE registers are not described.
	24	*/
	25	#define GICD_CTLR 0x0000
	26	#define GICD_TYPER 0x0004
	27	#define GICD_IIDR 0x0008
	28	#define GICD_STATUSR 0x0010
	29	#define GICD_SETSPI_NSR 0x0040
	30	#define GICD_CLRSPI_NSR 0x0048
	31	#define GICD_SETSPI_SR 0x0050
	32	#define GICD_CLRSPI_SR 0x0058
	33	#define GICD_SEIR 0x0068
a0675c25	34	#define GICD_IGROUPR 0x0080
021f6537 MZ	35	#define GICD_ISENABLER 0x0100
	36	#define GICD_ICENABLER 0x0180
	37	#define GICD_ISPENDR 0x0200
	38	#define GICD_ICPENDR 0x0280
	39	#define GICD_ISACTIVER 0x0300
	40	#define GICD_ICACTIVER 0x0380
	41	#define GICD_IPRIORITYR 0x0400
	42	#define GICD_ICFGR 0x0C00
a0675c25 AP	43	#define GICD_IGRPMODR 0x0D00
a0675c25 AP	44	#define GICD_NSACR 0x0E00
021f6537	45	#define GICD_IROUTER 0x6000
a0675c25	46	#define GICD_IDREGS 0xFFD0
021f6537 MZ	47	#define GICD_PIDR2 0xFFE8
021f6537 MZ	48
a0675c25 AP	49	/*
	50	* Those registers are actually from GICv2, but the spec demands that they
	51	* are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
	52	*/
	53	#define GICD_ITARGETSR 0x0800
	54	#define GICD_SGIR 0x0F00
	55	#define GICD_CPENDSGIR 0x0F10
	56	#define GICD_SPENDSGIR 0x0F20
	57
021f6537	58	#define GICD_CTLR_RWP (1U << 31)
a0675c25	59	#define GICD_CTLR_DS (1U << 6)
021f6537 MZ	60	#define GICD_CTLR_ARE_NS (1U << 4)
	61	#define GICD_CTLR_ENABLE_G1A (1U << 1)
	62	#define GICD_CTLR_ENABLE_G1 (1U << 0)
	63
a0675c25 AP	64	/*
	65	* In systems with a single security state (what we emulate in KVM)
	66	* the meaning of the interrupt group enable bits is slightly different
	67	*/
	68	#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
	69	#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
	70
	71	#define GICD_TYPER_LPIS (1U << 17)
	72	#define GICD_TYPER_MBIS (1U << 16)
	73
f5c1434c MZ	74	#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
f5c1434c MZ	75	#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
f5c1434c	76
021f6537 MZ	77	#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
	78	#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
	79
	80	#define GIC_PIDR2_ARCH_MASK 0xf0
	81	#define GIC_PIDR2_ARCH_GICv3 0x30
	82	#define GIC_PIDR2_ARCH_GICv4 0x40
	83
a0675c25 AP	84	#define GIC_V3_DIST_SIZE 0x10000
a0675c25 AP	85
021f6537 MZ	86	/*
	87	* Re-Distributor registers, offsets from RD_base
	88	*/
	89	#define GICR_CTLR GICD_CTLR
	90	#define GICR_IIDR 0x0004
	91	#define GICR_TYPER 0x0008
	92	#define GICR_STATUSR GICD_STATUSR
	93	#define GICR_WAKER 0x0014
	94	#define GICR_SETLPIR 0x0040
	95	#define GICR_CLRLPIR 0x0048
	96	#define GICR_SEIR GICD_SEIR
	97	#define GICR_PROPBASER 0x0070
	98	#define GICR_PENDBASER 0x0078
	99	#define GICR_INVLPIR 0x00A0
	100	#define GICR_INVALLR 0x00B0
	101	#define GICR_SYNCR 0x00C0
	102	#define GICR_MOVLPIR 0x0100
	103	#define GICR_MOVALLR 0x0110
a0675c25	104	#define GICR_IDREGS GICD_IDREGS
021f6537 MZ	105	#define GICR_PIDR2 GICD_PIDR2
021f6537 MZ	106
cc2d3216 MZ	107	#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
	108
	109	#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
	110
021f6537 MZ	111	#define GICR_WAKER_ProcessorSleep (1U << 1)
	112	#define GICR_WAKER_ChildrenAsleep (1U << 2)
	113
645b9e49 AP	114	#define GIC_BASER_CACHE_nCnB 0ULL
	115	#define GIC_BASER_CACHE_SameAsInner 0ULL
	116	#define GIC_BASER_CACHE_nC 1ULL
	117	#define GIC_BASER_CACHE_RaWt 2ULL
	118	#define GIC_BASER_CACHE_RaWb 3ULL
	119	#define GIC_BASER_CACHE_WaWt 4ULL
	120	#define GIC_BASER_CACHE_WaWb 5ULL
	121	#define GIC_BASER_CACHE_RaWaWt 6ULL
	122	#define GIC_BASER_CACHE_RaWaWb 7ULL
	123	#define GIC_BASER_CACHE_MASK 7ULL
	124	#define GIC_BASER_NonShareable 0ULL
	125	#define GIC_BASER_InnerShareable 1ULL
	126	#define GIC_BASER_OuterShareable 2ULL
	127	#define GIC_BASER_SHAREABILITY_MASK 3ULL
	128
	129	#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
	130	(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
	131
	132	#define GIC_BASER_SHAREABILITY(reg, type) \
	133	(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
	134
	135	#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
	136	#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
	137	#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
	138	#define GICR_PROPBASER_SHAREABILITY_MASK \
	139	GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
	140	#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
	141	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
	142	#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
	143	GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
	144	#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
	145
	146	#define GICR_PROPBASER_InnerShareable \
	147	GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
8c828a53 MZ	148
	149	#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
	150	#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
	151	#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
	152	#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
	153	#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
	154	#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
	155	#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
	156	#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
	157
645b9e49 AP	158	#define GICR_PROPBASER_IDBITS_MASK (0x1f)
	159
	160	#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
	161	#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
	162	#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
	163	#define GICR_PENDBASER_SHAREABILITY_MASK \
	164	GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
	165	#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
	166	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
	167	#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
	168	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
	169	#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
	170
	171	#define GICR_PENDBASER_InnerShareable \
	172	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
8c828a53 MZ	173
	174	#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
	175	#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
	176	#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
	177	#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
	178	#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
	179	#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
	180	#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
	181	#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
	182
645b9e49	183	#define GICR_PENDBASER_PTZ BIT_ULL(62)
4ad3e363	184
021f6537 MZ	185	/*
	186	* Re-Distributor registers, offsets from SGI_base
	187	*/
a0675c25	188	#define GICR_IGROUPR0 GICD_IGROUPR
021f6537 MZ	189	#define GICR_ISENABLER0 GICD_ISENABLER
	190	#define GICR_ICENABLER0 GICD_ICENABLER
	191	#define GICR_ISPENDR0 GICD_ISPENDR
	192	#define GICR_ICPENDR0 GICD_ICPENDR
	193	#define GICR_ISACTIVER0 GICD_ISACTIVER
	194	#define GICR_ICACTIVER0 GICD_ICACTIVER
	195	#define GICR_IPRIORITYR0 GICD_IPRIORITYR
	196	#define GICR_ICFGR0 GICD_ICFGR
a0675c25 AP	197	#define GICR_IGRPMODR0 GICD_IGRPMODR
a0675c25 AP	198	#define GICR_NSACR GICD_NSACR
021f6537	199
cc2d3216	200	#define GICR_TYPER_PLPIS (1U << 0)
021f6537 MZ	201	#define GICR_TYPER_VLPIS (1U << 1)
	202	#define GICR_TYPER_LAST (1U << 4)
	203
a0675c25 AP	204	#define GIC_V3_REDIST_SIZE 0x20000
a0675c25 AP	205
cc2d3216 MZ	206	#define LPI_PROP_GROUP1 (1 << 1)
	207	#define LPI_PROP_ENABLED (1 << 0)
	208
	209	/*
	210	* ITS registers, offsets from ITS_base
	211	*/
	212	#define GITS_CTLR 0x0000
	213	#define GITS_IIDR 0x0004
	214	#define GITS_TYPER 0x0008
	215	#define GITS_CBASER 0x0080
	216	#define GITS_CWRITER 0x0088
	217	#define GITS_CREADR 0x0090
	218	#define GITS_BASER 0x0100
645b9e49 AP	219	#define GITS_IDREGS_BASE 0xffd0
	220	#define GITS_PIDR0 0xffe0
	221	#define GITS_PIDR1 0xffe4
cc2d3216	222	#define GITS_PIDR2 GICR_PIDR2
645b9e49 AP	223	#define GITS_PIDR4 0xffd0
	224	#define GITS_CIDR0 0xfff0
	225	#define GITS_CIDR1 0xfff4
	226	#define GITS_CIDR2 0xfff8
	227	#define GITS_CIDR3 0xfffc
cc2d3216 MZ	228
	229	#define GITS_TRANSLATER 0x10040
	230
7cb99116 YW	231	#define GITS_CTLR_ENABLE (1U << 0)
	232	#define GITS_CTLR_QUIESCENT (1U << 31)
	233
645b9e49 AP	234	#define GITS_TYPER_PLPIS (1UL << 0)
645b9e49 AP	235	#define GITS_TYPER_IDBITS_SHIFT 8
f54b97ed MZ	236	#define GITS_TYPER_DEVBITS_SHIFT 13
f54b97ed MZ	237	#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
cc2d3216	238	#define GITS_TYPER_PTA (1UL << 19)
645b9e49 AP	239	#define GITS_TYPER_HWCOLLCNT_SHIFT 24
645b9e49 AP	240
b11283eb	241	#define GITS_CBASER_VALID (1ULL << 63)
645b9e49 AP	242	#define GITS_CBASER_SHAREABILITY_SHIFT (10)
	243	#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
	244	#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
	245	#define GITS_CBASER_SHAREABILITY_MASK \
	246	GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
	247	#define GITS_CBASER_INNER_CACHEABILITY_MASK \
	248	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
	249	#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
	250	GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
	251	#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
	252
	253	#define GITS_CBASER_InnerShareable \
	254	GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
8c828a53 MZ	255
	256	#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
	257	#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
	258	#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
	259	#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
	260	#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
	261	#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
	262	#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
	263	#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
cc2d3216 MZ	264
	265	#define GITS_BASER_NR_REGS 8
	266
b11283eb	267	#define GITS_BASER_VALID (1ULL << 63)
645b9e49	268	#define GITS_BASER_INDIRECT (1ULL << 62)
8c828a53	269
645b9e49 AP	270	#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
	271	#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
	272	#define GITS_BASER_INNER_CACHEABILITY_MASK \
	273	GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
8c828a53	274	#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
645b9e49 AP	275	#define GITS_BASER_OUTER_CACHEABILITY_MASK \
	276	GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
	277	#define GITS_BASER_SHAREABILITY_MASK \
	278	GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
	279
8c828a53 MZ	280	#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
	281	#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
	282	#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
	283	#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
	284	#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
	285	#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
	286	#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
	287	#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
	288
645b9e49	289	#define GITS_BASER_TYPE_SHIFT (56)
cc2d3216	290	#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
645b9e49	291	#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
9224eb77	292	#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
cc2d3216	293	#define GITS_BASER_SHAREABILITY_SHIFT (10)
645b9e49 AP	294	#define GITS_BASER_InnerShareable \
645b9e49 AP	295	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
cc2d3216	296	#define GITS_BASER_PAGE_SIZE_SHIFT (8)
e29bd6f2 VM	297	#define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
	298	#define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
	299	#define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
	300	#define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
30f21363	301	#define GITS_BASER_PAGES_MAX 256
9347359a	302	#define GITS_BASER_PAGES_SHIFT (0)
645b9e49	303	#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
cc2d3216 MZ	304
	305	#define GITS_BASER_TYPE_NONE 0
	306	#define GITS_BASER_TYPE_DEVICE 1
	307	#define GITS_BASER_TYPE_VCPU 2
4f46de9d	308	#define GITS_BASER_TYPE_RESERVED3 3
cc2d3216 MZ	309	#define GITS_BASER_TYPE_COLLECTION 4
	310	#define GITS_BASER_TYPE_RESERVED5 5
	311	#define GITS_BASER_TYPE_RESERVED6 6
	312	#define GITS_BASER_TYPE_RESERVED7 7
	313
3faf24ea SD	314	#define GITS_LVL1_ENTRY_SIZE (8UL)
3faf24ea SD	315
cc2d3216 MZ	316	/*
	317	* ITS commands
	318	*/
	319	#define GITS_CMD_MAPD 0x08
	320	#define GITS_CMD_MAPC 0x09
645b9e49	321	#define GITS_CMD_MAPTI 0x0a
645b9e49	322	#define GITS_CMD_MAPI 0x0b
cc2d3216 MZ	323	#define GITS_CMD_MOVI 0x01
	324	#define GITS_CMD_DISCARD 0x0f
	325	#define GITS_CMD_INV 0x0c
	326	#define GITS_CMD_MOVALL 0x0e
	327	#define GITS_CMD_INVALL 0x0d
	328	#define GITS_CMD_INT 0x03
	329	#define GITS_CMD_CLEAR 0x04
	330	#define GITS_CMD_SYNC 0x05
	331
645b9e49 AP	332	/*
	333	* ITS error numbers
	334	*/
	335	#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
	336	#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
fd837b08	337	#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
645b9e49 AP	338	#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
	339	#define E_ITS_MAPD_DEVICE_OOR 0x010801
	340	#define E_ITS_MAPC_PROCNUM_OOR 0x010902
	341	#define E_ITS_MAPC_COLLECTION_OOR 0x010903
	342	#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
	343	#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
	344	#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
	345	#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
	346	#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
	347	#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
	348
021f6537 MZ	349	/*
	350	* CPU interface registers
	351	*/
5c341537 VK	352	#define ICC_CTLR_EL1_EOImode_SHIFT (1)
	353	#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
	354	#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
	355	#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
	356	#define ICC_CTLR_EL1_CBPR_SHIFT 0
	357	#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
	358	#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
	359	#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
	360	#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
	361	#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
	362	#define ICC_CTLR_EL1_SEIS_SHIFT 14
	363	#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
	364	#define ICC_CTLR_EL1_A3V_SHIFT 15
	365	#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
	366	#define ICC_PMR_EL1_SHIFT 0
	367	#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
	368	#define ICC_BPR0_EL1_SHIFT 0
	369	#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
	370	#define ICC_BPR1_EL1_SHIFT 0
	371	#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
	372	#define ICC_IGRPEN0_EL1_SHIFT 0
	373	#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
	374	#define ICC_IGRPEN1_EL1_SHIFT 0
	375	#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
4dfc0505 MZ	376	#define ICC_SRE_EL1_DIB (1U << 2)
4dfc0505 MZ	377	#define ICC_SRE_EL1_DFB (1U << 1)
021f6537 MZ	378	#define ICC_SRE_EL1_SRE (1U << 0)
	379
	380	/*
	381	* Hypervisor interface registers (SRE only)
	382	*/
f6c86a41 JPB	383	#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
	384
	385	#define ICH_LR_EOI (1ULL << 41)
	386	#define ICH_LR_GROUP (1ULL << 60)
	387	#define ICH_LR_HW (1ULL << 61)
	388	#define ICH_LR_STATE (3ULL << 62)
	389	#define ICH_LR_PENDING_BIT (1ULL << 62)
	390	#define ICH_LR_ACTIVE_BIT (1ULL << 63)
fb182cf8	391	#define ICH_LR_PHYS_ID_SHIFT 32
f6c86a41	392	#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
59529f69	393	#define ICH_LR_PRIORITY_SHIFT 48
021f6537	394
44bfc42e AP	395	/* These are for GICv2 emulation only */
	396	#define GICH_LR_VIRTUALID (0x3ffUL << 0)
	397	#define GICH_LR_PHYSID_CPUID_SHIFT (10)
	398	#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
021f6537 MZ	399
	400	#define ICH_MISR_EOI (1 << 0)
	401	#define ICH_MISR_U (1 << 1)
	402
	403	#define ICH_HCR_EN (1 << 0)
	404	#define ICH_HCR_UIE (1 << 1)
	405
5c341537 VK	406	#define ICH_VMCR_CBPR_SHIFT 4
	407	#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
	408	#define ICH_VMCR_EOIM_SHIFT 9
	409	#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
021f6537 MZ	410	#define ICH_VMCR_BPR1_SHIFT 18
	411	#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
	412	#define ICH_VMCR_BPR0_SHIFT 21
	413	#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
	414	#define ICH_VMCR_PMR_SHIFT 24
	415	#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
5c341537 VK	416	#define ICH_VMCR_ENG0_SHIFT 0
	417	#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
	418	#define ICH_VMCR_ENG1_SHIFT 1
	419	#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
	420
	421	#define ICH_VTR_PRI_BITS_SHIFT 29
	422	#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
	423	#define ICH_VTR_ID_BITS_SHIFT 23
	424	#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
	425	#define ICH_VTR_SEIS_SHIFT 22
	426	#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
	427	#define ICH_VTR_A3V_SHIFT 21
	428	#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
021f6537	429
021f6537 MZ	430	#define ICC_IAR1_EL1_SPURIOUS 0x3ff
021f6537 MZ	431
021f6537 MZ	432	#define ICC_SRE_EL2_SRE (1 << 0)
	433	#define ICC_SRE_EL2_ENABLE (1 << 3)
	434
7e580278 AP	435	#define ICC_SGI1R_TARGET_LIST_SHIFT 0
	436	#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
	437	#define ICC_SGI1R_AFFINITY_1_SHIFT 16
	438	#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
	439	#define ICC_SGI1R_SGI_ID_SHIFT 24
dd5f1b04	440	#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
7e580278	441	#define ICC_SGI1R_AFFINITY_2_SHIFT 32
fab0cdc3	442	#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
7e580278 AP	443	#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
7e580278 AP	444	#define ICC_SGI1R_AFFINITY_3_SHIFT 48
fab0cdc3	445	#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
7e580278	446
7936e914	447	#include <asm/arch_gicv3.h>
021f6537 MZ	448
	449	#ifndef __ASSEMBLY__
	450
b48ac83d MZ	451	/*
	452	* We need a value to serve as a irq-type for LPIs. Choose one that will
	453	* hopefully pique the interest of the reviewer.
	454	*/
	455	#define GIC_IRQ_TYPE_LPI 0xa110c8ed
	456
f5c1434c MZ	457	struct rdists {
	458	struct {
	459	void __iomem *rd_base;
	460	struct page *pend_page;
	461	phys_addr_t phys_base;
	462	} __percpu *rdist;
	463	struct page *prop_page;
	464	int id_bits;
	465	u64 flags;
	466	};
	467
7936e914	468	struct irq_domain;
db40f0a7	469	struct fwnode_handle;
7936e914	470	int its_cpu_init(void);
db40f0a7	471	int its_init(struct fwnode_handle handle, struct rdists rdists,
7936e914	472	struct irq_domain *domain);
0b6a3da9	473
7cabd008 MZ	474	static inline bool gic_enable_sre(void)
7cabd008 MZ	475	{
7936e914	476	u32 val;
7cabd008	477
7936e914	478	val = gic_read_sre();
7cabd008 MZ	479	if (val & ICC_SRE_EL1_SRE)
	480	return true;
	481
	482	val \|= ICC_SRE_EL1_SRE;
7936e914 JPB	483	gic_write_sre(val);
7936e914 JPB	484	val = gic_read_sre();
7cabd008 MZ	485
	486	return !!(val & ICC_SRE_EL1_SRE);
	487	}
	488
021f6537 MZ	489	#endif
	490
	491	#endif