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f27ecacc | 1 | /* |
520f7bd7 | 2 | * include/linux/irqchip/arm-gic.h |
f27ecacc RK |
3 | * |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
520f7bd7 RH |
10 | #ifndef __LINUX_IRQCHIP_ARM_GIC_H |
11 | #define __LINUX_IRQCHIP_ARM_GIC_H | |
f27ecacc | 12 | |
f27ecacc RK |
13 | #define GIC_CPU_CTRL 0x00 |
14 | #define GIC_CPU_PRIMASK 0x04 | |
15 | #define GIC_CPU_BINPOINT 0x08 | |
16 | #define GIC_CPU_INTACK 0x0c | |
17 | #define GIC_CPU_EOI 0x10 | |
18 | #define GIC_CPU_RUNNINGPRI 0x14 | |
19 | #define GIC_CPU_HIGHPRI 0x18 | |
20 | ||
21 | #define GIC_DIST_CTRL 0x000 | |
22 | #define GIC_DIST_CTR 0x004 | |
7c7945a8 | 23 | #define GIC_DIST_IGROUP 0x080 |
f27ecacc RK |
24 | #define GIC_DIST_ENABLE_SET 0x100 |
25 | #define GIC_DIST_ENABLE_CLEAR 0x180 | |
26 | #define GIC_DIST_PENDING_SET 0x200 | |
27 | #define GIC_DIST_PENDING_CLEAR 0x280 | |
7c7945a8 CD |
28 | #define GIC_DIST_ACTIVE_SET 0x300 |
29 | #define GIC_DIST_ACTIVE_CLEAR 0x380 | |
f27ecacc RK |
30 | #define GIC_DIST_PRI 0x400 |
31 | #define GIC_DIST_TARGET 0x800 | |
32 | #define GIC_DIST_CONFIG 0xc00 | |
33 | #define GIC_DIST_SOFTINT 0xf00 | |
34 | ||
4294f8ba RH |
35 | struct device_node; |
36 | ||
d7ed36a4 | 37 | extern struct irq_chip gic_arch_extn; |
ff2e27ae | 38 | |
db0d4db2 | 39 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, |
75294957 | 40 | u32 offset, struct device_node *); |
38489533 | 41 | void gic_secondary_init(unsigned int); |
b3a1bde4 | 42 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
e807acbc | 43 | |
db0d4db2 MZ |
44 | static inline void gic_init(unsigned int nr, int start, |
45 | void __iomem *dist , void __iomem *cpu) | |
46 | { | |
75294957 | 47 | gic_init_bases(nr, start, dist, cpu, 0, NULL); |
db0d4db2 MZ |
48 | } |
49 | ||
f27ecacc | 50 | #endif |