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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
08a543ad GL |
2 | /* |
3 | * irq_domain - IRQ translation domains | |
4 | * | |
5 | * Translation infrastructure between hw and linux irq numbers. This is | |
6 | * helpful for interrupt controllers to implement mapping between hardware | |
7 | * irq numbers and the Linux irq number space. | |
8 | * | |
e7a46c81 MZ |
9 | * irq_domains also have hooks for translating device tree or other |
10 | * firmware interrupt representations into a hardware irq number that | |
11 | * can be mapped back to a Linux irq number without any extra platform | |
12 | * support code. | |
08a543ad | 13 | * |
7bb69bad GL |
14 | * Interrupt controller "domain" data structure. This could be defined as a |
15 | * irq domain controller. That is, it handles the mapping between hardware | |
16 | * and virtual interrupt numbers for a given interrupt domain. The domain | |
17 | * structure is generally created by the PIC code for a given PIC instance | |
18 | * (though a domain can cover more than one PIC if they have a flat number | |
19 | * model). It's the domain callbacks that are responsible for setting the | |
20 | * irq_chip on a given irq_desc after it's been mapped. | |
cc79ca69 | 21 | * |
e7a46c81 MZ |
22 | * The host code and data structures use a fwnode_handle pointer to |
23 | * identify the domain. In some cases, and in order to preserve source | |
24 | * code compatibility, this fwnode pointer is "upgraded" to a DT | |
25 | * device_node. For those firmware infrastructures that do not provide | |
26 | * a unique identifier for an interrupt controller, the irq_domain | |
27 | * code offers a fwnode allocator. | |
08a543ad | 28 | */ |
7bb69bad | 29 | |
08a543ad GL |
30 | #ifndef _LINUX_IRQDOMAIN_H |
31 | #define _LINUX_IRQDOMAIN_H | |
32 | ||
7bb69bad | 33 | #include <linux/types.h> |
1b537708 | 34 | #include <linux/irqhandler.h> |
f110711a | 35 | #include <linux/of.h> |
f1d78358 | 36 | #include <linux/mutex.h> |
7bb69bad | 37 | #include <linux/radix-tree.h> |
08a543ad | 38 | |
08a543ad | 39 | struct device_node; |
08219fb1 | 40 | struct fwnode_handle; |
08a543ad | 41 | struct irq_domain; |
f8264e34 JL |
42 | struct irq_chip; |
43 | struct irq_data; | |
06ee6d57 | 44 | struct cpumask; |
c3e7239a | 45 | struct seq_file; |
bec04037 | 46 | struct irq_affinity_desc; |
7bb69bad | 47 | |
1bc04f2c GL |
48 | /* Number of irqs reserved for a legacy isa controller */ |
49 | #define NUM_ISA_INTERRUPTS 16 | |
50 | ||
11e4438e MZ |
51 | #define IRQ_DOMAIN_IRQ_SPEC_PARAMS 16 |
52 | ||
53 | /** | |
54 | * struct irq_fwspec - generic IRQ specifier structure | |
55 | * | |
56 | * @fwnode: Pointer to a firmware-specific descriptor | |
57 | * @param_count: Number of device-specific parameters | |
58 | * @param: Device-specific parameters | |
59 | * | |
60 | * This structure, directly modeled after of_phandle_args, is used to | |
61 | * pass a device-specific description of an interrupt. | |
62 | */ | |
63 | struct irq_fwspec { | |
64 | struct fwnode_handle *fwnode; | |
65 | int param_count; | |
66 | u32 param[IRQ_DOMAIN_IRQ_SPEC_PARAMS]; | |
67 | }; | |
68 | ||
ad3aedfb MZ |
69 | /* |
70 | * Should several domains have the same device node, but serve | |
71 | * different purposes (for example one domain is for PCI/MSI, and the | |
72 | * other for wired IRQs), they can be distinguished using a | |
73 | * bus-specific token. Most domains are expected to only carry | |
74 | * DOMAIN_BUS_ANY. | |
75 | */ | |
76 | enum irq_domain_bus_token { | |
77 | DOMAIN_BUS_ANY = 0, | |
530cbe10 | 78 | DOMAIN_BUS_WIRED, |
61ce8d8d | 79 | DOMAIN_BUS_GENERIC_MSI, |
0380839d | 80 | DOMAIN_BUS_PCI_MSI, |
c706c239 | 81 | DOMAIN_BUS_PLATFORM_MSI, |
a5716070 | 82 | DOMAIN_BUS_NEXUS, |
29d5c8db | 83 | DOMAIN_BUS_IPI, |
9b1b282c | 84 | DOMAIN_BUS_FSL_MC_MSI, |
49b32315 | 85 | DOMAIN_BUS_TI_SCI_INTA_MSI, |
d46bca2b | 86 | DOMAIN_BUS_WAKEUP, |
c6c9e283 | 87 | DOMAIN_BUS_VMD_MSI, |
ad3aedfb MZ |
88 | }; |
89 | ||
08a543ad GL |
90 | /** |
91 | * struct irq_domain_ops - Methods for irq_domain objects | |
7bb69bad GL |
92 | * @match: Match an interrupt controller device node to a host, returns |
93 | * 1 on a match | |
94 | * @map: Create or update a mapping between a virtual irq number and a hw | |
95 | * irq number. This is called only once for a given mapping. | |
96 | * @unmap: Dispose of such a mapping | |
7bb69bad GL |
97 | * @xlate: Given a device tree node and interrupt specifier, decode |
98 | * the hardware irq number and linux irq type value. | |
99 | * | |
100 | * Functions below are provided by the driver and called whenever a new mapping | |
101 | * is created or an old mapping is disposed. The driver can then proceed to | |
102 | * whatever internal data structures management is required. It also needs | |
103 | * to setup the irq_desc when returning from map(). | |
08a543ad GL |
104 | */ |
105 | struct irq_domain_ops { | |
ad3aedfb MZ |
106 | int (*match)(struct irq_domain *d, struct device_node *node, |
107 | enum irq_domain_bus_token bus_token); | |
651e8b54 MZ |
108 | int (*select)(struct irq_domain *d, struct irq_fwspec *fwspec, |
109 | enum irq_domain_bus_token bus_token); | |
7bb69bad GL |
110 | int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw); |
111 | void (*unmap)(struct irq_domain *d, unsigned int virq); | |
7bb69bad GL |
112 | int (*xlate)(struct irq_domain *d, struct device_node *node, |
113 | const u32 *intspec, unsigned int intsize, | |
114 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 JL |
115 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
116 | /* extended V2 interfaces to support hierarchy irq_domains */ | |
117 | int (*alloc)(struct irq_domain *d, unsigned int virq, | |
118 | unsigned int nr_irqs, void *arg); | |
119 | void (*free)(struct irq_domain *d, unsigned int virq, | |
120 | unsigned int nr_irqs); | |
702cb0a0 | 121 | int (*activate)(struct irq_domain *d, struct irq_data *irqd, bool reserve); |
f8264e34 | 122 | void (*deactivate)(struct irq_domain *d, struct irq_data *irq_data); |
11e4438e MZ |
123 | int (*translate)(struct irq_domain *d, struct irq_fwspec *fwspec, |
124 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 | 125 | #endif |
c3e7239a TG |
126 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
127 | void (*debug_show)(struct seq_file *m, struct irq_domain *d, | |
128 | struct irq_data *irqd, int ind); | |
129 | #endif | |
08a543ad GL |
130 | }; |
131 | ||
088f40b7 TG |
132 | extern struct irq_domain_ops irq_generic_chip_ops; |
133 | ||
134 | struct irq_domain_chip_generic; | |
135 | ||
08a543ad GL |
136 | /** |
137 | * struct irq_domain - Hardware interrupt number translation object | |
7bb69bad | 138 | * @link: Element in global irq_domain list. |
1aa0dd94 | 139 | * @name: Name of interrupt domain |
7bb69bad GL |
140 | * @ops: pointer to irq_domain methods |
141 | * @host_data: private data pointer for use by owner. Not touched by irq_domain | |
142 | * core code. | |
f8264e34 | 143 | * @flags: host per irq_domain flags |
9dc6be3d | 144 | * @mapcount: The number of mapped interrupts |
1aa0dd94 GL |
145 | * |
146 | * Optional elements | |
4b821300 DL |
147 | * @fwnode: Pointer to firmware node associated with the irq_domain. Pretty easy |
148 | * to swap it for the of_node via the irq_domain_get_of_node accessor | |
1aa0dd94 GL |
149 | * @gc: Pointer to a list of generic chips. There is a helper function for |
150 | * setting up one or more generic chips for interrupt controllers | |
151 | * drivers using the generic chip library which uses this pointer. | |
f8264e34 | 152 | * @parent: Pointer to parent irq_domain to support hierarchy irq_domains |
087cdfb6 | 153 | * @debugfs_file: dentry for the domain debugfs file |
1aa0dd94 GL |
154 | * |
155 | * Revmap data, used internally by irq_domain | |
156 | * @revmap_direct_max_irq: The largest hwirq that can be set for controllers that | |
157 | * support direct mapping | |
158 | * @revmap_size: Size of the linear map table @linear_revmap[] | |
159 | * @revmap_tree: Radix map tree for hwirqs that don't fit in the linear map | |
160 | * @linear_revmap: Linear table of hwirq->virq reverse mappings | |
08a543ad GL |
161 | */ |
162 | struct irq_domain { | |
7bb69bad | 163 | struct list_head link; |
0bb4afb4 | 164 | const char *name; |
a18dc81b | 165 | const struct irq_domain_ops *ops; |
7bb69bad | 166 | void *host_data; |
f8264e34 | 167 | unsigned int flags; |
9dc6be3d | 168 | unsigned int mapcount; |
7bb69bad | 169 | |
1aa0dd94 | 170 | /* Optional data */ |
f110711a | 171 | struct fwnode_handle *fwnode; |
ad3aedfb | 172 | enum irq_domain_bus_token bus_token; |
088f40b7 | 173 | struct irq_domain_chip_generic *gc; |
f8264e34 JL |
174 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
175 | struct irq_domain *parent; | |
176 | #endif | |
087cdfb6 TG |
177 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
178 | struct dentry *debugfs_file; | |
179 | #endif | |
cef5075c | 180 | |
1aa0dd94 | 181 | /* reverse map data. The linear map gets appended to the irq_domain */ |
ddaf144c | 182 | irq_hw_number_t hwirq_max; |
1aa0dd94 GL |
183 | unsigned int revmap_direct_max_irq; |
184 | unsigned int revmap_size; | |
185 | struct radix_tree_root revmap_tree; | |
f1d78358 | 186 | struct mutex revmap_tree_mutex; |
cef5075c | 187 | unsigned int linear_revmap[]; |
08a543ad GL |
188 | }; |
189 | ||
f8264e34 JL |
190 | /* Irq domain flags */ |
191 | enum { | |
192 | /* Irq domain is hierarchical */ | |
193 | IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0), | |
194 | ||
6a6544e5 | 195 | /* Irq domain name was allocated in __irq_domain_add() */ |
2546287c | 196 | IRQ_DOMAIN_NAME_ALLOCATED = (1 << 1), |
36d72731 | 197 | |
0abefbaa QY |
198 | /* Irq domain is an IPI domain with virq per cpu */ |
199 | IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2), | |
200 | ||
201 | /* Irq domain is an IPI domain with single virq */ | |
202 | IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3), | |
203 | ||
631a9639 EA |
204 | /* Irq domain implements MSIs */ |
205 | IRQ_DOMAIN_FLAG_MSI = (1 << 4), | |
206 | ||
207 | /* Irq domain implements MSI remapping */ | |
208 | IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5), | |
209 | ||
6f1a4891 TG |
210 | /* |
211 | * Quirk to handle MSI implementations which do not provide | |
212 | * masking. Currently known to affect x86, but partially | |
213 | * handled in core code. | |
214 | */ | |
215 | IRQ_DOMAIN_MSI_NOMASK_QUIRK = (1 << 6), | |
216 | ||
f8264e34 JL |
217 | /* |
218 | * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved | |
219 | * for implementation specific purposes and ignored by the | |
220 | * core code. | |
221 | */ | |
222 | IRQ_DOMAIN_FLAG_NONCORE = (1 << 16), | |
223 | }; | |
224 | ||
10abc7df MZ |
225 | static inline struct device_node *irq_domain_get_of_node(struct irq_domain *d) |
226 | { | |
f110711a | 227 | return to_of_node(d->fwnode); |
10abc7df MZ |
228 | } |
229 | ||
7bb69bad | 230 | #ifdef CONFIG_IRQ_DOMAIN |
d59f6617 | 231 | struct fwnode_handle *__irq_domain_alloc_fwnode(unsigned int type, int id, |
b977fcf4 | 232 | const char *name, phys_addr_t *pa); |
d59f6617 TG |
233 | |
234 | enum { | |
235 | IRQCHIP_FWNODE_REAL, | |
236 | IRQCHIP_FWNODE_NAMED, | |
237 | IRQCHIP_FWNODE_NAMED_ID, | |
238 | }; | |
239 | ||
240 | static inline | |
241 | struct fwnode_handle *irq_domain_alloc_named_fwnode(const char *name) | |
242 | { | |
243 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED, 0, name, NULL); | |
244 | } | |
245 | ||
246 | static inline | |
247 | struct fwnode_handle *irq_domain_alloc_named_id_fwnode(const char *name, int id) | |
248 | { | |
249 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED_ID, id, name, | |
250 | NULL); | |
251 | } | |
252 | ||
b977fcf4 | 253 | static inline struct fwnode_handle *irq_domain_alloc_fwnode(phys_addr_t *pa) |
d59f6617 | 254 | { |
b977fcf4 | 255 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_REAL, 0, NULL, pa); |
d59f6617 TG |
256 | } |
257 | ||
b145dcc4 | 258 | void irq_domain_free_fwnode(struct fwnode_handle *fwnode); |
1bf4ddc4 | 259 | struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size, |
ddaf144c | 260 | irq_hw_number_t hwirq_max, int direct_max, |
fa40f377 GL |
261 | const struct irq_domain_ops *ops, |
262 | void *host_data); | |
781d0f46 MB |
263 | struct irq_domain *irq_domain_add_simple(struct device_node *of_node, |
264 | unsigned int size, | |
265 | unsigned int first_irq, | |
266 | const struct irq_domain_ops *ops, | |
267 | void *host_data); | |
a8db8cf0 | 268 | struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, |
1bc04f2c GL |
269 | unsigned int size, |
270 | unsigned int first_irq, | |
271 | irq_hw_number_t first_hwirq, | |
a18dc81b | 272 | const struct irq_domain_ops *ops, |
a8db8cf0 | 273 | void *host_data); |
b6e95788 AS |
274 | struct irq_domain *irq_domain_create_legacy(struct fwnode_handle *fwnode, |
275 | unsigned int size, | |
276 | unsigned int first_irq, | |
277 | irq_hw_number_t first_hwirq, | |
278 | const struct irq_domain_ops *ops, | |
279 | void *host_data); | |
651e8b54 | 280 | extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec, |
130b8c6c | 281 | enum irq_domain_bus_token bus_token); |
c7b41f0a | 282 | extern bool irq_domain_check_msi_remap(void); |
fa40f377 | 283 | extern void irq_set_default_host(struct irq_domain *host); |
9f199dd3 | 284 | extern struct irq_domain *irq_get_default_host(void); |
ac0a0cd2 | 285 | extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, |
06ee6d57 | 286 | irq_hw_number_t hwirq, int node, |
bec04037 | 287 | const struct irq_affinity_desc *affinity); |
fa40f377 | 288 | |
1bf4ddc4 MZ |
289 | static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) |
290 | { | |
291 | return node ? &node->fwnode : NULL; | |
292 | } | |
293 | ||
db3e50f3 SA |
294 | extern const struct fwnode_operations irqchip_fwnode_ops; |
295 | ||
75aba7b0 SS |
296 | static inline bool is_fwnode_irqchip(struct fwnode_handle *fwnode) |
297 | { | |
db3e50f3 | 298 | return fwnode && fwnode->ops == &irqchip_fwnode_ops; |
75aba7b0 SS |
299 | } |
300 | ||
61d0a000 MZ |
301 | extern void irq_domain_update_bus_token(struct irq_domain *domain, |
302 | enum irq_domain_bus_token bus_token); | |
303 | ||
651e8b54 MZ |
304 | static inline |
305 | struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, | |
306 | enum irq_domain_bus_token bus_token) | |
307 | { | |
308 | struct irq_fwspec fwspec = { | |
309 | .fwnode = fwnode, | |
310 | }; | |
311 | ||
312 | return irq_find_matching_fwspec(&fwspec, bus_token); | |
313 | } | |
314 | ||
130b8c6c MZ |
315 | static inline struct irq_domain *irq_find_matching_host(struct device_node *node, |
316 | enum irq_domain_bus_token bus_token) | |
317 | { | |
1bf4ddc4 | 318 | return irq_find_matching_fwnode(of_node_to_fwnode(node), bus_token); |
130b8c6c MZ |
319 | } |
320 | ||
ad3aedfb MZ |
321 | static inline struct irq_domain *irq_find_host(struct device_node *node) |
322 | { | |
64619343 MZ |
323 | struct irq_domain *d; |
324 | ||
325 | d = irq_find_matching_host(node, DOMAIN_BUS_WIRED); | |
326 | if (!d) | |
327 | d = irq_find_matching_host(node, DOMAIN_BUS_ANY); | |
328 | ||
329 | return d; | |
ad3aedfb MZ |
330 | } |
331 | ||
fa40f377 GL |
332 | /** |
333 | * irq_domain_add_linear() - Allocate and register a linear revmap irq_domain. | |
334 | * @of_node: pointer to interrupt controller's device tree node. | |
335 | * @size: Number of interrupts in the domain. | |
336 | * @ops: map/unmap domain callbacks | |
337 | * @host_data: Controller private data pointer | |
338 | */ | |
339 | static inline struct irq_domain *irq_domain_add_linear(struct device_node *of_node, | |
a8db8cf0 | 340 | unsigned int size, |
a18dc81b | 341 | const struct irq_domain_ops *ops, |
fa40f377 GL |
342 | void *host_data) |
343 | { | |
1bf4ddc4 | 344 | return __irq_domain_add(of_node_to_fwnode(of_node), size, size, 0, ops, host_data); |
fa40f377 GL |
345 | } |
346 | static inline struct irq_domain *irq_domain_add_nomap(struct device_node *of_node, | |
6fa6c8e2 | 347 | unsigned int max_irq, |
a18dc81b | 348 | const struct irq_domain_ops *ops, |
fa40f377 GL |
349 | void *host_data) |
350 | { | |
1bf4ddc4 | 351 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, max_irq, max_irq, ops, host_data); |
fa40f377 | 352 | } |
1bc04f2c GL |
353 | static inline struct irq_domain *irq_domain_add_legacy_isa( |
354 | struct device_node *of_node, | |
a18dc81b | 355 | const struct irq_domain_ops *ops, |
1bc04f2c GL |
356 | void *host_data) |
357 | { | |
358 | return irq_domain_add_legacy(of_node, NUM_ISA_INTERRUPTS, 0, 0, ops, | |
359 | host_data); | |
360 | } | |
cef5075c GL |
361 | static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_node, |
362 | const struct irq_domain_ops *ops, | |
363 | void *host_data) | |
364 | { | |
1bf4ddc4 MZ |
365 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, ~0, 0, ops, host_data); |
366 | } | |
367 | ||
368 | static inline struct irq_domain *irq_domain_create_linear(struct fwnode_handle *fwnode, | |
369 | unsigned int size, | |
370 | const struct irq_domain_ops *ops, | |
371 | void *host_data) | |
372 | { | |
373 | return __irq_domain_add(fwnode, size, size, 0, ops, host_data); | |
374 | } | |
375 | ||
376 | static inline struct irq_domain *irq_domain_create_tree(struct fwnode_handle *fwnode, | |
377 | const struct irq_domain_ops *ops, | |
378 | void *host_data) | |
379 | { | |
380 | return __irq_domain_add(fwnode, 0, ~0, 0, ops, host_data); | |
cef5075c | 381 | } |
58ee99ad PM |
382 | |
383 | extern void irq_domain_remove(struct irq_domain *host); | |
384 | ||
ddaf144c GL |
385 | extern int irq_domain_associate(struct irq_domain *domain, unsigned int irq, |
386 | irq_hw_number_t hwirq); | |
387 | extern void irq_domain_associate_many(struct irq_domain *domain, | |
388 | unsigned int irq_base, | |
389 | irq_hw_number_t hwirq_base, int count); | |
98aa468e | 390 | |
bb4c6910 LV |
391 | extern unsigned int irq_create_mapping_affinity(struct irq_domain *host, |
392 | irq_hw_number_t hwirq, | |
393 | const struct irq_affinity_desc *affinity); | |
c0131f09 | 394 | extern unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec); |
cc79ca69 | 395 | extern void irq_dispose_mapping(unsigned int virq); |
d3dcb436 | 396 | |
bb4c6910 LV |
397 | static inline unsigned int irq_create_mapping(struct irq_domain *host, |
398 | irq_hw_number_t hwirq) | |
399 | { | |
400 | return irq_create_mapping_affinity(host, hwirq, NULL); | |
401 | } | |
402 | ||
403 | ||
d3dcb436 GL |
404 | /** |
405 | * irq_linear_revmap() - Find a linux irq from a hw irq number. | |
406 | * @domain: domain owning this hardware interrupt | |
407 | * @hwirq: hardware irq number in that domain space | |
408 | * | |
409 | * This is a fast path alternative to irq_find_mapping() that can be | |
410 | * called directly by irq controller code to save a handful of | |
411 | * instructions. It is always safe to call, but won't find irqs mapped | |
412 | * using the radix tree. | |
413 | */ | |
414 | static inline unsigned int irq_linear_revmap(struct irq_domain *domain, | |
415 | irq_hw_number_t hwirq) | |
416 | { | |
417 | return hwirq < domain->revmap_size ? domain->linear_revmap[hwirq] : 0; | |
418 | } | |
cc79ca69 GL |
419 | extern unsigned int irq_find_mapping(struct irq_domain *host, |
420 | irq_hw_number_t hwirq); | |
421 | extern unsigned int irq_create_direct_mapping(struct irq_domain *host); | |
98aa468e GL |
422 | extern int irq_create_strict_mappings(struct irq_domain *domain, |
423 | unsigned int irq_base, | |
424 | irq_hw_number_t hwirq_base, int count); | |
425 | ||
426 | static inline int irq_create_identity_mapping(struct irq_domain *host, | |
427 | irq_hw_number_t hwirq) | |
428 | { | |
429 | return irq_create_strict_mappings(host, hwirq, hwirq, 1); | |
430 | } | |
431 | ||
a18dc81b | 432 | extern const struct irq_domain_ops irq_domain_simple_ops; |
16b2e6e2 GL |
433 | |
434 | /* stock xlate functions */ | |
435 | int irq_domain_xlate_onecell(struct irq_domain *d, struct device_node *ctrlr, | |
436 | const u32 *intspec, unsigned int intsize, | |
437 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
438 | int irq_domain_xlate_twocell(struct irq_domain *d, struct device_node *ctrlr, | |
439 | const u32 *intspec, unsigned int intsize, | |
440 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
441 | int irq_domain_xlate_onetwocell(struct irq_domain *d, struct device_node *ctrlr, | |
442 | const u32 *intspec, unsigned int intsize, | |
443 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
444 | ||
b5c231d8 BM |
445 | int irq_domain_translate_twocell(struct irq_domain *d, |
446 | struct irq_fwspec *fwspec, | |
447 | unsigned long *out_hwirq, | |
448 | unsigned int *out_type); | |
449 | ||
b01eccea YS |
450 | int irq_domain_translate_onecell(struct irq_domain *d, |
451 | struct irq_fwspec *fwspec, | |
452 | unsigned long *out_hwirq, | |
453 | unsigned int *out_type); | |
454 | ||
d17bf24e | 455 | /* IPI functions */ |
7cec18a3 MR |
456 | int irq_reserve_ipi(struct irq_domain *domain, const struct cpumask *dest); |
457 | int irq_destroy_ipi(unsigned int irq, const struct cpumask *dest); | |
d17bf24e | 458 | |
f8264e34 JL |
459 | /* V2 interfaces to support hierarchy IRQ domains. */ |
460 | extern struct irq_data *irq_domain_get_irq_data(struct irq_domain *domain, | |
461 | unsigned int virq); | |
5f22f5c6 SA |
462 | extern void irq_domain_set_info(struct irq_domain *domain, unsigned int virq, |
463 | irq_hw_number_t hwirq, struct irq_chip *chip, | |
464 | void *chip_data, irq_flow_handler_t handler, | |
465 | void *handler_data, const char *handler_name); | |
5c8f77a2 | 466 | extern void irq_domain_reset_irq_data(struct irq_data *irq_data); |
f8264e34 | 467 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
2a5e9a07 | 468 | extern struct irq_domain *irq_domain_create_hierarchy(struct irq_domain *parent, |
afb7da83 | 469 | unsigned int flags, unsigned int size, |
2a5e9a07 | 470 | struct fwnode_handle *fwnode, |
afb7da83 | 471 | const struct irq_domain_ops *ops, void *host_data); |
2a5e9a07 MZ |
472 | |
473 | static inline struct irq_domain *irq_domain_add_hierarchy(struct irq_domain *parent, | |
474 | unsigned int flags, | |
475 | unsigned int size, | |
476 | struct device_node *node, | |
477 | const struct irq_domain_ops *ops, | |
478 | void *host_data) | |
479 | { | |
480 | return irq_domain_create_hierarchy(parent, flags, size, | |
481 | of_node_to_fwnode(node), | |
482 | ops, host_data); | |
483 | } | |
484 | ||
f8264e34 JL |
485 | extern int __irq_domain_alloc_irqs(struct irq_domain *domain, int irq_base, |
486 | unsigned int nr_irqs, int node, void *arg, | |
bec04037 DL |
487 | bool realloc, |
488 | const struct irq_affinity_desc *affinity); | |
f8264e34 | 489 | extern void irq_domain_free_irqs(unsigned int virq, unsigned int nr_irqs); |
42e1cc2d | 490 | extern int irq_domain_activate_irq(struct irq_data *irq_data, bool early); |
f8264e34 JL |
491 | extern void irq_domain_deactivate_irq(struct irq_data *irq_data); |
492 | ||
493 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, | |
494 | unsigned int nr_irqs, int node, void *arg) | |
495 | { | |
06ee6d57 TG |
496 | return __irq_domain_alloc_irqs(domain, -1, nr_irqs, node, arg, false, |
497 | NULL); | |
f8264e34 JL |
498 | } |
499 | ||
6a6544e5 | 500 | extern int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain, |
c466595c MZ |
501 | unsigned int irq_base, |
502 | unsigned int nr_irqs, void *arg); | |
f8264e34 JL |
503 | extern int irq_domain_set_hwirq_and_chip(struct irq_domain *domain, |
504 | unsigned int virq, | |
505 | irq_hw_number_t hwirq, | |
506 | struct irq_chip *chip, | |
507 | void *chip_data); | |
f8264e34 JL |
508 | extern void irq_domain_free_irqs_common(struct irq_domain *domain, |
509 | unsigned int virq, | |
510 | unsigned int nr_irqs); | |
511 | extern void irq_domain_free_irqs_top(struct irq_domain *domain, | |
512 | unsigned int virq, unsigned int nr_irqs); | |
513 | ||
495c38d3 DD |
514 | extern int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg); |
515 | extern int irq_domain_pop_irq(struct irq_domain *domain, int virq); | |
516 | ||
36d72731 JL |
517 | extern int irq_domain_alloc_irqs_parent(struct irq_domain *domain, |
518 | unsigned int irq_base, | |
519 | unsigned int nr_irqs, void *arg); | |
f8264e34 | 520 | |
36d72731 JL |
521 | extern void irq_domain_free_irqs_parent(struct irq_domain *domain, |
522 | unsigned int irq_base, | |
523 | unsigned int nr_irqs); | |
f8264e34 | 524 | |
55567976 MZ |
525 | extern int irq_domain_disconnect_hierarchy(struct irq_domain *domain, |
526 | unsigned int virq); | |
527 | ||
f8264e34 JL |
528 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
529 | { | |
530 | return domain->flags & IRQ_DOMAIN_FLAG_HIERARCHY; | |
531 | } | |
0abefbaa QY |
532 | |
533 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
534 | { | |
535 | return domain->flags & | |
536 | (IRQ_DOMAIN_FLAG_IPI_PER_CPU | IRQ_DOMAIN_FLAG_IPI_SINGLE); | |
537 | } | |
538 | ||
539 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
540 | { | |
541 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_PER_CPU; | |
542 | } | |
543 | ||
544 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
545 | { | |
546 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE; | |
547 | } | |
631a9639 EA |
548 | |
549 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
550 | { | |
551 | return domain->flags & IRQ_DOMAIN_FLAG_MSI; | |
552 | } | |
553 | ||
554 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
555 | { | |
556 | return domain->flags & IRQ_DOMAIN_FLAG_MSI_REMAP; | |
557 | } | |
558 | ||
559 | extern bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain); | |
560 | ||
f8264e34 | 561 | #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
f8264e34 JL |
562 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, |
563 | unsigned int nr_irqs, int node, void *arg) | |
564 | { | |
565 | return -1; | |
566 | } | |
567 | ||
1e2a7d78 JH |
568 | static inline void irq_domain_free_irqs(unsigned int virq, |
569 | unsigned int nr_irqs) { } | |
570 | ||
f8264e34 JL |
571 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
572 | { | |
573 | return false; | |
574 | } | |
0abefbaa QY |
575 | |
576 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
577 | { | |
578 | return false; | |
579 | } | |
580 | ||
581 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
582 | { | |
583 | return false; | |
584 | } | |
585 | ||
586 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
587 | { | |
588 | return false; | |
589 | } | |
631a9639 EA |
590 | |
591 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
592 | { | |
593 | return false; | |
594 | } | |
595 | ||
596 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
597 | { | |
598 | return false; | |
599 | } | |
600 | ||
601 | static inline bool | |
602 | irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain) | |
603 | { | |
604 | return false; | |
605 | } | |
f8264e34 JL |
606 | #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
607 | ||
d593f25f GL |
608 | #else /* CONFIG_IRQ_DOMAIN */ |
609 | static inline void irq_dispose_mapping(unsigned int virq) { } | |
471036b2 SS |
610 | static inline struct irq_domain *irq_find_matching_fwnode( |
611 | struct fwnode_handle *fwnode, enum irq_domain_bus_token bus_token) | |
612 | { | |
613 | return NULL; | |
614 | } | |
b3e22847 MYK |
615 | static inline bool irq_domain_check_msi_remap(void) |
616 | { | |
617 | return false; | |
618 | } | |
d593f25f | 619 | #endif /* !CONFIG_IRQ_DOMAIN */ |
7e713301 | 620 | |
08a543ad | 621 | #endif /* _LINUX_IRQDOMAIN_H */ |