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b94d5230 DW |
1 | /* |
2 | * libnvdimm - Non-volatile-memory Devices Subsystem | |
3 | * | |
4 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of version 2 of the GNU General Public License as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | */ | |
15 | #ifndef __LIBNVDIMM_H__ | |
16 | #define __LIBNVDIMM_H__ | |
047fc8a1 | 17 | #include <linux/kernel.h> |
62232e45 DW |
18 | #include <linux/sizes.h> |
19 | #include <linux/types.h> | |
faec6f8a | 20 | #include <linux/uuid.h> |
aa9ad44a DJ |
21 | #include <linux/spinlock.h> |
22 | ||
23 | struct badrange_entry { | |
24 | u64 start; | |
25 | u64 length; | |
26 | struct list_head list; | |
27 | }; | |
28 | ||
29 | struct badrange { | |
30 | struct list_head list; | |
31 | spinlock_t lock; | |
32 | }; | |
e6dfb2de DW |
33 | |
34 | enum { | |
35 | /* when a dimm supports both PMEM and BLK access a label is required */ | |
8f078b38 | 36 | NDD_ALIASING = 0, |
58138820 | 37 | /* unarmed memory devices may not persist writes */ |
8f078b38 DW |
38 | NDD_UNARMED = 1, |
39 | /* locked memory devices should not be accessed */ | |
40 | NDD_LOCKED = 2, | |
62232e45 DW |
41 | |
42 | /* need to set a limit somewhere, but yes, this is likely overkill */ | |
43 | ND_IOCTL_MAX_BUFLEN = SZ_4M, | |
4577b066 | 44 | ND_CMD_MAX_ELEM = 5, |
40abf9be | 45 | ND_CMD_MAX_ENVELOPE = 256, |
1f7df6f8 | 46 | ND_MAX_MAPPINGS = 32, |
1b40e09a | 47 | |
004f1afb DW |
48 | /* region flag indicating to direct-map persistent memory by default */ |
49 | ND_REGION_PAGEMAP = 0, | |
06e8ccda DJ |
50 | /* |
51 | * Platform ensures entire CPU store data path is flushed to pmem on | |
52 | * system power loss. | |
53 | */ | |
54 | ND_REGION_PERSIST_CACHE = 1, | |
30e6d7bf DJ |
55 | /* |
56 | * Platform provides mechanisms to automatically flush outstanding | |
57 | * write data from memory controler to pmem on system power loss. | |
58 | * (ADR) | |
59 | */ | |
60 | ND_REGION_PERSIST_MEMCTRL = 2, | |
004f1afb | 61 | |
1b40e09a DW |
62 | /* mark newly adjusted resources as requiring a label update */ |
63 | DPA_RESOURCE_ADJUSTED = 1 << 0, | |
e6dfb2de DW |
64 | }; |
65 | ||
45def22c | 66 | extern struct attribute_group nvdimm_bus_attribute_group; |
62232e45 | 67 | extern struct attribute_group nvdimm_attribute_group; |
4d88a97a | 68 | extern struct attribute_group nd_device_attribute_group; |
74ae66c3 | 69 | extern struct attribute_group nd_numa_attribute_group; |
1f7df6f8 DW |
70 | extern struct attribute_group nd_region_attribute_group; |
71 | extern struct attribute_group nd_mapping_attribute_group; | |
45def22c | 72 | |
b94d5230 DW |
73 | struct nvdimm; |
74 | struct nvdimm_bus_descriptor; | |
75 | typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc, | |
76 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, | |
aef25338 | 77 | unsigned int buf_len, int *cmd_rc); |
b94d5230 | 78 | |
1ff19f48 | 79 | struct device_node; |
b94d5230 | 80 | struct nvdimm_bus_descriptor { |
45def22c | 81 | const struct attribute_group **attr_groups; |
7db5bb33 | 82 | unsigned long bus_dsm_mask; |
e3654eca | 83 | unsigned long cmd_mask; |
bc9775d8 | 84 | struct module *module; |
b94d5230 | 85 | char *provider_name; |
1ff19f48 | 86 | struct device_node *of_node; |
b94d5230 | 87 | ndctl_fn ndctl; |
7ae0fa43 | 88 | int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc); |
87bf572e | 89 | int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc, |
b3ed2ce0 | 90 | struct nvdimm *nvdimm, unsigned int cmd, void *data); |
b94d5230 DW |
91 | }; |
92 | ||
62232e45 DW |
93 | struct nd_cmd_desc { |
94 | int in_num; | |
95 | int out_num; | |
96 | u32 in_sizes[ND_CMD_MAX_ELEM]; | |
97 | int out_sizes[ND_CMD_MAX_ELEM]; | |
98 | }; | |
99 | ||
eaf96153 | 100 | struct nd_interleave_set { |
c12c48ce DW |
101 | /* v1.1 definition of the interleave-set-cookie algorithm */ |
102 | u64 cookie1; | |
103 | /* v1.2 definition of the interleave-set-cookie algorithm */ | |
104 | u64 cookie2; | |
86ef58a4 DW |
105 | /* compatibility with initial buggy Linux implementation */ |
106 | u64 altcookie; | |
faec6f8a DW |
107 | |
108 | guid_t type_guid; | |
eaf96153 DW |
109 | }; |
110 | ||
44c462eb DW |
111 | struct nd_mapping_desc { |
112 | struct nvdimm *nvdimm; | |
113 | u64 start; | |
114 | u64 size; | |
401c0a19 | 115 | int position; |
44c462eb DW |
116 | }; |
117 | ||
1f7df6f8 DW |
118 | struct nd_region_desc { |
119 | struct resource *res; | |
44c462eb | 120 | struct nd_mapping_desc *mapping; |
1f7df6f8 DW |
121 | u16 num_mappings; |
122 | const struct attribute_group **attr_groups; | |
eaf96153 | 123 | struct nd_interleave_set *nd_set; |
1f7df6f8 | 124 | void *provider_data; |
5212e11f | 125 | int num_lanes; |
41d7a6d6 | 126 | int numa_node; |
004f1afb | 127 | unsigned long flags; |
1ff19f48 | 128 | struct device_node *of_node; |
1f7df6f8 DW |
129 | }; |
130 | ||
29b9aa0a DW |
131 | struct device; |
132 | void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset, | |
133 | size_t size, unsigned long flags); | |
134 | static inline void __iomem *devm_nvdimm_ioremap(struct device *dev, | |
135 | resource_size_t offset, size_t size) | |
136 | { | |
137 | return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0); | |
138 | } | |
139 | ||
62232e45 | 140 | struct nvdimm_bus; |
3d88002e | 141 | struct module; |
047fc8a1 RZ |
142 | struct device; |
143 | struct nd_blk_region; | |
144 | struct nd_blk_region_desc { | |
145 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); | |
047fc8a1 RZ |
146 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
147 | void *iobuf, u64 len, int rw); | |
148 | struct nd_region_desc ndr_desc; | |
149 | }; | |
150 | ||
151 | static inline struct nd_blk_region_desc *to_blk_region_desc( | |
152 | struct nd_region_desc *ndr_desc) | |
153 | { | |
154 | return container_of(ndr_desc, struct nd_blk_region_desc, ndr_desc); | |
155 | ||
156 | } | |
157 | ||
f2989396 DJ |
158 | enum nvdimm_security_state { |
159 | NVDIMM_SECURITY_DISABLED, | |
160 | NVDIMM_SECURITY_UNLOCKED, | |
161 | NVDIMM_SECURITY_LOCKED, | |
162 | NVDIMM_SECURITY_FROZEN, | |
163 | NVDIMM_SECURITY_OVERWRITE, | |
164 | }; | |
165 | ||
166 | struct nvdimm_security_ops { | |
167 | enum nvdimm_security_state (*state)(struct nvdimm *nvdimm); | |
37833fb7 | 168 | int (*freeze)(struct nvdimm *nvdimm); |
f2989396 DJ |
169 | }; |
170 | ||
aa9ad44a DJ |
171 | void badrange_init(struct badrange *badrange); |
172 | int badrange_add(struct badrange *badrange, u64 addr, u64 length); | |
173 | void badrange_forget(struct badrange *badrange, phys_addr_t start, | |
174 | unsigned int len); | |
175 | int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr, | |
176 | u64 length); | |
bc9775d8 DW |
177 | struct nvdimm_bus *nvdimm_bus_register(struct device *parent, |
178 | struct nvdimm_bus_descriptor *nfit_desc); | |
b94d5230 | 179 | void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus); |
45def22c | 180 | struct nvdimm_bus *to_nvdimm_bus(struct device *dev); |
f2989396 | 181 | struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm); |
e6dfb2de | 182 | struct nvdimm *to_nvdimm(struct device *dev); |
1f7df6f8 | 183 | struct nd_region *to_nd_region(struct device *dev); |
243f29fe | 184 | struct device *nd_region_dev(struct nd_region *nd_region); |
047fc8a1 | 185 | struct nd_blk_region *to_nd_blk_region(struct device *dev); |
45def22c | 186 | struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus); |
37b137ff | 187 | struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus); |
e6dfb2de | 188 | const char *nvdimm_name(struct nvdimm *nvdimm); |
ba9c8dd3 | 189 | struct kobject *nvdimm_kobj(struct nvdimm *nvdimm); |
e3654eca | 190 | unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm); |
e6dfb2de | 191 | void *nvdimm_provider_data(struct nvdimm *nvdimm); |
d6548ae4 DJ |
192 | struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
193 | void *provider_data, const struct attribute_group **groups, | |
194 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
f2989396 DJ |
195 | struct resource *flush_wpq, const char *dimm_id, |
196 | const struct nvdimm_security_ops *sec_ops); | |
d6548ae4 DJ |
197 | static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
198 | void *provider_data, const struct attribute_group **groups, | |
199 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
200 | struct resource *flush_wpq) | |
201 | { | |
202 | return __nvdimm_create(nvdimm_bus, provider_data, groups, flags, | |
f2989396 | 203 | cmd_mask, num_flush, flush_wpq, NULL, NULL); |
d6548ae4 DJ |
204 | } |
205 | ||
62232e45 DW |
206 | const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd); |
207 | const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd); | |
208 | u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd, | |
209 | const struct nd_cmd_desc *desc, int idx, void *buf); | |
210 | u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd, | |
211 | const struct nd_cmd_desc *desc, int idx, const u32 *in_field, | |
efda1b5d | 212 | const u32 *out_field, unsigned long remainder); |
4d88a97a | 213 | int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count); |
1f7df6f8 DW |
214 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, |
215 | struct nd_region_desc *ndr_desc); | |
216 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, | |
217 | struct nd_region_desc *ndr_desc); | |
218 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, | |
219 | struct nd_region_desc *ndr_desc); | |
047fc8a1 RZ |
220 | void *nd_region_provider_data(struct nd_region *nd_region); |
221 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr); | |
222 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data); | |
223 | struct nvdimm *nd_blk_region_to_dimm(struct nd_blk_region *ndbr); | |
ca6a4657 | 224 | unsigned long nd_blk_memremap_flags(struct nd_blk_region *ndbr); |
047fc8a1 RZ |
225 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region); |
226 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); | |
eaf96153 | 227 | u64 nd_fletcher64(void *addr, size_t len, bool le); |
f284a4f2 DW |
228 | void nvdimm_flush(struct nd_region *nd_region); |
229 | int nvdimm_has_flush(struct nd_region *nd_region); | |
0b277961 | 230 | int nvdimm_has_cache(struct nd_region *nd_region); |
5deb67f7 | 231 | |
f2989396 DJ |
232 | static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
233 | unsigned int buf_len, int *cmd_rc) | |
234 | { | |
235 | struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm); | |
236 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
237 | ||
238 | return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); | |
239 | } | |
240 | ||
5deb67f7 RM |
241 | #ifdef CONFIG_ARCH_HAS_PMEM_API |
242 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WB | |
243 | void arch_wb_cache_pmem(void *addr, size_t size); | |
244 | void arch_invalidate_pmem(void *addr, size_t size); | |
245 | #else | |
246 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WT | |
247 | static inline void arch_wb_cache_pmem(void *addr, size_t size) | |
248 | { | |
249 | } | |
250 | static inline void arch_invalidate_pmem(void *addr, size_t size) | |
251 | { | |
252 | } | |
253 | #endif | |
254 | ||
b94d5230 | 255 | #endif /* __LIBNVDIMM_H__ */ |