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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
cd9e9808 MB |
2 | #ifndef NVM_H |
3 | #define NVM_H | |
4 | ||
b76eb20b | 5 | #include <linux/blkdev.h> |
a7fd9a4f | 6 | #include <linux/types.h> |
b76eb20b | 7 | #include <uapi/linux/lightnvm.h> |
a7fd9a4f | 8 | |
cd9e9808 MB |
9 | enum { |
10 | NVM_IO_OK = 0, | |
11 | NVM_IO_REQUEUE = 1, | |
12 | NVM_IO_DONE = 2, | |
13 | NVM_IO_ERR = 3, | |
14 | ||
15 | NVM_IOTYPE_NONE = 0, | |
16 | NVM_IOTYPE_GC = 1, | |
17 | }; | |
18 | ||
a7fd9a4f JA |
19 | #define NVM_BLK_BITS (16) |
20 | #define NVM_PG_BITS (16) | |
21 | #define NVM_SEC_BITS (8) | |
22 | #define NVM_PL_BITS (8) | |
23 | #define NVM_LUN_BITS (8) | |
df414b33 | 24 | #define NVM_CH_BITS (7) |
a7fd9a4f JA |
25 | |
26 | struct ppa_addr { | |
27 | /* Generic structure for all addresses */ | |
28 | union { | |
29 | struct { | |
30 | u64 blk : NVM_BLK_BITS; | |
31 | u64 pg : NVM_PG_BITS; | |
32 | u64 sec : NVM_SEC_BITS; | |
33 | u64 pl : NVM_PL_BITS; | |
34 | u64 lun : NVM_LUN_BITS; | |
35 | u64 ch : NVM_CH_BITS; | |
df414b33 | 36 | u64 reserved : 1; |
a7fd9a4f JA |
37 | } g; |
38 | ||
df414b33 MB |
39 | struct { |
40 | u64 line : 63; | |
41 | u64 is_cached : 1; | |
42 | } c; | |
43 | ||
a7fd9a4f JA |
44 | u64 ppa; |
45 | }; | |
46 | }; | |
47 | ||
48 | struct nvm_rq; | |
49 | struct nvm_id; | |
50 | struct nvm_dev; | |
8e53624d | 51 | struct nvm_tgt_dev; |
a7fd9a4f | 52 | |
a7fd9a4f | 53 | typedef int (nvm_id_fn)(struct nvm_dev *, struct nvm_id *); |
e11903f5 | 54 | typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *); |
00ee6cc3 | 55 | typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int); |
a7fd9a4f | 56 | typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); |
1a94b2d4 | 57 | typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *); |
a7fd9a4f JA |
58 | typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *); |
59 | typedef void (nvm_destroy_dma_pool_fn)(void *); | |
60 | typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t, | |
61 | dma_addr_t *); | |
62 | typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t); | |
63 | ||
64 | struct nvm_dev_ops { | |
65 | nvm_id_fn *identity; | |
a7fd9a4f JA |
66 | nvm_op_bb_tbl_fn *get_bb_tbl; |
67 | nvm_op_set_bb_fn *set_bb_tbl; | |
68 | ||
69 | nvm_submit_io_fn *submit_io; | |
1a94b2d4 | 70 | nvm_submit_io_sync_fn *submit_io_sync; |
a7fd9a4f JA |
71 | |
72 | nvm_create_dma_pool_fn *create_dma_pool; | |
73 | nvm_destroy_dma_pool_fn *destroy_dma_pool; | |
74 | nvm_dev_dma_alloc_fn *dev_dma_alloc; | |
75 | nvm_dev_dma_free_fn *dev_dma_free; | |
76 | ||
77 | unsigned int max_phys_sect; | |
78 | }; | |
79 | ||
cd9e9808 MB |
80 | #ifdef CONFIG_NVM |
81 | ||
82 | #include <linux/blkdev.h> | |
cd9e9808 MB |
83 | #include <linux/file.h> |
84 | #include <linux/dmapool.h> | |
e3eb3799 | 85 | #include <uapi/linux/lightnvm.h> |
cd9e9808 MB |
86 | |
87 | enum { | |
88 | /* HW Responsibilities */ | |
89 | NVM_RSP_L2P = 1 << 0, | |
90 | NVM_RSP_ECC = 1 << 1, | |
91 | ||
92 | /* Physical Adressing Mode */ | |
93 | NVM_ADDRMODE_LINEAR = 0, | |
94 | NVM_ADDRMODE_CHANNEL = 1, | |
95 | ||
96 | /* Plane programming mode for LUN */ | |
d5bdec8d MB |
97 | NVM_PLANE_SINGLE = 1, |
98 | NVM_PLANE_DOUBLE = 2, | |
99 | NVM_PLANE_QUAD = 4, | |
cd9e9808 MB |
100 | |
101 | /* Status codes */ | |
102 | NVM_RSP_SUCCESS = 0x0, | |
103 | NVM_RSP_NOT_CHANGEABLE = 0x1, | |
104 | NVM_RSP_ERR_FAILWRITE = 0x40ff, | |
105 | NVM_RSP_ERR_EMPTYPAGE = 0x42ff, | |
402ab9a8 | 106 | NVM_RSP_ERR_FAILECC = 0x4281, |
38ea2f76 | 107 | NVM_RSP_ERR_FAILCRC = 0x4004, |
402ab9a8 | 108 | NVM_RSP_WARN_HIGHECC = 0x4700, |
cd9e9808 MB |
109 | |
110 | /* Device opcodes */ | |
cd9e9808 MB |
111 | NVM_OP_PWRITE = 0x91, |
112 | NVM_OP_PREAD = 0x92, | |
113 | NVM_OP_ERASE = 0x90, | |
114 | ||
115 | /* PPA Command Flags */ | |
116 | NVM_IO_SNGL_ACCESS = 0x0, | |
117 | NVM_IO_DUAL_ACCESS = 0x1, | |
118 | NVM_IO_QUAD_ACCESS = 0x2, | |
119 | ||
57b4bd06 | 120 | /* NAND Access Modes */ |
cd9e9808 MB |
121 | NVM_IO_SUSPEND = 0x80, |
122 | NVM_IO_SLC_MODE = 0x100, | |
a7737f39 | 123 | NVM_IO_SCRAMBLE_ENABLE = 0x200, |
57b4bd06 MB |
124 | |
125 | /* Block Types */ | |
126 | NVM_BLK_T_FREE = 0x0, | |
127 | NVM_BLK_T_BAD = 0x1, | |
b5d4acd4 MB |
128 | NVM_BLK_T_GRWN_BAD = 0x2, |
129 | NVM_BLK_T_DEV = 0x4, | |
130 | NVM_BLK_T_HOST = 0x8, | |
f9a99950 MB |
131 | |
132 | /* Memory capabilities */ | |
133 | NVM_ID_CAP_SLC = 0x1, | |
134 | NVM_ID_CAP_CMD_SUSPEND = 0x2, | |
135 | NVM_ID_CAP_SCRAMBLE = 0x4, | |
136 | NVM_ID_CAP_ENCRYPT = 0x8, | |
ca5927e7 MB |
137 | |
138 | /* Memory types */ | |
139 | NVM_ID_FMTYPE_SLC = 0, | |
140 | NVM_ID_FMTYPE_MLC = 1, | |
bf643185 MB |
141 | |
142 | /* Device capabilities */ | |
143 | NVM_ID_DCAP_BBLKMGMT = 0x1, | |
144 | NVM_UD_DCAP_ECC = 0x2, | |
ca5927e7 MB |
145 | }; |
146 | ||
147 | struct nvm_id_lp_mlc { | |
148 | u16 num_pairs; | |
149 | u8 pairs[886]; | |
150 | }; | |
151 | ||
152 | struct nvm_id_lp_tbl { | |
153 | __u8 id[8]; | |
154 | struct nvm_id_lp_mlc mlc; | |
cd9e9808 MB |
155 | }; |
156 | ||
157 | struct nvm_id_group { | |
158 | u8 mtype; | |
159 | u8 fmtype; | |
cd9e9808 MB |
160 | u8 num_ch; |
161 | u8 num_lun; | |
162 | u8 num_pln; | |
163 | u16 num_blk; | |
164 | u16 num_pg; | |
165 | u16 fpg_sz; | |
166 | u16 csecs; | |
167 | u16 sos; | |
168 | u32 trdt; | |
169 | u32 trdm; | |
170 | u32 tprt; | |
171 | u32 tprm; | |
172 | u32 tbet; | |
173 | u32 tbem; | |
174 | u32 mpos; | |
12be5edf | 175 | u32 mccap; |
cd9e9808 | 176 | u16 cpar; |
73387e7b | 177 | }; |
cd9e9808 MB |
178 | |
179 | struct nvm_addr_format { | |
180 | u8 ch_offset; | |
181 | u8 ch_len; | |
182 | u8 lun_offset; | |
183 | u8 lun_len; | |
184 | u8 pln_offset; | |
185 | u8 pln_len; | |
186 | u8 blk_offset; | |
187 | u8 blk_len; | |
188 | u8 pg_offset; | |
189 | u8 pg_len; | |
190 | u8 sect_offset; | |
191 | u8 sect_len; | |
cd9e9808 MB |
192 | }; |
193 | ||
194 | struct nvm_id { | |
195 | u8 ver_id; | |
196 | u8 vmnt; | |
cd9e9808 MB |
197 | u32 cap; |
198 | u32 dom; | |
199 | struct nvm_addr_format ppaf; | |
19bd6fe7 | 200 | struct nvm_id_group grp; |
cd9e9808 MB |
201 | } __packed; |
202 | ||
203 | struct nvm_target { | |
204 | struct list_head list; | |
8e79b5cb | 205 | struct nvm_tgt_dev *dev; |
cd9e9808 MB |
206 | struct nvm_tgt_type *type; |
207 | struct gendisk *disk; | |
208 | }; | |
209 | ||
cd9e9808 MB |
210 | #define ADDR_EMPTY (~0ULL) |
211 | ||
212 | #define NVM_VERSION_MAJOR 1 | |
213 | #define NVM_VERSION_MINOR 0 | |
214 | #define NVM_VERSION_PATCH 0 | |
215 | ||
91276162 | 216 | struct nvm_rq; |
72d256ec | 217 | typedef void (nvm_end_io_fn)(struct nvm_rq *); |
91276162 | 218 | |
cd9e9808 | 219 | struct nvm_rq { |
8e53624d | 220 | struct nvm_tgt_dev *dev; |
cd9e9808 MB |
221 | |
222 | struct bio *bio; | |
223 | ||
224 | union { | |
225 | struct ppa_addr ppa_addr; | |
226 | dma_addr_t dma_ppa_list; | |
227 | }; | |
228 | ||
229 | struct ppa_addr *ppa_list; | |
230 | ||
003fad37 JG |
231 | void *meta_list; |
232 | dma_addr_t dma_meta_list; | |
cd9e9808 | 233 | |
91276162 MB |
234 | nvm_end_io_fn *end_io; |
235 | ||
cd9e9808 | 236 | uint8_t opcode; |
6d5be959 | 237 | uint16_t nr_ppas; |
cd9e9808 | 238 | uint16_t flags; |
72d256ec | 239 | |
9f867268 | 240 | u64 ppa_status; /* ppa media status */ |
72d256ec | 241 | int error; |
06894efe MB |
242 | |
243 | void *private; | |
cd9e9808 MB |
244 | }; |
245 | ||
246 | static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu) | |
247 | { | |
248 | return pdu - sizeof(struct nvm_rq); | |
249 | } | |
250 | ||
251 | static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata) | |
252 | { | |
253 | return rqdata + 1; | |
254 | } | |
255 | ||
ff0e498b JG |
256 | enum { |
257 | NVM_BLK_ST_FREE = 0x1, /* Free block */ | |
077d2389 | 258 | NVM_BLK_ST_TGT = 0x2, /* Block in use by target */ |
ff0e498b | 259 | NVM_BLK_ST_BAD = 0x8, /* Bad block */ |
cd9e9808 MB |
260 | }; |
261 | ||
8e79b5cb JG |
262 | /* Device generic information */ |
263 | struct nvm_geo { | |
cd9e9808 | 264 | int nr_chnls; |
8e79b5cb JG |
265 | int nr_luns; |
266 | int luns_per_chnl; /* -1 if channels are not symmetric */ | |
cd9e9808 | 267 | int nr_planes; |
cd9e9808 MB |
268 | int sec_per_pg; /* only sectors for a single page */ |
269 | int pgs_per_blk; | |
270 | int blks_per_lun; | |
4891d120 MB |
271 | int fpg_size; |
272 | int pfpg_size; /* size of buffer if all pages are to be read */ | |
cd9e9808 MB |
273 | int sec_size; |
274 | int oob_size; | |
f9a99950 | 275 | int mccap; |
7386af27 | 276 | struct nvm_addr_format ppaf; |
cd9e9808 MB |
277 | |
278 | /* Calculated/Cached values. These do not reflect the actual usable | |
279 | * blocks at run-time. | |
280 | */ | |
281 | int max_rq_size; | |
282 | int plane_mode; /* drive device in single, double or quad mode */ | |
283 | ||
284 | int sec_per_pl; /* all sectors across planes */ | |
285 | int sec_per_blk; | |
286 | int sec_per_lun; | |
8e79b5cb JG |
287 | }; |
288 | ||
ade69e24 | 289 | /* sub-device structure */ |
8e79b5cb JG |
290 | struct nvm_tgt_dev { |
291 | /* Device information */ | |
292 | struct nvm_geo geo; | |
293 | ||
8e53624d JG |
294 | /* Base ppas for target LUNs */ |
295 | struct ppa_addr *luns; | |
296 | ||
8e79b5cb JG |
297 | sector_t total_secs; |
298 | ||
299 | struct nvm_id identity; | |
300 | struct request_queue *q; | |
301 | ||
959e911b | 302 | struct nvm_dev *parent; |
8e53624d | 303 | void *map; |
8e79b5cb JG |
304 | }; |
305 | ||
306 | struct nvm_dev { | |
307 | struct nvm_dev_ops *ops; | |
308 | ||
309 | struct list_head devices; | |
310 | ||
8e79b5cb JG |
311 | /* Device information */ |
312 | struct nvm_geo geo; | |
cd9e9808 | 313 | |
4ece44af | 314 | unsigned long total_secs; |
cd9e9808 | 315 | |
da1e2849 | 316 | unsigned long *lun_map; |
75b85649 | 317 | void *dma_pool; |
cd9e9808 MB |
318 | |
319 | struct nvm_id identity; | |
320 | ||
321 | /* Backend device */ | |
322 | struct request_queue *q; | |
323 | char name[DISK_NAME_LEN]; | |
40267efd | 324 | void *private_data; |
e3eb3799 | 325 | |
8e53624d JG |
326 | void *rmap; |
327 | ||
e3eb3799 | 328 | struct mutex mlock; |
4c9dacb8 | 329 | spinlock_t lock; |
ade69e24 MB |
330 | |
331 | /* target management */ | |
332 | struct list_head area_list; | |
333 | struct list_head targets; | |
cd9e9808 MB |
334 | }; |
335 | ||
dab8ee9e MB |
336 | static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, |
337 | struct ppa_addr r) | |
cd9e9808 | 338 | { |
dab8ee9e | 339 | struct nvm_geo *geo = &tgt_dev->geo; |
cd9e9808 MB |
340 | struct ppa_addr l; |
341 | ||
8e79b5cb JG |
342 | l.ppa = ((u64)r.g.blk) << geo->ppaf.blk_offset; |
343 | l.ppa |= ((u64)r.g.pg) << geo->ppaf.pg_offset; | |
344 | l.ppa |= ((u64)r.g.sec) << geo->ppaf.sect_offset; | |
345 | l.ppa |= ((u64)r.g.pl) << geo->ppaf.pln_offset; | |
346 | l.ppa |= ((u64)r.g.lun) << geo->ppaf.lun_offset; | |
347 | l.ppa |= ((u64)r.g.ch) << geo->ppaf.ch_offset; | |
cd9e9808 MB |
348 | |
349 | return l; | |
350 | } | |
351 | ||
dab8ee9e MB |
352 | static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, |
353 | struct ppa_addr r) | |
cd9e9808 | 354 | { |
dab8ee9e | 355 | struct nvm_geo *geo = &tgt_dev->geo; |
cd9e9808 MB |
356 | struct ppa_addr l; |
357 | ||
5389a1df | 358 | l.ppa = 0; |
7386af27 MB |
359 | /* |
360 | * (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc. | |
361 | */ | |
8e79b5cb JG |
362 | l.g.blk = (r.ppa >> geo->ppaf.blk_offset) & |
363 | (((1 << geo->ppaf.blk_len) - 1)); | |
364 | l.g.pg |= (r.ppa >> geo->ppaf.pg_offset) & | |
365 | (((1 << geo->ppaf.pg_len) - 1)); | |
366 | l.g.sec |= (r.ppa >> geo->ppaf.sect_offset) & | |
367 | (((1 << geo->ppaf.sect_len) - 1)); | |
368 | l.g.pl |= (r.ppa >> geo->ppaf.pln_offset) & | |
369 | (((1 << geo->ppaf.pln_len) - 1)); | |
370 | l.g.lun |= (r.ppa >> geo->ppaf.lun_offset) & | |
371 | (((1 << geo->ppaf.lun_len) - 1)); | |
372 | l.g.ch |= (r.ppa >> geo->ppaf.ch_offset) & | |
373 | (((1 << geo->ppaf.ch_len) - 1)); | |
cd9e9808 MB |
374 | |
375 | return l; | |
376 | } | |
377 | ||
dece1635 | 378 | typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *); |
cd9e9808 | 379 | typedef sector_t (nvm_tgt_capacity_fn)(void *); |
4af3f75d JG |
380 | typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *, |
381 | int flags); | |
cd9e9808 | 382 | typedef void (nvm_tgt_exit_fn)(void *); |
9a69b0ed JG |
383 | typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *); |
384 | typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *); | |
cd9e9808 MB |
385 | |
386 | struct nvm_tgt_type { | |
387 | const char *name; | |
388 | unsigned int version[3]; | |
389 | ||
390 | /* target entry points */ | |
391 | nvm_tgt_make_rq_fn *make_rq; | |
392 | nvm_tgt_capacity_fn *capacity; | |
cd9e9808 MB |
393 | |
394 | /* module-specific init/teardown */ | |
395 | nvm_tgt_init_fn *init; | |
396 | nvm_tgt_exit_fn *exit; | |
397 | ||
9a69b0ed JG |
398 | /* sysfs */ |
399 | nvm_tgt_sysfs_init_fn *sysfs_init; | |
400 | nvm_tgt_sysfs_exit_fn *sysfs_exit; | |
401 | ||
cd9e9808 MB |
402 | /* For internal use */ |
403 | struct list_head list; | |
90014829 | 404 | struct module *owner; |
cd9e9808 MB |
405 | }; |
406 | ||
6063fe39 SL |
407 | extern int nvm_register_tgt_type(struct nvm_tgt_type *); |
408 | extern void nvm_unregister_tgt_type(struct nvm_tgt_type *); | |
cd9e9808 MB |
409 | |
410 | extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *); | |
411 | extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t); | |
412 | ||
b0b4e09c MB |
413 | extern struct nvm_dev *nvm_alloc_dev(int); |
414 | extern int nvm_register(struct nvm_dev *); | |
415 | extern void nvm_unregister(struct nvm_dev *); | |
cd9e9808 | 416 | |
333ba053 JG |
417 | extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *, |
418 | int, int); | |
a279006a | 419 | extern int nvm_max_phys_sects(struct nvm_tgt_dev *); |
8e53624d | 420 | extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *); |
1a94b2d4 | 421 | extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *); |
06894efe | 422 | extern void nvm_end_io(struct nvm_rq *); |
22e8c976 | 423 | extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int); |
333ba053 | 424 | extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *); |
e3eb3799 | 425 | |
cd9e9808 MB |
426 | #else /* CONFIG_NVM */ |
427 | struct nvm_dev_ops; | |
428 | ||
b0b4e09c MB |
429 | static inline struct nvm_dev *nvm_alloc_dev(int node) |
430 | { | |
431 | return ERR_PTR(-EINVAL); | |
432 | } | |
433 | static inline int nvm_register(struct nvm_dev *dev) | |
cd9e9808 MB |
434 | { |
435 | return -EINVAL; | |
436 | } | |
b0b4e09c | 437 | static inline void nvm_unregister(struct nvm_dev *dev) {} |
cd9e9808 MB |
438 | #endif /* CONFIG_NVM */ |
439 | #endif /* LIGHTNVM.H */ |