[mirror_ubuntu-jammy-kernel.git] / include / linux / lightnvm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef NVM_H
#define NVM_H

#include <linux/blkdev.h>
#include <linux/types.h>
#include <uapi/linux/lightnvm.h>

enum {
	NVM_IO_OK = 0,
	NVM_IO_REQUEUE = 1,
	NVM_IO_DONE = 2,
	NVM_IO_ERR = 3,

	NVM_IOTYPE_NONE = 0,
	NVM_IOTYPE_GC = 1,
};

/* common format */
#define NVM_GEN_CH_BITS  (8)
#define NVM_GEN_LUN_BITS (8)
#define NVM_GEN_BLK_BITS (16)
#define NVM_GEN_RESERVED (32)

/* 1.2 format */
#define NVM_12_PG_BITS  (16)
#define NVM_12_PL_BITS  (4)
#define NVM_12_SEC_BITS (4)
#define NVM_12_RESERVED (8)

/* 2.0 format */
#define NVM_20_SEC_BITS (24)
#define NVM_20_RESERVED (8)

enum {
	NVM_OCSSD_SPEC_12 = 12,
	NVM_OCSSD_SPEC_20 = 20,
};

struct ppa_addr {
	/* Generic structure for all addresses */
	union {
		/* generic device format */
		struct {
			u64 ch		: NVM_GEN_CH_BITS;
			u64 lun		: NVM_GEN_LUN_BITS;
			u64 blk		: NVM_GEN_BLK_BITS;
			u64 reserved	: NVM_GEN_RESERVED;
		} a;

		/* 1.2 device format */
		struct {
			u64 ch		: NVM_GEN_CH_BITS;
			u64 lun		: NVM_GEN_LUN_BITS;
			u64 blk		: NVM_GEN_BLK_BITS;
			u64 pg		: NVM_12_PG_BITS;
			u64 pl		: NVM_12_PL_BITS;
			u64 sec		: NVM_12_SEC_BITS;
			u64 reserved	: NVM_12_RESERVED;
		} g;

		/* 2.0 device format */
		struct {
			u64 grp		: NVM_GEN_CH_BITS;
			u64 pu		: NVM_GEN_LUN_BITS;
			u64 chk		: NVM_GEN_BLK_BITS;
			u64 sec		: NVM_20_SEC_BITS;
			u64 reserved	: NVM_20_RESERVED;
		} m;

		struct {
			u64 line	: 63;
			u64 is_cached	: 1;
		} c;

		u64 ppa;
	};
};

struct nvm_rq;
struct nvm_id;
struct nvm_dev;
struct nvm_tgt_dev;
struct nvm_chk_meta;

typedef int (nvm_id_fn)(struct nvm_dev *);
typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, struct nvm_chk_meta *,
								sector_t, int);
typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *);
typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *);
typedef void (nvm_destroy_dma_pool_fn)(void *);
typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
								dma_addr_t *);
typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);

struct nvm_dev_ops {
	nvm_id_fn		*identity;
	nvm_op_bb_tbl_fn	*get_bb_tbl;
	nvm_op_set_bb_fn	*set_bb_tbl;

	nvm_get_chk_meta_fn	*get_chk_meta;

	nvm_submit_io_fn	*submit_io;
	nvm_submit_io_sync_fn	*submit_io_sync;

	nvm_create_dma_pool_fn	*create_dma_pool;
	nvm_destroy_dma_pool_fn	*destroy_dma_pool;
	nvm_dev_dma_alloc_fn	*dev_dma_alloc;
	nvm_dev_dma_free_fn	*dev_dma_free;
};

#ifdef CONFIG_NVM

#include <linux/blkdev.h>
#include <linux/file.h>
#include <linux/dmapool.h>
#include <uapi/linux/lightnvm.h>

enum {
	/* HW Responsibilities */
	NVM_RSP_L2P	= 1 << 0,
	NVM_RSP_ECC	= 1 << 1,

	/* Physical Adressing Mode */
	NVM_ADDRMODE_LINEAR	= 0,
	NVM_ADDRMODE_CHANNEL	= 1,

	/* Plane programming mode for LUN */
	NVM_PLANE_SINGLE	= 1,
	NVM_PLANE_DOUBLE	= 2,
	NVM_PLANE_QUAD		= 4,

	/* Status codes */
	NVM_RSP_SUCCESS		= 0x0,
	NVM_RSP_NOT_CHANGEABLE	= 0x1,
	NVM_RSP_ERR_FAILWRITE	= 0x40ff,
	NVM_RSP_ERR_EMPTYPAGE	= 0x42ff,
	NVM_RSP_ERR_FAILECC	= 0x4281,
	NVM_RSP_ERR_FAILCRC	= 0x4004,
	NVM_RSP_WARN_HIGHECC	= 0x4700,

	/* Device opcodes */
	NVM_OP_PWRITE		= 0x91,
	NVM_OP_PREAD		= 0x92,
	NVM_OP_ERASE		= 0x90,

	/* PPA Command Flags */
	NVM_IO_SNGL_ACCESS	= 0x0,
	NVM_IO_DUAL_ACCESS	= 0x1,
	NVM_IO_QUAD_ACCESS	= 0x2,

	/* NAND Access Modes */
	NVM_IO_SUSPEND		= 0x80,
	NVM_IO_SLC_MODE		= 0x100,
	NVM_IO_SCRAMBLE_ENABLE	= 0x200,

	/* Block Types */
	NVM_BLK_T_FREE		= 0x0,
	NVM_BLK_T_BAD		= 0x1,
	NVM_BLK_T_GRWN_BAD	= 0x2,
	NVM_BLK_T_DEV		= 0x4,
	NVM_BLK_T_HOST		= 0x8,

	/* Memory capabilities */
	NVM_ID_CAP_SLC		= 0x1,
	NVM_ID_CAP_CMD_SUSPEND	= 0x2,
	NVM_ID_CAP_SCRAMBLE	= 0x4,
	NVM_ID_CAP_ENCRYPT	= 0x8,

	/* Memory types */
	NVM_ID_FMTYPE_SLC	= 0,
	NVM_ID_FMTYPE_MLC	= 1,

	/* Device capabilities */
	NVM_ID_DCAP_BBLKMGMT	= 0x1,
	NVM_UD_DCAP_ECC		= 0x2,
};

struct nvm_id_lp_mlc {
	u16	num_pairs;
	u8	pairs[886];
};

struct nvm_id_lp_tbl {
	__u8	id[8];
	struct nvm_id_lp_mlc mlc;
};

struct nvm_addrf_12 {
	u8	ch_len;
	u8	lun_len;
	u8	blk_len;
	u8	pg_len;
	u8	pln_len;
	u8	sec_len;

	u8	ch_offset;
	u8	lun_offset;
	u8	blk_offset;
	u8	pg_offset;
	u8	pln_offset;
	u8	sec_offset;

	u64	ch_mask;
	u64	lun_mask;
	u64	blk_mask;
	u64	pg_mask;
	u64	pln_mask;
	u64	sec_mask;
};

struct nvm_addrf {
	u8	ch_len;
	u8	lun_len;
	u8	chk_len;
	u8	sec_len;
	u8	rsv_len[2];

	u8	ch_offset;
	u8	lun_offset;
	u8	chk_offset;
	u8	sec_offset;
	u8	rsv_off[2];

	u64	ch_mask;
	u64	lun_mask;
	u64	chk_mask;
	u64	sec_mask;
	u64	rsv_mask[2];
};

enum {
	/* Chunk states */
	NVM_CHK_ST_FREE =	1 << 0,
	NVM_CHK_ST_CLOSED =	1 << 1,
	NVM_CHK_ST_OPEN =	1 << 2,
	NVM_CHK_ST_OFFLINE =	1 << 3,

	/* Chunk types */
	NVM_CHK_TP_W_SEQ =	1 << 0,
	NVM_CHK_TP_W_RAN =	1 << 1,
	NVM_CHK_TP_SZ_SPEC =	1 << 4,
};

/*
 * Note: The structure size is linked to nvme_nvm_chk_meta such that the same
 * buffer can be used when converting from little endian to cpu addressing.
 */
struct nvm_chk_meta {
	u8	state;
	u8	type;
	u8	wi;
	u8	rsvd[5];
	u64	slba;
	u64	cnlb;
	u64	wp;
};

struct nvm_target {
	struct list_head list;
	struct nvm_tgt_dev *dev;
	struct nvm_tgt_type *type;
	struct gendisk *disk;
};

#define ADDR_EMPTY (~0ULL)

#define NVM_TARGET_DEFAULT_OP (101)
#define NVM_TARGET_MIN_OP (3)
#define NVM_TARGET_MAX_OP (80)

#define NVM_VERSION_MAJOR 1
#define NVM_VERSION_MINOR 0
#define NVM_VERSION_PATCH 0

#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */

struct nvm_rq;
typedef void (nvm_end_io_fn)(struct nvm_rq *);

struct nvm_rq {
	struct nvm_tgt_dev *dev;

	struct bio *bio;

	union {
		struct ppa_addr ppa_addr;
		dma_addr_t dma_ppa_list;
	};

	struct ppa_addr *ppa_list;

	void *meta_list;
	dma_addr_t dma_meta_list;

	nvm_end_io_fn *end_io;

	uint8_t opcode;
	uint16_t nr_ppas;
	uint16_t flags;

	u64 ppa_status; /* ppa media status */
	int error;

	int is_seq; /* Sequential hint flag. 1.2 only */

	void *private;
};

static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
{
	return pdu - sizeof(struct nvm_rq);
}

static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
{
	return rqdata + 1;
}

enum {
	NVM_BLK_ST_FREE =	0x1,	/* Free block */
	NVM_BLK_ST_TGT =	0x2,	/* Block in use by target */
	NVM_BLK_ST_BAD =	0x8,	/* Bad block */
};

/* Instance geometry */
struct nvm_geo {
	/* device reported version */
	u8	major_ver_id;
	u8	minor_ver_id;

	/* kernel short version */
	u8	version;

	/* instance specific geometry */
	int num_ch;
	int num_lun;		/* per channel */

	/* calculated values */
	int all_luns;		/* across channels */
	int all_chunks;		/* across channels */

	int op;			/* over-provision in instance */

	sector_t total_secs;	/* across channels */

	/* chunk geometry */
	u32	num_chk;	/* chunks per lun */
	u32	clba;		/* sectors per chunk */
	u16	csecs;		/* sector size */
	u16	sos;		/* out-of-band area size */

	/* device write constrains */
	u32	ws_min;		/* minimum write size */
	u32	ws_opt;		/* optimal write size */
	u32	mw_cunits;	/* distance required for successful read */
	u32	maxoc;		/* maximum open chunks */
	u32	maxocpu;	/* maximum open chunks per parallel unit */

	/* device capabilities */
	u32	mccap;

	/* device timings */
	u32	trdt;		/* Avg. Tread (ns) */
	u32	trdm;		/* Max Tread (ns) */
	u32	tprt;		/* Avg. Tprog (ns) */
	u32	tprm;		/* Max Tprog (ns) */
	u32	tbet;		/* Avg. Terase (ns) */
	u32	tbem;		/* Max Terase (ns) */

	/* generic address format */
	struct nvm_addrf addrf;

	/* 1.2 compatibility */
	u8	vmnt;
	u32	cap;
	u32	dom;

	u8	mtype;
	u8	fmtype;

	u16	cpar;
	u32	mpos;

	u8	num_pln;
	u8	pln_mode;
	u16	num_pg;
	u16	fpg_sz;
};

/* sub-device structure */
struct nvm_tgt_dev {
	/* Device information */
	struct nvm_geo geo;

	/* Base ppas for target LUNs */
	struct ppa_addr *luns;

	struct request_queue *q;

	struct nvm_dev *parent;
	void *map;
};

struct nvm_dev {
	struct nvm_dev_ops *ops;

	struct list_head devices;

	/* Device information */
	struct nvm_geo geo;

	unsigned long *lun_map;
	void *dma_pool;

	/* Backend device */
	struct request_queue *q;
	char name[DISK_NAME_LEN];
	void *private_data;

	void *rmap;

	struct mutex mlock;
	spinlock_t lock;

	/* target management */
	struct list_head area_list;
	struct list_head targets;
};

static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &dev->geo;
	struct ppa_addr l;

	if (geo->version == NVM_OCSSD_SPEC_12) {
		struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;

		l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
		l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
		l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
		l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
		l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
		l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
	} else {
		struct nvm_addrf *lbaf = &geo->addrf;

		l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
		l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
		l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
		l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
	}

	return l;
}

static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &dev->geo;
	struct ppa_addr l;

	l.ppa = 0;

	if (geo->version == NVM_OCSSD_SPEC_12) {
		struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;

		l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
		l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
		l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
		l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
		l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
		l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
	} else {
		struct nvm_addrf *lbaf = &geo->addrf;

		l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
		l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
		l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
		l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
	}

	return l;
}

typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
typedef sector_t (nvm_tgt_capacity_fn)(void *);
typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
				int flags);
typedef void (nvm_tgt_exit_fn)(void *, bool);
typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);

enum {
	NVM_TGT_F_DEV_L2P = 0,
	NVM_TGT_F_HOST_L2P = 1 << 0,
};

struct nvm_tgt_type {
	const char *name;
	unsigned int version[3];
	int flags;

	/* target entry points */
	nvm_tgt_make_rq_fn *make_rq;
	nvm_tgt_capacity_fn *capacity;

	/* module-specific init/teardown */
	nvm_tgt_init_fn *init;
	nvm_tgt_exit_fn *exit;

	/* sysfs */
	nvm_tgt_sysfs_init_fn *sysfs_init;
	nvm_tgt_sysfs_exit_fn *sysfs_exit;

	/* For internal use */
	struct list_head list;
	struct module *owner;
};

extern int nvm_register_tgt_type(struct nvm_tgt_type *);
extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);

extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);

extern struct nvm_dev *nvm_alloc_dev(int);
extern int nvm_register(struct nvm_dev *);
extern void nvm_unregister(struct nvm_dev *);


extern int nvm_get_chunk_meta(struct nvm_tgt_dev *tgt_dev,
			      struct nvm_chk_meta *meta, struct ppa_addr ppa,
			      int nchks);

extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *,
			      int, int);
extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
extern void nvm_end_io(struct nvm_rq *);
extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int);
extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *);

#else /* CONFIG_NVM */
struct nvm_dev_ops;

static inline struct nvm_dev *nvm_alloc_dev(int node)
{
	return ERR_PTR(-EINVAL);
}
static inline int nvm_register(struct nvm_dev *dev)
{
	return -EINVAL;
}
static inline void nvm_unregister(struct nvm_dev *dev) {}
#endif /* CONFIG_NVM */
#endif /* LIGHTNVM.H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
cd9e9808 MB	2	#ifndef NVM_H
	3	#define NVM_H
	4
b76eb20b	5	#include <linux/blkdev.h>
a7fd9a4f	6	#include <linux/types.h>
b76eb20b	7	#include <uapi/linux/lightnvm.h>
a7fd9a4f	8
cd9e9808 MB	9	enum {
	10	NVM_IO_OK = 0,
	11	NVM_IO_REQUEUE = 1,
	12	NVM_IO_DONE = 2,
	13	NVM_IO_ERR = 3,
	14
	15	NVM_IOTYPE_NONE = 0,
	16	NVM_IOTYPE_GC = 1,
	17	};
	18
69471513 JG	19	/* common format */
	20	#define NVM_GEN_CH_BITS (8)
	21	#define NVM_GEN_LUN_BITS (8)
	22	#define NVM_GEN_BLK_BITS (16)
	23	#define NVM_GEN_RESERVED (32)
	24
	25	/* 1.2 format */
	26	#define NVM_12_PG_BITS (16)
	27	#define NVM_12_PL_BITS (4)
	28	#define NVM_12_SEC_BITS (4)
	29	#define NVM_12_RESERVED (8)
	30
	31	/* 2.0 format */
	32	#define NVM_20_SEC_BITS (24)
	33	#define NVM_20_RESERVED (8)
a7fd9a4f	34
f1d4e812 JG	35	enum {
	36	NVM_OCSSD_SPEC_12 = 12,
	37	NVM_OCSSD_SPEC_20 = 20,
	38	};
	39
a7fd9a4f JA	40	struct ppa_addr {
	41	/* Generic structure for all addresses */
	42	union {
69471513	43	/* generic device format */
a7fd9a4f	44	struct {
69471513 JG	45	u64 ch : NVM_GEN_CH_BITS;
	46	u64 lun : NVM_GEN_LUN_BITS;
	47	u64 blk : NVM_GEN_BLK_BITS;
	48	u64 reserved : NVM_GEN_RESERVED;
	49	} a;
	50
	51	/* 1.2 device format */
	52	struct {
	53	u64 ch : NVM_GEN_CH_BITS;
	54	u64 lun : NVM_GEN_LUN_BITS;
	55	u64 blk : NVM_GEN_BLK_BITS;
	56	u64 pg : NVM_12_PG_BITS;
	57	u64 pl : NVM_12_PL_BITS;
	58	u64 sec : NVM_12_SEC_BITS;
	59	u64 reserved : NVM_12_RESERVED;
a7fd9a4f JA	60	} g;
a7fd9a4f JA	61
69471513 JG	62	/* 2.0 device format */
	63	struct {
	64	u64 grp : NVM_GEN_CH_BITS;
	65	u64 pu : NVM_GEN_LUN_BITS;
	66	u64 chk : NVM_GEN_BLK_BITS;
	67	u64 sec : NVM_20_SEC_BITS;
	68	u64 reserved : NVM_20_RESERVED;
	69	} m;
	70
df414b33 MB	71	struct {
	72	u64 line : 63;
	73	u64 is_cached : 1;
	74	} c;
	75
a7fd9a4f JA	76	u64 ppa;
	77	};
	78	};
	79
	80	struct nvm_rq;
	81	struct nvm_id;
	82	struct nvm_dev;
8e53624d	83	struct nvm_tgt_dev;
a294c199	84	struct nvm_chk_meta;
a7fd9a4f	85
e46f4e48	86	typedef int (nvm_id_fn)(struct nvm_dev *);
e11903f5	87	typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev , struct ppa_addr, u8 );
00ee6cc3	88	typedef int (nvm_op_set_bb_fn)(struct nvm_dev , struct ppa_addr , int, int);
a294c199 JG	89	typedef int (nvm_get_chk_meta_fn)(struct nvm_dev , struct nvm_chk_meta ,
a294c199 JG	90	sector_t, int);
a7fd9a4f	91	typedef int (nvm_submit_io_fn)(struct nvm_dev , struct nvm_rq );
1a94b2d4	92	typedef int (nvm_submit_io_sync_fn)(struct nvm_dev , struct nvm_rq );
a7fd9a4f JA	93	typedef void (nvm_create_dma_pool_fn)(struct nvm_dev , char *);
	94	typedef void (nvm_destroy_dma_pool_fn)(void *);
	95	typedef void (nvm_dev_dma_alloc_fn)(struct nvm_dev , void *, gfp_t,
	96	dma_addr_t *);
	97	typedef void (nvm_dev_dma_free_fn)(void , void, dma_addr_t);
	98
	99	struct nvm_dev_ops {
	100	nvm_id_fn *identity;
a7fd9a4f JA	101	nvm_op_bb_tbl_fn *get_bb_tbl;
	102	nvm_op_set_bb_fn *set_bb_tbl;
	103
a294c199 JG	104	nvm_get_chk_meta_fn *get_chk_meta;
a294c199 JG	105
a7fd9a4f	106	nvm_submit_io_fn *submit_io;
1a94b2d4	107	nvm_submit_io_sync_fn *submit_io_sync;
a7fd9a4f JA	108
	109	nvm_create_dma_pool_fn *create_dma_pool;
	110	nvm_destroy_dma_pool_fn *destroy_dma_pool;
	111	nvm_dev_dma_alloc_fn *dev_dma_alloc;
	112	nvm_dev_dma_free_fn *dev_dma_free;
a7fd9a4f JA	113	};
a7fd9a4f JA	114
cd9e9808 MB	115	#ifdef CONFIG_NVM
	116
	117	#include <linux/blkdev.h>
cd9e9808 MB	118	#include <linux/file.h>
cd9e9808 MB	119	#include <linux/dmapool.h>
e3eb3799	120	#include <uapi/linux/lightnvm.h>
cd9e9808 MB	121
	122	enum {
	123	/* HW Responsibilities */
	124	NVM_RSP_L2P = 1 << 0,
	125	NVM_RSP_ECC = 1 << 1,
	126
	127	/* Physical Adressing Mode */
	128	NVM_ADDRMODE_LINEAR = 0,
	129	NVM_ADDRMODE_CHANNEL = 1,
	130
	131	/* Plane programming mode for LUN */
d5bdec8d MB	132	NVM_PLANE_SINGLE = 1,
	133	NVM_PLANE_DOUBLE = 2,
	134	NVM_PLANE_QUAD = 4,
cd9e9808 MB	135
	136	/* Status codes */
	137	NVM_RSP_SUCCESS = 0x0,
	138	NVM_RSP_NOT_CHANGEABLE = 0x1,
	139	NVM_RSP_ERR_FAILWRITE = 0x40ff,
	140	NVM_RSP_ERR_EMPTYPAGE = 0x42ff,
402ab9a8	141	NVM_RSP_ERR_FAILECC = 0x4281,
38ea2f76	142	NVM_RSP_ERR_FAILCRC = 0x4004,
402ab9a8	143	NVM_RSP_WARN_HIGHECC = 0x4700,
cd9e9808 MB	144
cd9e9808 MB	145	/* Device opcodes */
cd9e9808 MB	146	NVM_OP_PWRITE = 0x91,
	147	NVM_OP_PREAD = 0x92,
	148	NVM_OP_ERASE = 0x90,
	149
	150	/* PPA Command Flags */
	151	NVM_IO_SNGL_ACCESS = 0x0,
	152	NVM_IO_DUAL_ACCESS = 0x1,
	153	NVM_IO_QUAD_ACCESS = 0x2,
	154
57b4bd06	155	/* NAND Access Modes */
cd9e9808 MB	156	NVM_IO_SUSPEND = 0x80,
cd9e9808 MB	157	NVM_IO_SLC_MODE = 0x100,
a7737f39	158	NVM_IO_SCRAMBLE_ENABLE = 0x200,
57b4bd06 MB	159
	160	/* Block Types */
	161	NVM_BLK_T_FREE = 0x0,
	162	NVM_BLK_T_BAD = 0x1,
b5d4acd4 MB	163	NVM_BLK_T_GRWN_BAD = 0x2,
	164	NVM_BLK_T_DEV = 0x4,
	165	NVM_BLK_T_HOST = 0x8,
f9a99950 MB	166
	167	/* Memory capabilities */
	168	NVM_ID_CAP_SLC = 0x1,
	169	NVM_ID_CAP_CMD_SUSPEND = 0x2,
	170	NVM_ID_CAP_SCRAMBLE = 0x4,
	171	NVM_ID_CAP_ENCRYPT = 0x8,
ca5927e7 MB	172
	173	/* Memory types */
	174	NVM_ID_FMTYPE_SLC = 0,
	175	NVM_ID_FMTYPE_MLC = 1,
bf643185 MB	176
	177	/* Device capabilities */
	178	NVM_ID_DCAP_BBLKMGMT = 0x1,
	179	NVM_UD_DCAP_ECC = 0x2,
ca5927e7 MB	180	};
	181
	182	struct nvm_id_lp_mlc {
	183	u16 num_pairs;
	184	u8 pairs[886];
	185	};
	186
	187	struct nvm_id_lp_tbl {
	188	__u8 id[8];
	189	struct nvm_id_lp_mlc mlc;
cd9e9808 MB	190	};
cd9e9808 MB	191
e46f4e48	192	struct nvm_addrf_12 {
c6ac3f35	193	u8 ch_len;
c6ac3f35	194	u8 lun_len;
c6ac3f35	195	u8 blk_len;
c6ac3f35	196	u8 pg_len;
e46f4e48	197	u8 pln_len;
a40afad9	198	u8 sec_len;
c6ac3f35	199
e46f4e48 JG	200	u8 ch_offset;
	201	u8 lun_offset;
	202	u8 blk_offset;
	203	u8 pg_offset;
	204	u8 pln_offset;
a40afad9	205	u8 sec_offset;
fae7fae4	206
e46f4e48 JG	207	u64 ch_mask;
	208	u64 lun_mask;
	209	u64 blk_mask;
	210	u64 pg_mask;
	211	u64 pln_mask;
	212	u64 sec_mask;
	213	};
62771fe0	214
e46f4e48 JG	215	struct nvm_addrf {
	216	u8 ch_len;
	217	u8 lun_len;
	218	u8 chk_len;
	219	u8 sec_len;
	220	u8 rsv_len[2];
c6ac3f35	221
e46f4e48 JG	222	u8 ch_offset;
	223	u8 lun_offset;
	224	u8 chk_offset;
	225	u8 sec_offset;
	226	u8 rsv_off[2];
	227
	228	u64 ch_mask;
	229	u64 lun_mask;
	230	u64 chk_mask;
	231	u64 sec_mask;
	232	u64 rsv_mask[2];
	233	};
cd9e9808	234
32ef9412 JG	235	enum {
	236	/* Chunk states */
	237	NVM_CHK_ST_FREE = 1 << 0,
	238	NVM_CHK_ST_CLOSED = 1 << 1,
	239	NVM_CHK_ST_OPEN = 1 << 2,
	240	NVM_CHK_ST_OFFLINE = 1 << 3,
	241
	242	/* Chunk types */
	243	NVM_CHK_TP_W_SEQ = 1 << 0,
	244	NVM_CHK_TP_W_RAN = 1 << 1,
	245	NVM_CHK_TP_SZ_SPEC = 1 << 4,
	246	};
	247
a294c199 JG	248	/*
	249	* Note: The structure size is linked to nvme_nvm_chk_meta such that the same
	250	* buffer can be used when converting from little endian to cpu addressing.
	251	*/
	252	struct nvm_chk_meta {
	253	u8 state;
	254	u8 type;
	255	u8 wi;
	256	u8 rsvd[5];
	257	u64 slba;
	258	u64 cnlb;
	259	u64 wp;
	260	};
	261
cd9e9808 MB	262	struct nvm_target {
cd9e9808 MB	263	struct list_head list;
8e79b5cb	264	struct nvm_tgt_dev *dev;
cd9e9808 MB	265	struct nvm_tgt_type *type;
	266	struct gendisk *disk;
	267	};
	268
cd9e9808 MB	269	#define ADDR_EMPTY (~0ULL)
cd9e9808 MB	270
e5392739 JG	271	#define NVM_TARGET_DEFAULT_OP (101)
	272	#define NVM_TARGET_MIN_OP (3)
	273	#define NVM_TARGET_MAX_OP (80)
	274
cd9e9808 MB	275	#define NVM_VERSION_MAJOR 1
	276	#define NVM_VERSION_MINOR 0
	277	#define NVM_VERSION_PATCH 0
	278
89a09c56 MB	279	#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
89a09c56 MB	280
91276162	281	struct nvm_rq;
72d256ec	282	typedef void (nvm_end_io_fn)(struct nvm_rq *);
91276162	283
cd9e9808	284	struct nvm_rq {
8e53624d	285	struct nvm_tgt_dev *dev;
cd9e9808 MB	286
	287	struct bio *bio;
	288
	289	union {
	290	struct ppa_addr ppa_addr;
	291	dma_addr_t dma_ppa_list;
	292	};
	293
	294	struct ppa_addr *ppa_list;
	295
003fad37 JG	296	void *meta_list;
003fad37 JG	297	dma_addr_t dma_meta_list;
cd9e9808	298
91276162 MB	299	nvm_end_io_fn *end_io;
91276162 MB	300
cd9e9808	301	uint8_t opcode;
6d5be959	302	uint16_t nr_ppas;
cd9e9808	303	uint16_t flags;
72d256ec	304
9f867268	305	u64 ppa_status; /* ppa media status */
72d256ec	306	int error;
06894efe	307
d7b68016 MB	308	int is_seq; /* Sequential hint flag. 1.2 only */
d7b68016 MB	309
06894efe	310	void *private;
cd9e9808 MB	311	};
	312
	313	static inline struct nvm_rq nvm_rq_from_pdu(void pdu)
	314	{
	315	return pdu - sizeof(struct nvm_rq);
	316	}
	317
	318	static inline void nvm_rq_to_pdu(struct nvm_rq rqdata)
	319	{
	320	return rqdata + 1;
	321	}
	322
ff0e498b JG	323	enum {
ff0e498b JG	324	NVM_BLK_ST_FREE = 0x1, /* Free block */
077d2389	325	NVM_BLK_ST_TGT = 0x2, /* Block in use by target */
ff0e498b	326	NVM_BLK_ST_BAD = 0x8, /* Bad block */
cd9e9808 MB	327	};
cd9e9808 MB	328
e46f4e48	329	/* Instance geometry */
8e79b5cb	330	struct nvm_geo {
e46f4e48	331	/* device reported version */
3cb98f84 JG	332	u8 major_ver_id;
3cb98f84 JG	333	u8 minor_ver_id;
e46f4e48	334
f1d4e812 JG	335	/* kernel short version */
	336	u8 version;
	337
e46f4e48	338	/* instance specific geometry */
a40afad9 JG	339	int num_ch;
a40afad9 JG	340	int num_lun; /* per channel */
fae7fae4	341
e46f4e48 JG	342	/* calculated values */
	343	int all_luns; /* across channels */
	344	int all_chunks; /* across channels */
	345
	346	int op; /* over-provision in instance */
	347
	348	sector_t total_secs; /* across channels */
	349
	350	/* chunk geometry */
a40afad9	351	u32 num_chk; /* chunks per lun */
e46f4e48 JG	352	u32 clba; /* sectors per chunk */
	353	u16 csecs; /* sector size */
	354	u16 sos; /* out-of-band area size */
cd9e9808	355
e46f4e48 JG	356	/* device write constrains */
	357	u32 ws_min; /* minimum write size */
	358	u32 ws_opt; /* optimal write size */
	359	u32 mw_cunits; /* distance required for successful read */
3f48021b JG	360	u32 maxoc; /* maximum open chunks */
3f48021b JG	361	u32 maxocpu; /* maximum open chunks per parallel unit */
fae7fae4	362
e46f4e48 JG	363	/* device capabilities */
e46f4e48 JG	364	u32 mccap;
fae7fae4	365
e46f4e48 JG	366	/* device timings */
	367	u32 trdt; /* Avg. Tread (ns) */
	368	u32 trdm; /* Max Tread (ns) */
	369	u32 tprt; /* Avg. Tprog (ns) */
	370	u32 tprm; /* Max Tprog (ns) */
	371	u32 tbet; /* Avg. Terase (ns) */
	372	u32 tbem; /* Max Terase (ns) */
e5392739	373
e46f4e48 JG	374	/* generic address format */
e46f4e48 JG	375	struct nvm_addrf addrf;
fae7fae4	376
e46f4e48 JG	377	/* 1.2 compatibility */
	378	u8 vmnt;
	379	u32 cap;
	380	u32 dom;
	381
	382	u8 mtype;
	383	u8 fmtype;
	384
	385	u16 cpar;
	386	u32 mpos;
	387
	388	u8 num_pln;
a40afad9	389	u8 pln_mode;
e46f4e48 JG	390	u16 num_pg;
e46f4e48 JG	391	u16 fpg_sz;
8e79b5cb JG	392	};
8e79b5cb JG	393
ade69e24	394	/* sub-device structure */
8e79b5cb JG	395	struct nvm_tgt_dev {
	396	/* Device information */
	397	struct nvm_geo geo;
	398
8e53624d JG	399	/* Base ppas for target LUNs */
	400	struct ppa_addr *luns;
	401
8e79b5cb JG	402	struct request_queue *q;
8e79b5cb JG	403
959e911b	404	struct nvm_dev *parent;
8e53624d	405	void *map;
8e79b5cb JG	406	};
	407
	408	struct nvm_dev {
	409	struct nvm_dev_ops *ops;
	410
	411	struct list_head devices;
	412
8e79b5cb JG	413	/* Device information */
8e79b5cb JG	414	struct nvm_geo geo;
cd9e9808	415
da1e2849	416	unsigned long *lun_map;
75b85649	417	void *dma_pool;
cd9e9808	418
cd9e9808 MB	419	/* Backend device */
	420	struct request_queue *q;
	421	char name[DISK_NAME_LEN];
40267efd	422	void *private_data;
e3eb3799	423
8e53624d JG	424	void *rmap;
8e53624d JG	425
e3eb3799	426	struct mutex mlock;
4c9dacb8	427	spinlock_t lock;
ade69e24 MB	428
	429	/* target management */
	430	struct list_head area_list;
	431	struct list_head targets;
cd9e9808 MB	432	};
cd9e9808 MB	433
7100d50a	434	static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
dab8ee9e	435	struct ppa_addr r)
cd9e9808	436	{
7100d50a	437	struct nvm_geo *geo = &dev->geo;
cd9e9808 MB	438	struct ppa_addr l;
cd9e9808 MB	439
69471513 JG	440	if (geo->version == NVM_OCSSD_SPEC_12) {
	441	struct nvm_addrf_12 ppaf = (struct nvm_addrf_12 )&geo->addrf;
	442
	443	l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
	444	l.ppa \|= ((u64)r.g.lun) << ppaf->lun_offset;
	445	l.ppa \|= ((u64)r.g.blk) << ppaf->blk_offset;
	446	l.ppa \|= ((u64)r.g.pg) << ppaf->pg_offset;
	447	l.ppa \|= ((u64)r.g.pl) << ppaf->pln_offset;
	448	l.ppa \|= ((u64)r.g.sec) << ppaf->sec_offset;
	449	} else {
	450	struct nvm_addrf *lbaf = &geo->addrf;
	451
	452	l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
	453	l.ppa \|= ((u64)r.m.pu) << lbaf->lun_offset;
	454	l.ppa \|= ((u64)r.m.chk) << lbaf->chk_offset;
	455	l.ppa \|= ((u64)r.m.sec) << lbaf->sec_offset;
	456	}
cd9e9808 MB	457
	458	return l;
	459	}
	460
7100d50a	461	static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
dab8ee9e	462	struct ppa_addr r)
cd9e9808	463	{
7100d50a	464	struct nvm_geo *geo = &dev->geo;
cd9e9808 MB	465	struct ppa_addr l;
cd9e9808 MB	466
5389a1df	467	l.ppa = 0;
e46f4e48	468
69471513 JG	469	if (geo->version == NVM_OCSSD_SPEC_12) {
	470	struct nvm_addrf_12 ppaf = (struct nvm_addrf_12 )&geo->addrf;
	471
	472	l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
	473	l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
	474	l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
	475	l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
	476	l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
	477	l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
	478	} else {
	479	struct nvm_addrf *lbaf = &geo->addrf;
	480
	481	l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
	482	l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
	483	l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
	484	l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
	485	}
cd9e9808 MB	486
	487	return l;
	488	}
	489
dece1635	490	typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue , struct bio );
cd9e9808	491	typedef sector_t (nvm_tgt_capacity_fn)(void *);
4af3f75d JG	492	typedef void (nvm_tgt_init_fn)(struct nvm_tgt_dev , struct gendisk *,
4af3f75d JG	493	int flags);
a7c9e910	494	typedef void (nvm_tgt_exit_fn)(void *, bool);
9a69b0ed JG	495	typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
9a69b0ed JG	496	typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
cd9e9808	497
656e33ca MB	498	enum {
	499	NVM_TGT_F_DEV_L2P = 0,
	500	NVM_TGT_F_HOST_L2P = 1 << 0,
	501	};
	502
cd9e9808 MB	503	struct nvm_tgt_type {
	504	const char *name;
	505	unsigned int version[3];
656e33ca	506	int flags;
cd9e9808 MB	507
	508	/* target entry points */
	509	nvm_tgt_make_rq_fn *make_rq;
	510	nvm_tgt_capacity_fn *capacity;
cd9e9808 MB	511
	512	/* module-specific init/teardown */
	513	nvm_tgt_init_fn *init;
	514	nvm_tgt_exit_fn *exit;
	515
9a69b0ed JG	516	/* sysfs */
	517	nvm_tgt_sysfs_init_fn *sysfs_init;
	518	nvm_tgt_sysfs_exit_fn *sysfs_exit;
	519
cd9e9808 MB	520	/* For internal use */
cd9e9808 MB	521	struct list_head list;
90014829	522	struct module *owner;
cd9e9808 MB	523	};
cd9e9808 MB	524
6063fe39 SL	525	extern int nvm_register_tgt_type(struct nvm_tgt_type *);
6063fe39 SL	526	extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
cd9e9808 MB	527
	528	extern void nvm_dev_dma_alloc(struct nvm_dev , gfp_t, dma_addr_t *);
	529	extern void nvm_dev_dma_free(struct nvm_dev , void , dma_addr_t);
	530
b0b4e09c MB	531	extern struct nvm_dev *nvm_alloc_dev(int);
	532	extern int nvm_register(struct nvm_dev *);
	533	extern void nvm_unregister(struct nvm_dev *);
cd9e9808	534
a294c199 JG	535
	536	extern int nvm_get_chunk_meta(struct nvm_tgt_dev *tgt_dev,
	537	struct nvm_chk_meta *meta, struct ppa_addr ppa,
	538	int nchks);
	539
333ba053 JG	540	extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr ,
333ba053 JG	541	int, int);
8e53624d	542	extern int nvm_submit_io(struct nvm_tgt_dev , struct nvm_rq );
1a94b2d4	543	extern int nvm_submit_io_sync(struct nvm_tgt_dev , struct nvm_rq );
06894efe	544	extern void nvm_end_io(struct nvm_rq *);
22e8c976	545	extern int nvm_bb_tbl_fold(struct nvm_dev , u8 , int);
333ba053	546	extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr, u8 );
e3eb3799	547
cd9e9808 MB	548	#else /* CONFIG_NVM */
	549	struct nvm_dev_ops;
	550
b0b4e09c MB	551	static inline struct nvm_dev *nvm_alloc_dev(int node)
	552	{
	553	return ERR_PTR(-EINVAL);
	554	}
	555	static inline int nvm_register(struct nvm_dev *dev)
cd9e9808 MB	556	{
	557	return -EINVAL;
	558	}
b0b4e09c	559	static inline void nvm_unregister(struct nvm_dev *dev) {}
cd9e9808 MB	560	#endif /* CONFIG_NVM */
cd9e9808 MB	561	#endif /* LIGHTNVM.H */